JP2009005007A - Communication equipment and communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To transmit multi-bit data within one clock cycle through one signal line. <P>SOLUTION: The communication equipment comprises: a delay circuit 120 for generating a plurality of delay signals within one cycle of a reference clock by a plurality of delay elements; an encoder 101 for determining a set of rise timing and fall timing within one pulse of the reference clock for digital data; a selection circuit 150 for selecting delay signals of the determined one set of rise timing and fall timing; and a pulse generation circuit 160 for generating pulse signals from the delay signal corresponding to the rise timing and the delay signal corresponding to the fall timing which are selected in the selection circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a communication apparatus and a communication system, and more particularly, to a communication circuit and a communication system capable of generating and transmitting a set of rising and falling timing pulse signals according to digital data within one reference clock cycle. .

Various digital circuits require a clock for circuit operation. This clock is generated by various types of clock generation circuits.
Data transfer is performed by H and L pulse signals based on this clock. Therefore, when performing high-speed data transfer, it is necessary to prepare a high-speed clock.

  As digital modulation / demodulation methods in wireless communication, three methods of ASK (Amplitude Shift Keying), FSK (Frequency Shift Keying), and PSK (Phase Shift Keying) are known. As applications of PSK, there are BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), and the like.

These modulate the phase of a high-frequency carrier having a constant frequency with a baseband signal.
Data transmission is also disclosed in the following patent documents.
Japanese Patent Publication 8-31797 (first page, Fig. 1) JP2003-174484 (first page, FIG. 1)

  The above-described technologies such as PSK are used for digital wireless communications such as mobile communications, broadcasting, and modems. The high-speed transmission technology using such a carrier requires a high-frequency modulation / demodulation circuit, is not suitable for signal transmission inside one apparatus, is greatly affected by high-frequency noise, and is an expensive system.

  Further, in Patent Document 1 described above, this is to transmit and receive the pulse width in units of clocks. Although this is a basic principle, a high-frequency clock pulse is required for high-speed communication.

  In the data transmission system of Patent Document 2 described above, the phases of the pulse signal for communication and the clock pulse are compared, but basically in units of clocks. That is, a clock pulse having a frequency proportional to the communication pulse signal is required.

As described above, in order to perform high-speed communication using a pulse signal, a clock pulse having a frequency proportional to the pulse signal is required.
Note that conventional data transmission using signal lines includes general serial I / F and parallel I / F. In serial transmission, transmission is possible with one signal line, but several clocks are required to transmit multi-bit data. In parallel transmission, although multi-bit data can be transmitted with one clock, a plurality of signal lines corresponding to the number of bits are required.

  The present invention has been made to solve the above-described problem, and in a general transmission system in the frequency band of a baseband signal, multi-bit data is transferred to one clock using one signal line. It is an object of the present invention to provide a communication device and a communication system capable of transmitting a plurality of bits within a network.

The above-described problems are solved by the following invention.
(1) The invention described in claim 1 is a communication apparatus for generating and transmitting a pulse signal in accordance with input digital data, and a plurality of delays having different timings within one reference clock cycle by a plurality of delay elements. A delay circuit that generates a signal; an encoder that determines a set of rising and falling timings in accordance with input digital data within one cycle of the reference clock; and a set of rising edges determined by the encoder A selection circuit that selects a timing and a fall timing from the output of the delay circuit, and a pulse generation circuit that generates a pulse signal within one cycle of a reference clock by a set of rise timing and fall timing selected by the selection circuit And a communication device. Here, the selection circuit selects a delay signal at a timing determined by the encoder, and the pulse generation circuit generates a pulse signal based on the selected delay signal.

  (2) The invention according to claim 2 is a delay value measuring circuit that obtains the number of stages of the delay signal corresponding to one cycle of the reference clock as the number of synchronization stages, and obtains a delay time per delay element from the number of synchronization stages; A timing calculation circuit that refers to the delay time per stage of the delay element and performs a timing calculation to obtain the number of stages of the delay signal according to a set of rising timing and falling timing determined by the encoder; The communication device according to claim 1, wherein the selection circuit selects the delay signal according to the number of stages of the delay signal obtained by the timing calculation.

  (3) The invention described in claim 3 is a communication device that receives an input pulse signal and converts the pulse signal into digital data, and the timing is different within one cycle of the reference clock by a plurality of delay elements. A delay circuit that generates a plurality of delay signals, and the number of stages of the delay signals that match the rising timing and falling timing of a set of the pulse signals in accordance with the input pulse signal within one cycle of the reference clock. And a decoder for converting the number of stages of the delay signal detected by the pulse timing detection circuit into predetermined digital data.

  (4) The invention described in claim 4 includes a delay value measuring circuit that obtains the number of stages of the delay signal corresponding to one cycle of the reference clock as the number of synchronization stages, and obtains the delay time per delay element from the number of synchronization stages. The decoder refers to the delay time per delay element and the number of stages of the delay signal detected by the timing detection circuit, and extracts predetermined digital data. A communication apparatus according to claim 3.

  (5) The invention according to claim 5 transmits or receives digital data of a plurality of bits within one cycle of the reference clock by using a pulse signal having a set of rising timing and falling timing within one cycle of the reference clock. The communication device according to claim 1, wherein the communication device is a communication device.

  (6) The invention according to claim 6 is a transmission side communication device for generating and transmitting a pulse signal according to input digital data, and receiving the input pulse signal and converting the pulse signal into digital data. A communication system that performs communication with a receiving communication device that includes a delay circuit that generates a plurality of delay signals having different timings within one cycle of a reference clock by a plurality of delay elements, and a reference clock An encoder that determines a set of rise timing and fall timing according to input digital data within one period, and a set of rise timing and fall timing determined by the encoder A selection circuit to be selected from the output, and a set of rising timing and falling edge selected by the selection circuit are And a pulse generation circuit that generates a pulse signal within one cycle of the reference clock according to timing, and the receiving-side communication device receives a plurality of delay signals with different timings within one cycle of the reference clock by a plurality of delay elements. A delay circuit to be generated, and pulse timing detection that outputs the number of stages of the delay signal that matches the rising timing and falling timing of a set of the pulse signal in accordance with the input pulse signal within one cycle of the reference clock A communication system comprising: a circuit; and a decoder that converts the number of stages of the delay signal detected by the pulse timing detection circuit into predetermined digital data. Here, the selection circuit selects a delay signal at a timing determined by the encoder, and the pulse generation circuit generates a pulse signal based on the selected delay signal.

  (7) In the invention according to claim 7, the transmission side communication apparatus obtains the number of stages of the delay signal corresponding to one cycle of the reference clock as the number of synchronization stages, and calculates the delay time per delay element from the number of synchronization stages. Timing for calculating a delay value measurement circuit to be obtained and timing calculation for obtaining the number of stages of the delay signal according to a set of rising timing and falling timing determined by the encoder with reference to the delay time per delay element 7. The communication system according to claim 6, further comprising an arithmetic circuit, wherein the selection circuit selects the delay signal according to the number of stages of the delay signal obtained by the timing calculation.

  (8) In the invention according to claim 8, the receiving-side communication device obtains the number of stages of the delay signal corresponding to one cycle of the reference clock as the number of synchronization stages, and calculates the delay time per delay element from the number of synchronization stages. A delay value measuring circuit to be obtained, wherein the decoder extracts predetermined digital data by referring to the delay time per stage of the delay element and the number of stages of the delay signal detected by the timing detection circuit; The communication device according to claim 6, wherein the communication device is a communication device.

  (9) According to the ninth aspect of the invention, by using a pulse signal having a set of rising timing and falling timing within one cycle of the reference clock, digital data of a plurality of bits is transmitted or received within one cycle of the reference clock. The communication system according to any one of claims 6 to 8, wherein:

  (10) The invention according to claim 10 includes the transmission-side communication device and the reception-side communication device between a plurality of substrates in the image processing device, and a set of rising timings and rises within one reference clock cycle. The communication system according to any one of claims 6 to 9, wherein communication is performed using a pulse signal having a falling timing.

According to the present invention described above, the following effects can be obtained.
(1) In the first aspect of the present invention, when a set of rising and falling timing pulse signals are generated and transmitted according to digital data within one reference clock cycle, a plurality of cascaded delays are connected. A plurality of delay signals having different timings within one cycle of the reference clock are generated by the element, digital data is determined at one set of rising timing and falling timing within one pulse of the reference clock, and the determined set The delay signal corresponding to the rise timing and the fall timing is selected, and the digital signal is selected from the delay signal corresponding to the rise timing and the delay signal corresponding to the fall timing. A set of rising timings within one cycle of the reference clock determined according to the data Generating a pulse signal of grayed and fall timing.

  The above communication device does not require a clock having a frequency higher than that of the reference clock, and can generate a set of rise timing and fall timing pulse signals according to digital data within one cycle of the reference clock. In a general transmission system in a baseband signal frequency band, a plurality of bits can be transmitted within one clock using a single signal line.

  (2) In the invention of claim 2, the number of stages of the delay signal corresponding to one cycle of the reference clock is obtained as the number of synchronization stages, the delay time per stage of the delay element is obtained from the number of synchronization stages, and the delay time is referred to The timing calculation for obtaining the number of stages of the delayed signal according to the set of rise timing and fall timing determined by the encoder is performed, and the delay signal is selected according to the obtained number of stages of the delayed signal. Therefore, a high-accuracy delay element is not used, a clock having a higher frequency than the reference clock is not required, and a set of pulse signals having a rising timing and a falling timing within one reference clock cycle according to digital data. In general transmission systems in the frequency band of baseband signals, Using one signal line data, it can be transmitted plurality of bits in one clock.

  That is, by calculating the delay time from the number of synchronization stages in this way, even when using a delay element that has a characteristic that the delay time changes due to various factors such as temperature, time, power supply voltage, and individual element differences, the reference clock is used. A set of rising and falling timing pulse signals can be handled within one cycle of the reference clock with high accuracy without requiring a high frequency clock.

  (3) In the invention according to claim 3, when digital data is extracted from a set of rise timing and fall timing pulse signals within one cycle of the reference clock, the reference clock 1 is connected by a plurality of cascaded delay elements. A plurality of delayed signals having different timings within a cycle are generated, and the rising timing and the rising timing are determined according to an external pulse signal having a set of rising timing and falling timing within one reference clock cycle. The falling timing is detected, and predetermined digital data is extracted from the number of stages of the delayed signal corresponding to the detected rising timing and falling timing.

  With the above communication apparatus, digital data can be extracted (demodulated) from a set of rise timing and fall timing pulse signals within one cycle of the reference clock without requiring a clock having a higher frequency than the reference clock. In a general transmission system in a baseband signal frequency band, a plurality of bits can be transmitted within one clock using a single signal line for multi-bit data.

  (4) In the invention according to claim 4, the number of stages of the delay signal corresponding to one cycle of the reference clock is obtained as the number of synchronization stages, and the delay time per stage of the delay element is obtained from the number of synchronization stages. The delay time and the number of stages of the delay signal selected by the selection circuit are referred to, and predetermined digital data is extracted. Therefore, without using a high-accuracy delay element, the reference clock is used. Digital data can be extracted (demodulated) from a set of rising and falling timing pulse signals within one reference clock cycle without the need for a high frequency clock. In a general transmission system, multiple bits of data can be transmitted in a single clock using a single signal line.

  That is, by calculating the delay time from the number of synchronization stages in this way, even when using a delay element that has a characteristic that the delay time changes due to various factors such as temperature, time, power supply voltage, and individual element differences, the reference clock is used. A set of rising and falling timing pulse signals can be handled within one cycle of the reference clock with high accuracy without requiring a high frequency clock.

  (5) In the invention according to claim 5, digital data of a plurality of bits is transmitted or received within one cycle of the reference clock using a pulse signal having a set of rising timing and falling timing within one cycle of the reference clock. Therefore, in a general transmission system in the frequency band of the baseband signal, multi-bit data can be transmitted in a plurality of bits within one clock using a single signal line.

  (6) In the invention according to claim 6, in the transmission side communication device in the communication system, when generating and transmitting a set of rise timing and fall timing pulse signals according to digital data within one cycle of the reference clock. In addition, a plurality of delay signals having different timings within one cycle of the reference clock are generated by a plurality of cascaded delay elements, and digital data is generated at a set of rising timing and falling timing within one pulse of the reference clock. In accordance with the determined set of rise timing and fall timing, a delay signal having a corresponding timing is selected, and the delay signal and fall timing corresponding to the rise timing thus selected are selected. A reference determined according to the digital data from the corresponding delay signal Lock for generating a pulse signal of a pair of the rising timing and falling timing in one cycle.

  In the communication device on the receiving side in the communication system, when digital data is extracted from a set of rise timing and fall timing pulse signals within one cycle of the reference clock, the reference clock 1 is connected by a plurality of cascaded delay elements. A plurality of delayed signals having different timings within a cycle are generated, and the rising timing and the rising timing are determined according to an external pulse signal having a set of rising timing and falling timing within one reference clock cycle. The falling timing is detected, and predetermined digital data is extracted from the number of stages of the delayed signal corresponding to the detected rising timing and falling timing.

  With the above communication device on the transmitting side, a set of rise and fall timing pulse signals can be generated in accordance with digital data within one cycle of the reference clock without requiring a clock having a higher frequency than the reference clock. The receiving-side communication device can extract (demodulate) digital data from a set of rise timing and fall timing pulse signals within one cycle of the reference clock without requiring a clock having a higher frequency than the reference clock. Therefore, in a general transmission system in the baseband signal frequency band, multi-bit data can be transmitted (transmitted to received) within one clock using a single signal line.

  (7) In the invention according to claim 7, the transmission side communication apparatus in the communication system obtains the number of stages of the delay signal corresponding to one cycle of the reference clock as the number of synchronization stages, and based on the number of synchronization stages, the delay time per delay element stage Referring to the delay time, a timing calculation is performed to determine the number of stages of the delayed signal according to the set of rising timing and falling timing determined by the encoder, and the delay is determined according to the determined number of stages of the delayed signal. Since the signal is selected, a set of rise and fall timings are used within one cycle of the reference clock without using a high-accuracy delay element and without requiring a clock having a higher frequency than the reference clock. Since the timing pulse signal can be generated according to the digital data, In Do transmission system, the multi-bit data using one signal line can transmit multiple bits in one clock.

  That is, by calculating the delay time from the number of synchronization stages in this way, even when using a delay element that has a characteristic that the delay time changes due to various factors such as temperature, time, power supply voltage, and individual element differences, the reference clock is used. A set of rising and falling timing pulse signals can be handled within one cycle of the reference clock with high accuracy without requiring a high frequency clock.

  (8) In the invention according to claim 8, the receiving-side communication apparatus in the communication system obtains the number of stages of the delay signal corresponding to one cycle of the reference clock as the number of synchronization stages, and based on the number of synchronization stages, delay per delay element stage The time is obtained and the delay time per stage of the delay element and the number of stages of the delay signal selected by the selection circuit are referred to extract predetermined digital data. Because digital data can be extracted (demodulated) from a set of rising and falling timing pulse signals within one cycle of the reference clock without using a clock having a higher frequency than the reference clock. In a general transmission system in a baseband signal frequency band, multi-bit data is transmitted by one clock using one signal line. Multiple bits can be transmitted within.

  That is, by calculating the delay time from the number of synchronization stages in this way, even when using a delay element that has a characteristic that the delay time changes due to various factors such as temperature, time, power supply voltage, and individual element differences, the reference clock is used. A set of rising and falling timing pulse signals can be handled within one cycle of the reference clock with high accuracy without requiring a high frequency clock.

  (9) In the invention according to claim 9, in the communication system, a plurality of bits of digital data within one cycle of the reference clock using a pulse signal having a set of rising timing and falling timing within one cycle of the reference clock. Therefore, in a general transmission system in the baseband signal frequency band, multiple bits of data can be transmitted in a single clock using a single signal line.

  (10) In the invention according to claim 10, the communication system is applied between a plurality of substrates in the image processing apparatus, and a pulse signal having a set of rising timing and falling timing within one cycle of the reference clock is used. In order to transmit / receive digital data of multiple bits within one cycle of the reference clock, in a general transmission system in the frequency band of the baseband signal, multi-bit data is transmitted within one clock using one signal line Can transmit multiple bits.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a block diagram showing a circuit configuration of a communication circuit according to a first embodiment of the present invention. Here, FIG. 1A shows a communication circuit 100 on the transmission side in the communication system, and FIG. 1B shows a communication circuit 200 on the reception side in the communication system.

  In the communication circuit 100 shown in FIG. 1A, reference numeral 101 denotes an encoder that controls each unit and generates rising timing data and falling timing data from image data. The rise timing data and the fall timing data are timing data indicating at which timing of the reference clock the rise / fall of the pulse signal occurs.

  Reference numeral 110 denotes a clock generation circuit that generates a reference clock that serves as a reference for the operation of each part of the apparatus. In this embodiment, a set of rise timing and fall timing pulse signals is generated in accordance with digital data using a delay signal within one cycle of the reference clock, so that it depends on the pulse signal used for data transmission. There is no need to increase the frequency of the reference clock.

  A delay circuit 120 includes a delay element group configured by cascading delay elements having a small delay time in order to obtain a plurality of delay signals by finely delaying the reference clock by a predetermined amount. Here, in the delay circuit 120, it is preferable that the delay elements are cascade-connected in a chain shape so that the delay signals having slightly different phases can be generated over about two cycles of the reference clock.

  A delay value measuring circuit 130 measures the delay value of each delay signal generated by the delay circuit 120. The delay value measurement circuit 130 obtains a delay time per delay element as a delay value from the number of synchronization stages of the delay signal synchronized with the reference clock among the plurality of delay signals. This delay value is supplied from the delay value measuring circuit 130 to a timing arithmetic circuit described later.

  For example, a semiconductor digital delay element manufactured by a C-MOS process is used as the cascaded delay element. In this case, the delay value of the delay element inside the semiconductor may vary by about 0.5 to 2 times due to factors such as temperature, power supply voltage, and chip-to-chip variations. However, the relative delay difference (in-chip variation) of the delay amounts of the plurality of delay elements is as small as about ± 3% at the maximum inside the chip. Therefore, using such physical characteristics, the absolute delay variation is corrected by calculation using the measurement result of the delay value measurement circuit 130.

  Reference numeral 140a denotes a rise timing calculation circuit that refers to the delay value and the rise timing data to determine the number of stages of the delay signal that matches the rise timing data. Reference numeral 140b denotes a fall timing calculation circuit that refers to the delay value and the fall timing data and determines the number of stages of the delay signal that matches the fall timing data.

Reference numeral 150a denotes a rise selection circuit that selects one of the delayed signals from the delay circuit 120 as the rise signal according to the determination of the rise timing arithmetic circuit 140a.
Reference numeral 150b denotes a fall selection circuit that selects one of the delayed signals from the delay circuit 120 as a fall signal in accordance with the decision of the fall timing calculation circuit 140b.

  Reference numeral 160 denotes a pulse generation circuit that executes a pulse generation process that generates a pulse signal that rises by the above rising signal and falls by the above falling signal, and outputs the generated pulse signal to the outside.

  In the communication circuit 200 shown in FIG. 1B, reference numeral 210 denotes a clock generation circuit that generates a reference clock that serves as a reference for the operation of each part of the apparatus. In this embodiment, a set of rise timing and fall timing pulse signals are demodulated using a delay signal within one cycle of the reference clock. Therefore, the frequency of the reference clock is set according to the pulse signal used for data transmission. There is no need to raise it.

  A delay circuit 220 includes a delay element group configured by cascading delay elements having small delay times in order to obtain a plurality of delay signals by finely delaying the reference clock by a predetermined amount. Here, in the delay circuit 220, it is preferable that the delay elements are cascade-connected in a chain shape so that delay signals having slightly different phases can be generated over about two cycles of the reference clock.

  Reference numeral 230 denotes a delay value measurement circuit that measures the delay value of each delay signal generated by the delay circuit 120. The delay value measurement circuit 230 obtains the delay time per delay element as a delay value from the number of synchronization stages of the delay signal synchronized with the reference clock among the plurality of delay signals. This delay value is supplied from the delay value measuring circuit 230 to various circuits to be described later.

  For example, a semiconductor digital delay element manufactured by a C-MOS process is used as the cascaded delay element. In this case, the delay value of the delay element inside the semiconductor may vary by about 0.5 to 2 times due to factors such as temperature, power supply voltage, and chip-to-chip variations. However, the relative delay difference (in-chip variation) of the delay amounts of the plurality of delay elements is as small as about ± 3% at the maximum inside the chip. Therefore, using such physical characteristics, the absolute delay variation is corrected by calculation using the measurement result of the delay value measurement circuit 130.

  Reference numeral 240a selects a delay signal from the delay circuit 120 having a timing that coincides with the rising timing of the received pulse signal, and information on the number of stages of the selected delay signal counted from the rising edge of the reference clock. It is a timing arithmetic circuit to output.

  Reference numeral 240b selects a delay signal from the delay circuit 120 having a timing that coincides with the falling timing of the received pulse signal, and information on the number of stages of the selected delay signal counted from the rising edge of the reference clock. Is a timing arithmetic circuit that outputs.

  Reference numeral 260 denotes a decoder that extracts digital data predetermined for the pulse signal from the number of stages of the delay signal at the rising timing of the pulse signal, the number of stages of the delay signal at the falling timing of the pulse signal, and the delay value described above.

  In the above configuration, the delay circuit 120 and the delay circuit 220 generate delay signals that are slightly different in phase, for example, as shown in FIG. FIG. 2 shows a part of the delay signal DLn where n is the number of delay stages.

  Here, the delay value measuring circuit 130 is between a first synchronization point (DL20 in FIG. 2) and a second synchronization point (DL280 in FIG. 2) synchronized with the reference clock among the plurality of delay signals. The number of stages of the delay signal is obtained as the number of synchronization stages (280 stages−20 stages = 260 stages in FIG. 2), and the number of stages per delay element of the delay circuit 120 is determined from the period of the reference clock and the number of stages of the delay signal (number of synchronization stages). The delay time is obtained as a delay value.

  By doing this, even if the delay time per delay element changes due to temperature, power supply voltage, individual delay element differences, etc., the delay time per delay element is calculated backward from the reference clock of crystal oscillation accuracy. In other words, it is possible to calculate an accurate delay time at that time.

  On the other hand, the encoder 101 receives the digital data, refers to a table of the relationship between the predetermined digital data and the pulse signal, and outputs rising timing data and falling timing data corresponding to the digital data.

Here, in the present embodiment, as an example of the pulse signal predetermined for the digital data, it is as shown in FIG.
Here, an example in which the reference clock is used with 8 resolutions is shown as a specific example.

In this embodiment, in order to prevent connection with the preceding and following pulse signals, a certain empty space is provided at the start position and the end position of the pulse signal as shown in FIG.
Since the resolution is 8, the minimum pulse is 1/8 of the reference clock as shown in FIG. 3 (2), and the minimum pulse (1/8 pulse) to the maximum pulse (6/8 pulse) And also gives information to changes in the position of 1/8 pulse to 5/8 pulse.

  That is, six types (FIGS. 3 (b) to (g)) due to the difference in the position of the 1/8 pulse, and five types (FIGS. 3 (h) to (l)) according to the difference in the position of the 2/8 pulse, 3 / 4 types (Figs. 3 (m) to (p)) due to differences in the positions of 8 pulses, 3 types (Figs. 3 (q) to (s)) due to differences in positions of 4/8 pulses, and 5/8 pulse positions Depending on the difference, a total of 21 patterns of two types (FIG. 3 (t) to (u)) and one type of 6/8 pulse (FIG. 3 (v)) are possible.

  Note that the number of patterns z ′ when the resolution is z can be obtained as a sum from 1 to (z−2). For example, 21 patterns at the above 8 resolution, 36 patterns at 10 resolution, 105 patterns at 16 resolution, 171 patterns at 20 resolution, 465 patterns at 32 resolution, and 595 patterns at 36 resolution. Yes, it is 741 patterns at 40 resolution, and 1953 patterns at 64 resolution.

  In addition, since the communication circuit 100 on the transmission side and the communication circuit 200 on the reception side both transmit data with the correct phase relationship, a predetermined synchronization signal or the like is transmitted at a predetermined time and a predetermined number of data at the start of communication. It is desirable to transmit and receive during standby.

  Further, as the synchronization signal, for example, a pulse signal combined with FIG. 3B and FIG. 3G, a pulse signal combined with FIG. 3H and FIG. It is a pattern different from the pulse signal used for normal data transmission, such as a pulse signal combined with 3 (m) and FIG. 3 (l), and a pattern in which the phase state can be recognized within one cycle of the reference clock. It is desirable to be.

  The encoder 101 of the communication circuit 100 on the transmission side generates rising timing data indicating at which timing it rises in order to generate the pulse signal as shown in FIG. 3, and supplies it to the timing arithmetic circuit 140a. In the case of the 8 resolution shown in FIG. 3, if one pulse of the reference clock is divided into 8 and there is a timing of 0/8 to 8/8, one of the rising timing data of 1/8 to 6/8 is obtained. Generate rising timing data of any one of 2/8 to 7/8.

  The timing calculation circuit 140a receives the number of delay stages from the delay value measurement circuit 130 and the rising timing data, and calculates the number of delay element stages of the delay circuit that matches the rising timing by calculation. Further, the timing calculation circuit 140b receives the number of delay stages from the delay value measurement circuit 130 and the falling timing data, and calculates the number of delay element stages of the delay circuit that matches the falling timing by calculation.

  For example, when generating the pulse signal of FIG. 3B determined as predetermined digital data, the delay signal synchronized with the clock pulse first is the 50th stage, and then the delay signal synchronized with the clock pulse is the 290th stage. In this case, in the timing arithmetic circuit 140a that has received the timing data of the reference clock 1/8, 50+ (290-50) × 1/8 = 80, and the selection signal SEL80 for selecting the 80th stage delay signal is used. To the selection circuit 150a.

  In the timing arithmetic circuit 140a that receives the timing data of the reference clock 2/8, 50+ (290-50) × 2/8 = 110, and the selection signal SEL110 for selecting the 110th stage delay signal is It outputs to the selection circuit 150b. As a result, the pulse generation circuit 160 generates a pulse signal corresponding to FIG. 3B from the delay signal of the 80th stage selected by the selection circuit 150a and the delay signal of the 110th stage selected by the selection circuit 150b. And output.

  Further, when the same pulse signal of FIG. 3B is generated and the delay time of the delay element changes depending on the temperature or the power supply voltage, for example, the delay signal first synchronized with the clock pulse is the 66th stage. When the delay signal synchronized with the clock pulse is in the 330th stage, 66+ (330−66) × 1/8 = 99 in the timing arithmetic circuit 140a that has received the timing data of the reference clock 1/8. A selection signal SEL99 for selecting the delay signal at the stage is output to the selection circuit 150a.

  Then, in the timing arithmetic circuit 140a that receives the timing data of the reference clock 2/8, 66+ (330−66) × 2/8 = 126, and the selection signal SEL126 for selecting the 126th stage delay signal is It outputs to the selection circuit 150b. As a result, the pulse generation circuit 160 generates a pulse signal corresponding to FIG. 3B from the 99th stage delay signal selected by the selection circuit 150a and the 126th stage delay signal selected by the selection circuit 150b. And output.

  The above communication device 100 does not require a clock having a frequency higher than that of the reference clock, and can generate a set of rise timing and fall timing pulse signals in accordance with digital data within one cycle of the reference clock. In a general transmission system in a baseband signal frequency band, a plurality of bits can be transmitted within one clock using a single signal line for multi-bit data.

  And by calculating the delay time from the number of synchronization stages in this way, even when using a delay element that has a characteristic that the delay time changes due to various factors such as temperature, time, power supply voltage, and individual element differences, the reference clock is used. A set of rising and falling timing pulse signals can be handled within one cycle of the reference clock with high accuracy without requiring a high frequency clock.

  In the communication circuit 200 on the reception side, for example, when the delay signal synchronized first with the clock pulse is at the 40th stage and the delay signal synchronized with the clock pulse is at the 280th stage, the communication circuit 200 on the reception side When the rising edge of the received pulse signal matches the delay signal 80th stage in the timing arithmetic circuit 240a, the timing arithmetic circuit 240a has (70-40) / (280-40) = 1/8, and UP (1 / 8) is output to the decoder 260. When the falling edge of the pulse signal received by the communication circuit 200 on the receiving side coincides with the 110th stage of the delayed signal in the timing arithmetic circuit 240b, the timing arithmetic circuit 240a determines (110-50) / (280-40) = 2. / 8, and DOWN (2/8) is output to the decoder 260. As a result, it can be seen that the pulse signal of FIG. 3B has been received, and the decoder extracts predetermined digital data.

  When a pulse signal having the same timing is received and the delay time of the delay element changes depending on the temperature or the power supply voltage, for example, the delay signal first synchronized with the clock pulse is received by the communication circuit 200 on the receiving side. Is the 56th stage, and then the delay signal synchronized with the clock pulse is the 320th stage, the rising edge of the pulse signal received by the communication circuit 200 on the receiving side becomes the 89th stage of the delayed signal by the timing arithmetic circuit 240a. If they match, the timing calculation circuit 240 a outputs (99−56) / (320−56) = 1/8, and outputs UP (1/8) to the decoder 260.

  When the falling edge of the pulse signal received by the communication circuit 200 on the receiving side coincides with the 110th stage of the delayed signal in the timing arithmetic circuit 240b, the timing arithmetic circuit 240a determines (122-56) / (320-56) = 2/8, and DOWN (2/8) is output to the decoder 260. As a result, it can be seen that the pulse signal of FIG. 3B has been received, and the decoder extracts predetermined digital data.

  The above communication device 200 does not require a clock having a frequency higher than that of the reference clock, and receives a set of rise timing and fall timing pulse signals generated in accordance with digital data within one cycle of the reference clock. Therefore, in a general transmission system in a baseband signal frequency band, a plurality of bits can be received within one clock using a single signal line.

  And by calculating the delay time from the number of synchronization stages in this way, even when using a delay element that has a characteristic that the delay time changes due to various factors such as temperature, time, power supply voltage, and individual element differences, the reference clock is used. A set of rising and falling timing pulse signals can be handled within one cycle of the reference clock with high accuracy without requiring a high frequency clock.

  In addition, the communication system including the communication device 100 and the communication device 200 described above does not require a clock having a frequency higher than the reference clock, and generates a set of rise timing and fall timing pulse signals within one cycle of the reference clock. Since it can be generated according to digital data, multi-bit data can be transmitted in multiple bits within one clock using a single signal line in a general transmission system in the frequency band of a baseband signal. .

  That is, by calculating the delay time from the number of synchronization stages in this way, even when using a delay element that has a characteristic that the delay time changes due to various factors such as temperature, time, power supply voltage, and individual element differences, the reference clock is used. A set of rising and falling timing pulse signals can be handled within one cycle of the reference clock with high accuracy without requiring a high frequency clock.

  A communication system is applied between a plurality of substrates in an image processing apparatus, and digital data of a plurality of bits within one cycle of the reference clock is obtained using a pulse signal having a set of rising timing and falling timing within one cycle of the reference clock. In general transmission systems in the baseband signal frequency band for transmission and reception, multi-bit data can be transmitted in multiple bits within one clock using a single signal line, and EMI is also considered. Will be able to communicate.

<Other embodiments>
In the above embodiment, the synchronization signal is transmitted and received for synchronization between the transmission side and the reception side. Instead of this, or in addition to this, for example, the pulse signals of all patterns in FIG. 3 are transmitted and received in a predetermined order. It is also possible to use this for synchronization.

  In addition, by sequentially transmitting and receiving the pulse signals of all patterns in this way, it is possible to match the resolution and communication standards of the transmission side and the reception side. Note that the resolution and communication standard may be notified from the transmission side to the reception side at the start of communication.

  In the above embodiment, it is not necessary that the frequencies of the reference clocks on the transmission side and the reception side match if the ability to perform communication with a predetermined resolution exists. For example, if each pattern of the pulse signal in FIG. 3 can be identified, the receiving-side communication circuit 200 can extract digital data by a decoder even if the clock pulse cycle is not the same as that in FIG. .

  Even when this embodiment is applied using a delay element whose delay time does not change due to various factors such as temperature, time, power supply voltage, and individual element differences, good data transmission can be performed. In this case, the delay value measuring circuit 130 and the delay value measuring circuit 230 are not necessary.

  Further, in the above data transmission, various known error corrections can be applied, and the system is not limited.

1 is a configuration diagram illustrating an overall configuration of an image forming apparatus according to an exemplary embodiment of the present invention. 6 is a time chart for explaining the operation of the image forming apparatus according to the embodiment of the present invention. 6 is a time chart for explaining the operation of the image forming apparatus according to the embodiment of the present invention.

Explanation of symbols

100 Transmission side communication circuit 101 Encoder 110 Clock generation circuit 120 Delay circuit 130 Delay value measurement circuit 140a Timing calculation circuit 140b Timing calculation circuit 150a Selection circuit 150b Selection circuit 160 Pulse generation circuit 200 Reception side communication circuit 210 Clock generation circuit 220 Delay Circuit 230 Delay value measurement circuit 240a Timing operation circuit 240b Timing operation circuit 260 Decoder

Claims (10)

A communication device for generating and transmitting a pulse signal according to input digital data,
A delay circuit that generates a plurality of delay signals having different timings within one cycle of the reference clock by a plurality of delay elements;
An encoder that determines a set of rising and falling timings in accordance with input digital data within one reference clock cycle;
A selection circuit that selects a set of rising and falling timings determined by the encoder from the output of the delay circuit;
A pulse generation circuit that generates a pulse signal within one cycle of a reference clock according to a set of rise timing and fall timing selected by the selection circuit;
A communication device. A delay value measuring circuit that obtains the number of stages of the delay signal corresponding to one cycle of a reference clock as the number of synchronization stages, and obtains a delay time per delay element from the number of synchronization stages;
A timing calculation circuit that refers to the delay time per stage of the delay element and performs a timing calculation to obtain the number of stages of the delay signal according to a set of rising timing and falling timing determined by the encoder;
The selection circuit selects the delay signal according to the number of stages of the delay signal obtained by the timing calculation.
The communication apparatus according to claim 1. A communication device that receives an input pulse signal and converts the pulse signal into digital data,
A delay circuit that generates a plurality of delay signals having different timings within one cycle of the reference clock by a plurality of delay elements;
A pulse timing detection circuit that outputs the number of stages of the delayed signal that matches each of the rising timing and falling timing of a set of the pulse signal in accordance with the input pulse signal within one reference clock cycle;
A decoder that converts the number of stages of the delay signal detected by the pulse timing detection circuit into predetermined digital data;
A communication device. A delay value measuring circuit that obtains the number of stages of the delay signal corresponding to one cycle of a reference clock as the number of synchronization stages, and obtains a delay time per delay element from the number of synchronization stages;
The decoder refers to the delay time per stage of the delay element and the stage number of the delay signal detected by the timing detection circuit, and extracts predetermined digital data;
The communication device according to claim 3. By using a pulse signal having a set of rising timing and falling timing within one cycle of the reference clock, digital data of a plurality of bits is transmitted or received within one cycle of the reference clock.
The communication device according to any one of claims 1 to 4, wherein the communication device is characterized in that: Communication in which communication is performed by a transmission-side communication device that generates and transmits a pulse signal according to input digital data and a reception-side communication device that receives the input pulse signal and converts the pulse signal into digital data A system,
The transmission side communication device is:
A delay circuit that generates a plurality of delay signals having different timings within one cycle of the reference clock by a plurality of delay elements;
An encoder that determines a set of rising and falling timings in accordance with input digital data within one reference clock cycle;
A selection circuit that selects a set of rising and falling timings determined by the encoder from the output of the delay circuit;
A pulse generation circuit that generates a pulse signal within one cycle of a reference clock according to a set of rise timing and fall timing selected by the selection circuit,
The receiving communication device
A delay circuit that generates a plurality of delay signals having different timings within one cycle of the reference clock by a plurality of delay elements;
A pulse timing detection circuit that outputs the number of stages of the delayed signal that matches each of the rising timing and falling timing of a set of the pulse signal in accordance with the input pulse signal within one reference clock cycle;
A decoder for converting the number of stages of the delay signal detected by the pulse timing detection circuit into predetermined digital data,
A communication system characterized by the above. The transmission side communication device is:
A delay value measuring circuit that obtains the number of stages of the delay signal corresponding to one cycle of a reference clock as the number of synchronization stages, and obtains a delay time per delay element from the number of synchronization stages;
A timing calculation circuit that refers to the delay time per stage of the delay element and performs a timing calculation to obtain the number of stages of the delay signal according to a set of rising timing and falling timing determined by the encoder;
The selection circuit selects the delay signal according to the number of stages of the delay signal obtained by the timing calculation.
The communication system according to claim 6. The receiving communication device is
A delay value measuring circuit that obtains the number of stages of the delay signal corresponding to one cycle of a reference clock as the number of synchronization stages, and obtains a delay time per delay element from the number of synchronization stages;
The decoder refers to the delay time per stage of the delay element and the stage number of the delay signal detected by the timing detection circuit, and extracts predetermined digital data;
The communication apparatus according to claim 6 or 7, characterized in that By using a pulse signal having a set of rising timing and falling timing within one cycle of the reference clock, digital data of a plurality of bits is transmitted or received within one cycle of the reference clock.
The communication system according to any one of claims 6 to 8, wherein the communication system is characterized. Between the plurality of substrates in the image processing apparatus, comprising the transmission side communication device and the reception side communication device,
Communicate using a pulse signal that has a set of rising and falling timings within one cycle of the reference clock.
The communication system according to any one of claims 6 to 9, wherein the communication system is characterized.

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