JP2008516558A - Wireless communication method and apparatus - Google Patents

Abstract

One aspect of the invention relates to operating in a wireless network a device designed to operate in a different wireless network. In one aspect, a device designed to operate in a GSM wireless network can be used for communication in a PHS wireless network.

Description

  The present invention generally relates to wireless communications.

  A simple mobile phone system (PHS) is a lightweight mobile communication system that uses an existing public telephone network by being built on an existing landline network. The PHS network base station coverage radius is significantly narrower than the typical mobile phone network coverage, and because PHS mobile terminals use low-power transmitters, PHS is most suitable for densely populated areas ing. PHS was originally deployed in Japan in the early 1990s and was intended to provide a low-cost alternative to cellular networks. However, PHS has not been commercially successful because of its limited mobility, poor signal quality, and limited ability to operate on a moving vehicle.

Despite the poor response in Japan, PHS has recently been deployed in other densely populated areas of Asia with the aim of providing a low cost alternative to traditional wireless and landline networks.
However, because PHS has not been commercially successful in Japan, hardware manufacturers have invested a lot of money to design and further develop PHS hardware (eg, base stations and mobile terminal chipsets) Be cautious to do. Therefore, it would be desirable to have a wireless device that can operate in a PHS wireless system without spending time and money on the design and development of such a device.

One aspect of the present invention provides a circuit that is designed to operate in a first wireless system in accordance with a first wireless standard and that operates in accordance with a second wireless standard that is different from the first wireless standard. Operating in a wireless system.
Another aspect of the invention relates to a method for determining a symbol boundary of a radio signal of a first radio system that transmits at a first slot rate. The method operates a clock signal circuit configured to operate in a second wireless system transmitting at a second slot rate, and counts a predetermined number of clock pulses of the clock signal to slot. Estimating a boundary, wherein the frequency of the clock signal is not an integer multiple of the first slot rate.

  A further aspect of the invention is a method for utilizing in a first wireless system a wireless device designed to operate in a second wireless system, wherein the wireless device has a data rate. Including a first element that transmits a signal to a second element over an interface, wherein the data rate of the interface is not an integer multiple of a symbol rate of the first wireless system. The method includes: a) determining a data rate of the interface; b) determining a symbol rate of a first wireless system; c) based on the data rate and the symbol rate, the interface at the symbol rate. Determining a sampling rate that allows a signal to be transmitted via; d) determining a time interval for sampling the signal based on the sampling rate to achieve the sampling rate; and e) Providing a fractional interpolator for estimating a signal value in a determined time interval.

  One aspect of the present invention relates to a method for receiving a wireless signal of a simple mobile phone system (PHS). The method demodulates a received signal to generate a baseband waveform: filtering the baseband waveform with a mismatched channel selection filter; and performing coherent detection of the baseband waveform to obtain a baseband waveform Extracting at least one PHS symbol from.

DETAILED DESCRIPTION OF THE INVENTION One aspect of the present invention relates to operating hardware (eg, GSM devices) designed to operate in another cellular network in a PHS network. This can be done in any suitable way. For example, the hardware designed to operate on another mobile phone network may be software programmed to operate on the PHS network.
It is difficult to use the hardware in a mobile phone network other than a network designed to work with some hardware, because the mobile phone network is a network designed to work with the hardware. This is because different timing schemes can be used.

  For example, in many cellular networks, mobile terminals are synchronized to the base station of the cell in which they are located. This timing synchronization allows the mobile terminal to transmit data when the base station expects to receive data from the terminal and expects to receive data from the base station when the base station transmits data. be able to.

  That is, for example, the base station of the first radio system can transmit data to the mobile terminal at a symbol rate of 1000 Hz, and the base station of the second radio system can transmit data to the mobile terminal at a symbol rate of 800 Hz. . A mobile terminal determines the symbol boundary or sampling point of a signal transmitted by a base station (ie, the point at which one symbol ends and the next symbol begins in the signal) based on the symbol rate of the radio system. Can do. If the mobile terminal uses an incorrect symbol rate to determine the symbol boundaries of the signal, the sampled value of the signal can also be incorrect. FIG. 1 shows symbol boundaries of signal 100 for symbol rates of two different wireless systems. In FIG. 1, the symbol boundary of a wireless system having a symbol rate of 1000 Hz is indicated by a solid line and the symbol boundary of a wireless system having a symbol rate of 800 Hz is indicated by a broken line. The signal boundaries for a 1000 Hz radio system occur at 1 ms, 2 ms, 3 ms, 4 ms, 5 ms, 6 ms and 7 ms. The signal boundaries for the 800 Hz radio system occur at 1.25 ms, 2.5 ms, 3.75 ms, 5 ms, 6.25 ms and 7.5 ms. Therefore, if the mobile station determines the value of the signal 100 based on a symbol rate of 1000 Hz, the signal 100 has a binary value of “1110001”, while the mobile station sets the signal value to 800 Hz. If determined based on the symbol rate, the signal will have a binary value of “110011”.

  Thus, as shown in FIG. 1, it is important for a mobile terminal to determine the correct symbol boundary of a signal in order to determine the intended signal value. Accordingly, one aspect of the present invention modifies a hardware timing scheme designed to operate in a first wireless system so that the hardware also operates correctly in a second wireless network. About that. For example, the clock signal used to determine the symbol boundaries of a wireless signal may not be generated by the wireless device's master clock (eg, the fact that the device was designed to operate in a different wireless system). Therefore, a clock signal having a resolution finer than the symbol rate of the wireless signal can be generated by the wireless device and used to determine symbol boundaries of the wireless signal. The determined symbol boundary may not be the actual symbol boundary of the signal, but is sufficiently close to the actual symbol boundary to the extent of tolerance.

  For example, the GSM radio system radio standard defines a symbol rate of 270.083 kHz. A GSM device (eg, a mobile terminal or base station) can include a master clock that operates at a specified frequency and one or more programmable integer dividers. Other clock signals operating at different frequencies can be derived from the master clock signal using, for example, a programmable integer divider. Since the master clock of many GSM devices operates at a frequency of 13 MHz, a clock signal having a symbol rate frequency of 270.083 kHz is obtained using an integer divider that divides the master clock frequency by 48 from the 13 MHz master clock. Can lead.

Similarly, the PHS system wireless standard defines a symbol rate of 192 kHz. The master clock of many PHS devices operates at a frequency of 19.2 MHz, and a clock signal at a symbol rate (ie, 192 kHz) frequency can be derived from the master clock by dividing the master clock frequency by 100. Is possible.
However, when trying to operate a GSM device (eg GSM mobile terminal) in a PHS radio system, a 192 kHz PHS symbol rate is derived from a GSM master clock operating at a frequency of 13 MHz using an integer divider. May not be possible. As shown in Table 1, in order to derive a 192 kHz clock from a 13 MHz clock, division by a non-integer coefficient of 67.7083 is required.

しかし、ＰＨＳおよびＧＳＭなどの無線システムにおいては、基地局と移動体端末との間の時間同期は、データをフレーム、スロットおよびシンボル単位で送信することにより得られる。すなわち、フレームは複数のスロットを含み、フレーム内の各スロットは複数のシンボルを含む。移動体端末と基地局は、フレーム境界、スロット境界およびシンボル境界に基づいて同期する。図２に示すように、ＰＨＳ無線システムにおいては、例えば１つのフレームは８個のスロットを含み、各スロットは１２０個のシンボルを含む。ＰＨＳ標準が定めたフレームレートは２００Ｈｚ（すなわち、１秒当たり２００Ｈｚ）である。したがって、スロットレートは１６００Ｈｚである。２００Ｈｚおよび１６００Ｈｚの周波数を有するクロック信号は、１９．２ＭＨｚのＰＨＳマスタークロックから整数除算器を用いて導くことができる。

However, in wireless systems such as PHS and GSM, time synchronization between the base station and the mobile terminal is obtained by transmitting data in units of frames, slots and symbols. That is, the frame includes a plurality of slots, and each slot in the frame includes a plurality of symbols. The mobile terminal and the base station are synchronized based on the frame boundary, slot boundary, and symbol boundary. As shown in FIG. 2, in a PHS wireless system, for example, one frame includes 8 slots, and each slot includes 120 symbols. The frame rate defined by the PHS standard is 200 Hz (ie, 200 Hz per second). Therefore, the slot rate is 1600 Hz. Clock signals having frequencies of 200 Hz and 1600 Hz can be derived from the 19.2 MHz PHS master clock using an integer divider.

In one implementation of a GSM wireless device, a 13 MHz GSM master clock can be used to drive a software timing engine that generates clock signals for other elements of the wireless device. The software timing engine can have a resolution of 6.5 MHz.
When a GSM device is used in a PHS wireless system, the clock at the frequency of the PHS frame rate can be derived from the software timing engine using, for example, a programmable integer divider. That is, as shown in Table 2, the 6.5 MHz clock of the software timing engine can be divided by a coefficient of 32,500 to realize a clock signal having a frequency of 200 Hz.

したがって、ＧＳＭデバイスは、１３ＭＨｚマスタークロック信号から導かれた２００Ｈｚクロック信号を用いて、送信された無線信号のフレーム境界を決定することができる。しかし、１６００Ｈｚ（すなわち、ＰＨＳスロットレート）の周波数を有するクロック信号は、６．５ＭＨｚクロックから整数除算器を用いて導くことはできない。
本発明の１つの態様において、ソフトウェアタイミングエンジンクロックは、送信されたＰＨＳ信号のスロット境界を決定するために用いることができる。ソフトウェアタイミングエンジンクロックは、厳密にスロット境界上のクロック端を有していない可能性があるが、クロック端は、無線標準により規定されている許容誤差の範囲であるように、スロット境界に十分近くすることができる。

Thus, the GSM device can use the 200 Hz clock signal derived from the 13 MHz master clock signal to determine the frame boundary of the transmitted radio signal. However, a clock signal having a frequency of 1600 Hz (ie PHS slot rate) cannot be derived from a 6.5 MHz clock using an integer divider.
In one aspect of the invention, the software timing engine clock can be used to determine the slot boundaries of the transmitted PHS signal. The software timing engine clock may not have a clock edge exactly on the slot boundary, but the clock edge is close enough to the slot boundary to be within the tolerances specified by the radio standard can do.

  That is, for example, since the PHS slot rate is 1600 Hz, there are 4062.5 clock pulses from the software timing engine clock in each PHS slot, and there are 8125 pulses in every two PHS slots. For example, as shown in FIG. 3, the first PHS slot 301 and the second PHS slot 307 have actual slot boundaries as indicated by reference numeral 303. Clock signal 309 is part of the clock signal generated by the software timing engine. The 4062nd count pulse of the clock signal occurs just before the actual slot boundary 303. Thus, the slot boundary determined using the clock signal 309 (ie, slot boundary 305) occurs immediately before the actual slot boundary 303. However, since the clock pulse of the clock signal 309 occurs every 0.153 μs, the determined slot boundary 305 is at most 0.153 μs before (or after) the actual slot boundary. As mentioned above, the PHS symbol rate is 192 kHz and the length of the PHS symbol is 5.24 μs. Therefore, as shown in Table 3, the determined slot boundary may differ from the actual slot boundary by less than 3% of the length of the PHS slot.

携帯機器の発振器は多くの場合完全に正確ではないため（例えば結晶誤差のため）、無線システムには多くの場合、誤差に対するいくらかの許容範囲が組み込まれる。例えばＰＨＳ無線システムは、送信機に対して２５％までのシンボルピリオドの許容範囲を提供する。６．５ＭＨｚのＧＳＭタイミングエンジンクロック信号の使用から生じる、最悪でも３％未満の誤差は、十分に無線システムに組み込まれた許容範囲内である。ＧＳＭソフトウェアタイミングエンジンクロックを用いて、ＰＨＳ送信信号のスロット境界を決定することにより、ＧＳＭ無線システムで動作するように設計されたデバイスを、ＰＨＳ信号を発生するための送信機で用いることができる。

Since portable device oscillators are often not completely accurate (eg, due to crystal errors), wireless systems often incorporate some tolerance for error. For example, PHS radio systems provide up to 25% symbol period tolerance for transmitters. The worst-case error of less than 3% resulting from the use of a 6.5 MHz GSM timing engine clock signal is well within the tolerances built into the wireless system. By using the GSM software timing engine clock to determine slot boundaries for PHS transmission signals, devices designed to operate in GSM radio systems can be used in transmitters for generating PHS signals.

As mentioned above, there are 8125 clock pulses for every two PHS slots. Therefore, by counting 8125 pulses, the slot boundary of every other PHS slot can be determined. Thus, in the example of FIG. 3, after 4062 clock pulses have occurred, 4063 additional clock pulses can be counted to determine the next slot boundary. According to this method, errors in determining the slot boundary 303 are not accumulated at the next slot boundary.
Although the above example relates to using a GSM device in a PHS radio system, the invention is not limited in this respect because it uses a clock signal having a frequency that is not an integer multiple of the slot rate of the radio system. This is because the above technique for determining slot boundaries in a wireless signal can be used in any wireless system.

Furthermore, in the above example, the GSM system is described as using a 6.5 MHz clock signal, and the PHS system is described as using a 19.2 MHz master clock. It should be understood that the clock frequency of both the GSM clock and the PHS master clock may differ slightly from these values due to oscillator errors.
Furthermore, the present invention is not limited to determining slot boundaries in a radio signal having a symbol rate of 192 KHz using a 6.5 MHz clock. In fact, any clock frequency and slot rate can be used in aspects of the present invention, where the clock frequency is not an integer multiple of the slot rate of the radio signal, and the clock frequency determines slot boundaries within tolerances Provides a sufficient resolution.

Furthermore, in the above example, it has been described that some clock signals are derived from the master clock of GSM and PHS systems using a programmable integer divider. However, the present invention is not limited in this respect because clock signals can be derived from other clock signals in any suitable manner (eg, by division). Further, in embodiments of the invention that use integer dividers, the clock signal need not be divided by one integer divider, because the clock signal can be desired step by step by any suitable number of integer dividers. This is because it is possible to divide the frequency up to.
Furthermore, it should be understood that the above techniques can be used in both base stations and mobile terminals as the invention is not limited in this respect.

Another obstacle that may be encountered when a wireless device designed to operate in the first wireless system is used in the second wireless system is that the transmission path of the wireless device is the first wireless system. Can be clocked at a frequency designed to support the transmission of other signals, but this is not suitable for the transmission of signals in the second radio system.
In this regard, one aspect of the present invention relates to implementing the transmission path of the second wireless system in a device designed to operate in the first wireless system.

  For example, in one aspect of the invention, the mobile terminal 401 shown in FIG. 4 includes a digital baseband processor 403 and an analog baseband processor 405. Digital baseband processor 403 can communicate with analog baseband processor 405 via interface 407. The digital baseband processor 403 can perform functions such as, for example, modulation and demodulation of digital signals, processing of input from a mobile terminal keyboard, power management, and other functions. The analog baseband processor 405 performs functions such as analog / digital conversion, digital / analog conversion, analog and digital signal filtering, and also functions as an interface between the digital baseband processor 403 and the mobile terminal 401 radio. can do.

In order to transmit the signal, the signal can first be processed and modulated by the digital baseband processor 403. The signal can then be transmitted to the analog baseband processor 405 via the interface 407. The analog baseband processor 405 can perform further filtering, rate conversion, and digital / analog conversion of the signal and transmits the signal to the wireless unit of the mobile terminal 401 for transmission.
In one aspect, interface 407 is designed to operate in a GSM radio system and can therefore be clocked at 13 MHz by a GSM master clock. Therefore, the interface 407 transmits data at a rate of 13 Mbps. To sample the signal, both the in-phase component (I) and the quadrature component (Q) of the signal are sampled. Each of these component samples can contain 8 bits, so there are 16 bits for each signal sample. Therefore, as shown in Table 4, the data rate of the interface 407 is 812,500 samples / second.

ＧＳＭシステムにおいて、ＧＳＭ標準により指定されたシンボルレートは２７０．８３ｋＨｚ、または２７０，８３３．３シンボル／秒である。したがって、デジタルベースバンドプロセッサは２７０，８３３．３シンボル／秒のレートでデータを出力することができる。より高いシンボルレートでクロックされるインターフェイスを介してこのシンボルレートでデータを送信することは、該インターフェイスを介して１シンボル当たり複数サンプルを送信することにより実現できる。表５に示すように、１３Ｍｂｐｓリンクを介して２７０，８３３．３シンボル／秒のシンボルレートを達成するには、３サンプル／シンボルを送信すればよい。

In the GSM system, the symbol rate specified by the GSM standard is 270.83 kHz, or 270,833.3 symbols / second. Therefore, the digital baseband processor can output data at a rate of 270, 833.3 symbols / second. Transmitting data at this symbol rate over an interface clocked at a higher symbol rate can be achieved by transmitting multiple samples per symbol over the interface. As shown in Table 5, to achieve a symbol rate of 270,833.3 symbols / second over a 13 Mbps link, 3 samples / symbols may be transmitted.

しかし、ＰＨＳシステムにおいて、ＰＨＳ標準で指定されたシンボルレートは１９２，０００シンボル／秒である。１３Ｍｂｐｓでクロックされるインターフェイス（すなわちインターフェイス４０７）を介してこのシンボルレートでデータを送信すると、表６に示すように、該インターフェイスを介して非整数のサンプル／シンボル（すなわち、４．２３１８サンプル／シンボル）が送信されることになる。

However, in the PHS system, the symbol rate specified by the PHS standard is 192,000 symbols / second. Sending data at this symbol rate over an interface clocked at 13 Mbps (ie, interface 407) will result in non-integer samples / symbols (ie, 4.2318 samples / symbol) over the interface as shown in Table 6. ) Will be sent.

図５は、デジタルベースバンドプロセッサ４０３の機能要素を示すブロック図である。図５に示すように、デジタルベースバンドプロセッサ４０３のモジュレータ５００は、信号の変調を行うＰｉ／４微分求積位相偏移キーイング（ＤＱＰＳＫ）ユニット５０１を含む。ルート・レイズド・コサイン（ＲＲＣ）フィルタ５０５ａおよび５０５ｂは、信号のパルス整形を行うことができ、分数補間器５０７は、フィルタ５０５ａおよび５０５ｂから出力される信号に分数補間を行うことができる。同相成分および直交成分に対して、モジュレータ５００を通る別々の信号経路（すなわち、信号経路Ａおよび信号経路Ｂ）がある。

FIG. 5 is a block diagram showing functional elements of the digital baseband processor 403. As shown in FIG. 5, the modulator 500 of the digital baseband processor 403 includes a Pi / 4 differential quadrature phase shift keying (DQPSK) unit 501 that performs signal modulation. Root raised cosine (RRC) filters 505a and 505b can perform signal pulse shaping, and fractional interpolator 507 can perform fractional interpolation on the signals output from filters 505a and 505b. There are separate signal paths through modulator 500 (ie, signal path A and signal path B) for in-phase and quadrature components.

The oversampling unit 503 can oversample the output signal of the Pi / 4-DQPSK unit 501 by a factor of four. This enables data transmission at a specific symbol rate via an interface having a data rate higher than the symbol rate. For example, if the specific symbol rate is 4 symbols / second and the interface data rate is 16 samples / second, each symbol can be sampled 4 times and each of these samples can be transmitted over the link. Thus, data can be transmitted over the interface at a rate of 16 samples / second, but only 4 symbols per second are transmitted.
In one aspect, functional elements 501, 503, 505a, 505b and 507 may be implemented in software executed by a digital baseband processor. However, the present invention is not limited in this respect because these functions can be implemented by dedicated hardware, software or any combination thereof.

Thus, for example, in the case of the PHS standard where the specified symbol rate is 192K symbols / second, data can be transmitted over the interface at a rate of 768K samples / second by oversampling the symbols with a factor of 4. Become. A symbol rate of 192K symbols / second results in the transfer of one symbol every 5.2083 μs.
FIG. 6 shows an example of a PHS signal waveform over one symbol period. To transfer symbols over the interface at a rate of 768K samples / second, the symbols need only be sampled every 1.3021 μs, resulting in 4 samples per symbol. For example, as shown in FIG. 6, the symbols can be sampled at 1.3021 μs, 2.6042 μs, 3.9063 μs, and 5.2083 μs.

This can be achieved by transferring a different number of samples for the various symbols so that the average number of samples per symbol of all transferred symbols is 4.2318. For example, 4 samples can be transferred across the interface for some symbols and 5 samples can be transferred for other symbols.
As shown in Table 7, the signal may be sampled every 1.2308 μs to achieve an average of 4.2318 samples / symbol. However, as shown in FIG. 6, by oversampling the signal with a coefficient of 4, the signal is sampled every 1.3021 μs. The value of the signal at intervals of 1.2308 μs may be determined by fractional interpolation.

この補間は図５の分数補間器５０７により行うことができる。したがって、分数補間器５０７からの出力データレートは４．２３１８サンプル／シンボルであり、これはインターフェイス４０７を介して、８１２，５００サンプル／秒のレートで、１９２，０００シンボル／秒のシンボルレートで、データの転送を可能とする。

This interpolation can be performed by the fractional interpolator 507 in FIG. Thus, the output data rate from the fractional interpolator 507 is 4.2318 samples / symbol, which is via the interface 407 at a rate of 812,500 samples / second and a symbol rate of 192,000 symbols / second, Enables data transfer.

  FIG. 7 is a block diagram illustrating functional elements of an analog baseband processor 701 in one aspect of the invention. The analog baseband processor includes an 8X interpolator 703, a digital to analog converter (DAC) 705, a switched capacitor filter 707, and an active continuous time domain (CT) filter 709. Once the signal is received via the interface 407, the signal is processed by an 8X interpolator 703 that increases the number of samples per symbol, and a signal input at a data rate of 812,500 samples / second results in 6,500,000. Increased to a data rate of samples / second. This interpolation is done because the DAC 705 is clocked at 6.5 MHz (ie, by dividing the GSM master clock frequency by a factor of 2). After digital / analog conversion, the signal is further filtered by filters 707 and 709 and the signal is then transmitted to the wireless unit for transmission.

In one aspect, the functional elements 703, 705, 707, and 709 can be implemented in analog baseband processor hardware. However, the present invention is not limited in this respect because these functions can be implemented by dedicated hardware, software or any combination thereof.
Although the example described above relates to the use of a device designed to operate in a GSM radio system in a PHS radio system, the invention is not limited in this regard, as it operates in another radio system. This is because the above-described technique for implementing a transmission path in a certain wireless system using a device designed for the above can be used in any suitable wireless system.

Further, in the above example, the GSM device is described as using a 13 MHz master clock to clock the interface 407, and the PHS system is described as having a symbol rate of 192,000 symbols / second. . However, the present invention is not limited to using a 13 MHz master clock to clock the interface, where the data transmitted over the interface has a symbol rate of 192,000 symbols / second. In fact, any suitable master clock frequency and symbol rate can be used, and the invention is not limited in this respect.
Another obstacle that may be encountered when a device designed to operate in a first wireless system is used in a second wireless system is that the wireless device operates in a second wireless system. There is a possibility that hardware which is not designed in the above will be included in the receiving path.

For example, as shown in FIG. 8, the reception path of the GSM device includes an analog / digital converter 800 that converts a received analog signal into an input digital form, and a frequency component of the received signal that is not in the frequency band of the wireless system. A channel selection filter 802 that filters out the received signal, a decimator 804 that reduces the number of samples of the received signal for subsequent processing, and a digital baseband processor 806 that demodulates and detects the received signal.
As mentioned above, in the GSM system, the symbol rate is 270.83 kHz. The ADC 800 is clocked at a GSM master clock frequency of 13 MHz. As a result, the ADC 800 samples the input signal at a rate of 13 MHz (ie, 13,000,000 samples / second). As shown in Table 8, when a GSM signal with a symbol rate of 270.83 kHz is sampled at a rate of 13 MHz, 48 samples are generated per GSM symbol.

チャネル選択フィルタ８０２は、無線システムで用いられる周波数バンドにない受信信号の周波数成分をフィルタリングして取り除き、信号をデシメータ８０４に送信する。１つの態様において、チャネル選択フィルタは、ＧＳＭ無線標準で規定されたチャネル選択の仕様に合うように、設計することができる。デシメータ８０４は、受信信号のサンプリング周波数を４８の係数で２７０，８３３サンプル／秒に減少させることにより、ＡＤＣ８００により信号に付加されたオーバーサンプリングデータを取り除く（すなわち１サンプル／シンボル）。デジタルベースバンドプロセッサは次に、ＧＳＭのシンボルレート、すなわち１サンプル／シンボルでサンプリングされたデータを処理することができる。

The channel selection filter 802 filters out the frequency component of the received signal that is not in the frequency band used in the wireless system, and transmits the signal to the decimator 804. In one aspect, the channel selection filter can be designed to meet the channel selection specifications specified in the GSM radio standard. Decimator 804 removes the oversampling data added to the signal by ADC 800 by reducing the sampling frequency of the received signal by a factor of 48 to 270,833 samples / second (ie, 1 sample / symbol). The digital baseband processor can then process the data sampled at the GSM symbol rate, ie 1 sample / symbol.

  However, using a GSM receiver path in a PHS radio system can result in some performance degradation because the demodulation and detection algorithms used in the PHS radio system have a minimum sampling of 1.5 samples / symbol. This is because the rate is set. As mentioned above, the symbol rate used in the PHS radio system is 192 kHz. The PHS signal can be received by ADC 800 and converted to digital form. Similarly, as mentioned above, the ADC 800 samples the PHS signal at a rate of 13 MHz. This results in 67.7083 samples / PHS symbols, as shown in Table 9.

オーバーサンプリングされた信号がチャネル選択フィルタ８０２によりフィルタリングされた後、デシメータ８０４は、信号内のサンプル数を、４８の係数で１．４１０５サンプル／ＰＨＳシンボルにまで減少させる。１つの態様において、要素８００、８０２および８０４はハードウェア要素である。さらに、アナログベースバンドプロセッサをデジタルベースバンドプロセッサ８０６に結合するインターフェイス８０５は、リンク８０５を介して送信される最大ＰＨＳサンプリングレートが１．４１０５サンプル／ＰＨＳシンボルとなるようなレートで、クロックされ得る。上で示したように、このサンプル／シンボル率は、ＰＨＳ無線標準により定められている１．５サンプル／シンボルの基準を満たさない。しかし、回路がＧＳＭ無線システムで動作するように設計されているため、リンク８０５は、必要な最小ＰＨＳサンプリングレートをサポートしない可能性がある。この不十分なサンプリングレートは、続く処理において信号におけるエイリアシングおよびシンボル間干渉をもたらす可能性がある。

After the oversampled signal is filtered by the channel selection filter 802, the decimator 804 reduces the number of samples in the signal by a factor of 48 to 1.4105 samples / PHS symbols. In one aspect, elements 800, 802 and 804 are hardware elements. Further, the interface 805 that couples the analog baseband processor to the digital baseband processor 806 may be clocked at a rate such that the maximum PHS sampling rate transmitted over the link 805 is 1.4105 samples / PHS symbols. As indicated above, this sample / symbol rate does not meet the 1.5 sample / symbol criteria defined by the PHS radio standard. However, link 805 may not support the required minimum PHS sampling rate because the circuit is designed to operate in a GSM radio system. This insufficient sampling rate can lead to aliasing and intersymbol interference in the signal in subsequent processing.

  As further noted above, the channel selection filter 802 can be designed to meet the GSM channel selection specification and not the PHS channel selection specification. For example, the PHS radio standard defines that the channel selection filter must be a matched filter. That is, in addition to filtering out frequency components outside the PHS frequency band, the filter also weights signal frequency components based on power, thereby increasing the signal-to-noise ratio. In this way, the matched filter weights the contribution from each filter band in proportion to the signal power, thereby matching the filter frequency response to the frequency spectrum of the signal.

  However, since channel selection filter 802 is designed to operate in a GSM system, channel selection filter 802 may be a mismatched filter with respect to a PHS system. Instead of using a matched filter to filter the PHS signal, using a mismatched filter results in a low signal-to-noise ratio and can cause performance degradation when the device is operated in a PHS system. As mentioned above, the digital baseband processor can demodulate and detect the received signal. Demodulation is the process of removing the carrier signal and obtaining the original signal waveform. Detection is the process of extracting symbols from the baseband waveform.

  Detection can be performed coherently or non-coherently. In coherent detection, channel phase and attenuation estimates, and carrier frequency error and timing estimates are obtained. This information is used to recondition the received signal, which can then be demodulated to obtain a PHS symbol. On the other hand, non-coherent detection does not require channel phase and attenuation estimates and is therefore simpler than coherent detection. Non-coherent detection is simple and consumes less processing resources to perform, but may reduce the accuracy of detection of the original transmitted symbols.

  The PHS radio standard defines the use of non-coherent detection of PHS radio signals. However, if the digital baseband processor 806 performs coherent detection instead of performing non-coherent detection, performance degradation due to using the mismatch filter 802 and insufficient sampling rate at the interface 805 may be compensated. In one aspect, this can result in a net performance gain of about 2 dB at the signal to noise ratio.

  As mentioned above, channel phase and attenuation, carrier frequency error and timing error can be estimated when performing coherent detection. This estimation may be performed using a higher sampling rate. For example, as shown in FIG. 9, the digital baseband processor 901 receives data at a rate of 270.83K samples / second or 1.4105 samples / PHS symbol. However, it is possible to obtain channel estimates and carrier frequency and timing error estimates using a data rate of 7 samples / PHS symbols. Thus, the incoming signal can be interpolated by a factor of 5 by an interpolator 903, and then decimated by a fractional factor of 0.992492 by a fractional decimator 905, resulting in an output data rate of 7 samples / PHS symbols.

  As noted above, an ideal PHS matched filter may not be available because it uses a chip designed to operate in a GSM system. However, the filters inside the digital baseband processor can be designed so that the overall filter, including the analog baseband processor filter, approximates the ideal PHS matched filter. That is, the filter in the digital baseband processor predistorts the signal so that the signal after passing through one or more downstream filters approximates the output of an ideal PHS filter. To be able to. For example, this predistortion technique may be used in the RRC filters 505a and 505b shown in FIG. This predistortion technique may also be used in the interpolation filter 903 of FIG. The technique for predistortion is described in more detail in a provisional application entitled “Filters For Communication Systems”, filed at the same date with the agent docket number A0312.70551US00.

  In one aspect of the invention, the digital baseband processor 806 may be software programmed to perform coherent detection for non-coherent detection. However, the present invention is not limited in this respect because the digital baseband process can perform coherent detection in any suitable manner. For example, the digital baseband processor may be incorporated in hardware to perform coherent detection.

  The various aspects of the invention can be used alone, in combination, or in various arrangements not specifically mentioned in the foregoing embodiments, and thus, in that application, the elements described above or shown in the drawings. The details and arrangement are not limited. The invention is capable of other embodiments and of being practiced or carried out in various ways. In particular, the various aspects of the invention can be practiced with numerous types, arrangements, configurations and performance processing devices. Device implementation is not limited.

Further, the various aspects of the invention described in one embodiment can be used in combination with other embodiments and are not limited to the arrangements and functional combinations specifically described herein. Various modifications, changes and improvements will be readily apparent to those skilled in the art. Such modifications, changes and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the above description and drawings are for illustrative purposes only.
The use of terms indicating the order for modifying claim elements in a claim, such as “first”, “second”, “third”, etc., per se is any priority, advantage or It does not imply an order, or a temporal order in which actions are performed in the methods herein, but one claim element of a name from another element of the same name (except for the use of ordering terms). It is used only as a label for identification to identify a claim element.

Also, the expressions and terminology used herein are for descriptive purposes only and should not be considered limiting. As used herein, “including”, “comprising”, or “having”, “containing”, “involving” and variations thereof are listed below. Are included and their equivalents, as well as additional items.
Various modifications and improvements will be readily apparent to those skilled in the art since several aspects of the invention have been described in detail. Such modifications and improvements are intended to be included within the spirit and scope of the invention. Accordingly, the above description is for illustrative purposes only and is not intended to be limiting. The present invention is limited only by the following claims and their equivalents.

FIG. 4 is a timing diagram illustrating examples of symbol values of a signal according to two different symbol rates according to one aspect of the present invention. It is a figure which shows the example of the radio | wireless communication frame suitable for using in the aspect of this invention. FIG. 6 illustrates symbol boundary selection between two PHS symbols according to one aspect of the present invention. FIG. 6 is a block diagram of an example wireless device suitable for use in aspects of the present invention. FIG. 4 is a block diagram of functional units in the transmission path of a digital baseband processor according to one aspect of the present invention. FIG. 6 is a timing diagram of an example PHS symbol, according to one aspect of the invention. It is a block diagram of an example of the transmission path of the radio | wireless device suitable for using in the aspect of this invention. It is a block diagram of an example of the receiving path of the radio | wireless device suitable for using in the aspect of this invention. FIG. 3 is a block diagram of functional units in the receiving path of a digital baseband processor according to one aspect of the present invention.

Claims (9)

A method for receiving a wireless signal of a simple mobile phone system (PHS), comprising:
Demodulating the received signal to generate a baseband waveform;
Filtering the baseband waveform using a mismatched channel selection filter; and extracting at least one PHS symbol from the baseband waveform by performing coherent detection of the baseband waveform;
Said method.   The method of claim 1, wherein received signal filtering, received signal demodulation, and at least one PHS symbol extraction are performed in a second radio system different from the PHS radio system.   The method of claim 2, wherein the second wireless system operates in accordance with an international standard for mobile communications (GSM) wireless standards. The method of claim 1, further comprising sampling the baseband waveform at a sampling rate that is lower than a theoretical minimum rate of the PHS wireless system.   The method of claim 4, wherein the theoretical minimum sampling rate is a Nyquist sampling rate. The method of claim 4, further comprising transmitting the sampled baseband waveform over the interface. The method of claim 4, further comprising oversampling the sampled baseband waveform. Oversampling the sampled baseband waveform
5. The method of claim 4, comprising oversampling the baseband waveform using at least one of an integer interpolation filter, a fractional interpolation filter, or a fractional decimation filter.   Oversampling the sampled baseband waveform includes oversampling the baseband waveform using at least an integer interpolation filter, wherein the integer interpolation filter compensates for at least one hardware downstream filter. 5. The method of claim 4, wherein the method is predistorted.

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