JP2008511283A - Method and apparatus for customizing a power supply based on load characteristic data - Google Patents

Abstract

A method for responding to load characteristic data, such as VID codes of multiple processor types, and providing a required voltage or other condition, eg, an overvoltage protection limit value, according to the load characteristic data.
A power supply for powering an electrical load that generates load characteristic data that determines power supply characteristics to be provided from the power supply to the electrical load, responsive to a reference signal to set the power supply characteristics A voltage regulator for generating an output voltage to be provided as an input voltage for powering the electrical load, and a control circuit for generating the reference signal for the regulator, the control circuit comprising: Responsive to a selection input for selecting a type of electrical load from load characteristic data from the electrical load and a plurality of types of electrical load, the selection input determining the type of electrical load, and the control circuit A power supply adapted to evaluate the load characteristic data and to generate a reference signal for the regulator.
[Selection] Figure 5a

Description

  The present invention relates to power supplies, and more particularly to power supplies for supplying low voltage, high current power to devices such as portable computers, such as notebook computers and laptop computers.

  In order to provide low voltage, high current, high efficiency power supplies for applications such as portable computers such as laptop computers and notebook computers, multiphase buck converter switching power supplies are currently used.

  The present invention provides output voltage or other power supply characteristics, such as, for example, output voltage or other power supply characteristics, depending on load characteristic data such as a digital voltage data code known as a VID code received from a microprocessor that is powered by a power source. The present invention relates to a power supply capable of setting an overvoltage protection limit value.

  Various microprocessor manufacturers, such as Intel, AMD, etc., provide a table of power supply inputs for the microprocessor, depending on operating conditions. The microprocessor generates a voltage identification (VID) code that includes digital bits that specify the input voltage required at a particular moment in response to processor activity.

  This allows the processor to store energy when the load condition is low, and to receive more power when the load condition is high. Each manufacturer uses a different VID code, and this VID code may be different if the processor chip is different, even if the same manufacturer makes it.

  In the past, power supplies for computer systems required a dedicated power supply that could decode the VID code for a particular processor. However, these power supplies cannot decode VID codes for processors other than the processor for which the power supply is designed.

  It is an object of the present invention to provide a power supply that can respond to load characteristic data, such as multiple processor type VID codes, and provide the required voltage or other conditions, such as overvoltage protection limits, according to the load characteristic data. It is to provide.

  The above and other objects of the present invention are a power supply for supplying power to an electrical load that generates load characteristic data that determines the power supply characteristics to be provided from the power supply to the electrical load, and sets the power supply characteristics A voltage regulator for generating an output voltage that is responsive to a reference signal and to be provided as an input voltage for powering the electrical load, and a control circuit for generating the reference signal for the regulator The control circuit is responsive to load characteristic data from the electrical load and a selection input for selecting an electrical load type from a plurality of electrical load types, so that the selection input is Determine the type of electrical load and allow the control circuit to evaluate the load characteristic data and generate a reference signal for the regulator Is accomplished by a power source is turned so that.

  The above and other objects of the present invention are a power supply for powering a microprocessor load that generates a digital voltage identification (VID) code that determines the power supply characteristics to be provided from the power supply to the microprocessor load. A voltage regulator that is responsive to a reference voltage for setting an output voltage and that provides an output voltage to be provided as an input voltage for powering the microprocessor load; and the reference signal for the regulator A control circuit for generating, wherein the control circuit is responsive to a digital VID code from the microprocessor load and a selection input for selecting a microprocessor type from a plurality of microprocessor load types Therefore, the selection input is a negative value of the microprocessor. Determining the type, by the VID code, said to be able to evaluate the VID code is accomplished by a power source adapted to generate a reference signal for the regulator.

The above and other objects of the present invention are a method for powering an electrical load from a power source that generates load characteristic data that determines power supply characteristics to be provided to the electrical load,
Responsive to a reference signal for setting the power supply characteristic, generating an output voltage to be provided as an input voltage for powering the electrical load;
Responsive to a load input from the electrical load and a selection input for selecting an electrical load type from a plurality of electrical load types, generating the reference signal for the regulator, and thus the selection Also achieved by a method for powering an electrical load, further comprising the step of allowing the input to determine the type of electrical load and to evaluate the load characteristic data to generate a reference signal for the regulator. The

  Further and other objects of the present invention are a method for powering a microprocessor load that generates a digital voltage identification (VID) code that determines the input voltage to be provided from the power source to the microprocessor load. Responsive to a reference voltage to set an output voltage, generating an output voltage to be provided as an input voltage for powering the microprocessor load, a digital VID code from the microprocessor load, and a plurality of In response to a selection input for selecting a microprocessor load type from a microprocessor load type, and generating the reference signal for the regulator, so that the selection input determines the microprocessor load type. Determine and generate the reference signal for the regulator The said further comprising the step of allowing evaluation of digital VID codes also achieved by a method for powering a microprocessor load.

Other features and advantages of the present invention will become apparent from the following detailed description of the invention when read with reference to the accompanying drawings.
The present invention will now be described in more detail with reference to the accompanying drawings.

  FIG. 1 shows a switching regulator power supply for a two-phase buck converter. The control chip 10 shown in the block diagram of FIG. 2 receives a number of digital inputs VID0 to VID5 labeled 12 in FIG.

  This VID input is received from a powering microprocessor and is a digital bit that sets the voltage output of the buck converter under various conditions. For example, in an Intel VR-10 chip, the output voltage varies between 0.8375V and 1.6000V based on the digital bit settings on VID0 to VID5 determined by the chip manufacturer.

  Pin VID_SEL (13) is used to indicate which processor chip is being powered, which allows control chip 10 to identify the VID code. For example, if VID_SEL is grounded, the processor chip is an Intel VR-10 and the VID code is decoded to provide the correct voltage for this chip.

  If VID_SEL is at VCC, the processor is an AMD ATHLON. If VID_SEL remains open, the processor is AMD's HAMMER. In the ATHLON chip, the range of Vout is 1.100 to 1.550V.

  For all three processors, if all VID bits are 1, Vout is disabled. That is, it becomes OFF. In FIG. 1, VID_SEL is shown as being connected to ground, so the control chip 10 decodes the VID code as an Intel VR_10 chip.

  Please refer to FIG. Power from a suitable power source, typically a battery, or an AC-DC transformer / rectifier is supplied at VIN. The control chip 10 has an output GATE H1 and GATE L1 for driving the high voltage side transistor of the first phase 14 and the low voltage side transistor of the multiphase converter. The transistor H1 is a high voltage side transistor, and the transistor L1 is a low voltage side transistor.

  Outputs GATE H2 and GATE L2 drive a second phase 16 that includes a high side transistor H2 and a low side transistor L2. Each set of transistors is arranged in a half-bridge structure, and a common connection is provided for each output inductor L10 and L20. The other ends of the inductors L10 and L20 are coupled to a common output node VOUT +, and an output is taken across the output capacitor COUT coupled between VOUT + and ground (VOUT−).

  The output voltage is detected between VOUTSNS + and VOUTSNS−, and these VOUTSNS + and VOUTSNS− are applied to the feedback FB input and VOSNS− input of the control chip 10, respectively.

  Current detection for each phase is performed at inputs CSINP1 and CSINP2, respectively, and current is detected by lossless average inductor current detection. A series resistor RCS1 and a capacitor CCS1 for phase 1 are provided at both ends of the inductor L10. Connected in series, the voltage across the capacitor is detected.

  Resistor RCS1 and capacitor CCS1 are selected such that the time constants of RCS1 and CCS1 are equal to the inductor time constant obtained by dividing the inductance of L10 by the resistance value of inductor DC. If these two time constants match, the voltage across CCS1 is proportional to the current in L10, and the detection circuit is as if only a detection resistor having a value of RL (L10 DC resistance) is used. Thus, the detection circuit can be handled. Even if these time constants do not match, the measured value of the inductor DC current is not affected, but the AC component of the inductor current is affected.

  The advantage of detecting inductor current over high side detection or low side detection is that it detects the actual output current being sent to the load, not the peak information or sample information about the switch current. is there. Based on the real-time information, the output voltage can be determined to fill the load line.

  Except for the sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. There is no other way to provide information either during load increase (low voltage side detection) or load decrease (high voltage side detection). Another phase 2 has a sense resistor RCS2 and a capacitor CCS2 and functions similarly.

  FIG. 2 shows a block diagram of the control chip 10 in more detail. Here, voltage mode control for performing trailing edge (rear edge) modulation is performed. Within the voltage control loop, a high gain, wide bandwidth voltage type error amplifier is used. At the input FB, output voltage detection is performed and this voltage is provided to the inverting input of the error amplifier.

  The other non-inverting input is coupled to a reference voltage VDAC, which is set by the VID and VID_SEL pins as described with reference to FIG. 1 above. The VID_SEL pin in FIG. 1 is shown to be grounded to the Intel VR10 chip.

  In other processors, such as AMD HAMMER or ATHLON processors, the VID_SEL pin is connected to a different voltage or remains open. In an AMD HAMMER processor, VID_SEL is open, and in an AMD ATHLON chip, VID_SEL is connected to VCC. The VDAC setting determines the reference voltage VDAC for the error amplifier 50, so its output voltage is set.

  The control chip 10 has an oscillator 60 that can be programmed using an external resistor ROSC. This oscillator generates a 50% duty cycle internal sawtooth signal as shown in FIG. 3A. The 50% duty cycle sawtooth signal of FIG. 3A is used to generate two 180 ° out-of-phase timing pulse signals that set phase 1 and phase 2 RS flip-flops 70 and 80.

  3B and 3C show timing pulses, which are shown as CLK1 and CLK2 in FIG.

  Referring to FIGS. 2 and 3, each flip-flop 70 and 80 is set upon receipt of a clock pulse. Further, the respective ramp voltages are provided at the non-inverting inputs of the respective PWM comparators 90 and 100. The output of the error amplifier 50 is supplied to each inverting input of the PWM comparator. The PWM comparator 90 is provided with a fixed slope ramp voltage, which is generated by charging the current through the capacitor 110 from the current source IROSC / 2. When the flip-flop 70 is set, the low voltage side switch L1 is turned off and the high voltage side switch H1 is turned on. See also FIGS. 4A, 4C, and 4D.

  Switch SW1 across capacitor 110 is opened by the QB output of flip-flop 70, allowing capacitor 110 to begin charging to provide a ramp voltage to PWM comparator 90. Similarly, under the control of the flip-flop 80, in another phase, the low-voltage side driver is turned off and the high-voltage side driver is turned on when the clock pulse is received, and the switch SW2 is opened by the QB output of the flip-flop 80. Then, the capacitor 120 starts charging.

  In phase 1, capacitor 110 is charged by a current source proportional to the switching frequency that produces a fixed slope ramp rate of about 57 millivolts per percent duty cycle. For example, the duty cycle of the steady state operating switch mode is 10% and the internal lamp amplitude is approximately 570 mV from the start point to the time when the lamp crosses the output voltage of the error amplifier EAOUT, as shown in FIG. 3D. It becomes. In FIG. 3D, the fixed slope ramp signal provided to the non-inverting input of the PWM comparator 90 is shown in the first and third quadrants of the graph.

  In contrast, the PWM comparator 100 for the second phase is supplied with a variable slope ramp voltage, which is shown in the second and fourth quadrants of FIG. 3D. This will be described in detail later.

  In phase 1, flip-flop 70 is reset when the PWM ramp voltage exceeds the output voltage of the error amplifier. As a result, the high-voltage side switch H1 is turned off and the low-voltage side switch L1 is turned on, and the PWM lamp is discharged to 0.7 V until the next clock pulse. Phase 2 flip-flop 80 and comparator 100 operate in the same manner, but the slope of the ramp signal provided to the non-inverting input of comparator 100 is variable, as described below.

  Since each flip-flop 70, 80 is reset to dominant, both phases can be zero duty cycle within tens of nanoseconds in response to a stepped decrease in load. The phase is responsive to a stepped increase in load that is gated on by the clock voltage, and the phases overlap and can be 100% duty cycle.

  As a result of the output voltage of the error amplifier that is larger than the input range of the common mode of the PWM comparator, the duty cycle is 100% regardless of the voltage of the PWM lamp. Such a structure ensures that the error amplifier 50 is always in control and can require a 0-100% duty cycle if necessary.

  Given the low output-to-input voltage ratio of most systems, it is advantageous to respond to a suitable load step reduction. Inductor current will increase more rapidly in response to a load transient decrease rather than decrease.

  This control method is such that, within a single switching cycle, the inductor current changes in response to load transients, maximizing power supply effectiveness and minimizing output capacitor requirements.

  As described above, the ramp signal to the comparator 90 and the ramp signal to the comparator 100 are different. The PWM comparator 90 receives a fixed slope ramp voltage as shown in quadrants I and III of FIG. 3D.

  In contrast, PWM comparator 100 receives, at its non-inverting input, a variable slope ramp voltage as shown in quadrants II and IV of FIG. 3D. This variable slope ramp voltage is adjusted by distribution adjustment error amplifier 130 in response to inputs CSINP1 and CSINP2.

  The distribution of current between the two phases is achieved by a master-slave current distribution loop topology. The output of the phase 1 current sense amplifier 140 sets a variable reference for the distribution adjustment error amplifier 130.

  Next, the distribution adjustment error amplifier adjusts the duty cycle of the PWM ramp 2 by adjusting the slope, as shown by the dotted line in FIG. 3D, so that the input error of the distribution adjustment amplifier becomes zero. The current distribution between the two phases can be precise.

  The maximum and minimum duty cycle adjustment ranges of lamp 2 relative to lamp 1 in the preferred embodiment are limited to 0.5X and 2.0X of the master, ie fixed slope (phase 1) ramp signal. This is illustrated by the slope of the ramp voltage provided to the phase 2 PWM comparator 100 in FIG. 3D.

  The minimum duty cycle is indicated by the ramp with the maximum slope in FIG. 3D, and the maximum duty cycle is indicated by the ramp with the minimum slope in FIG. 3D.

  The crossover frequency of the current distribution loop can be programmed by a capacitor at the SCOMP input terminal so that the distribution loop does not interfere with the output voltage loop. This SCOMP capacitor is driven by a transconductance stage that can source and sink 25 microamps. The duty cycle of lamp 2 is designed to track the voltage on the SCOMP pin in reverse.

  When the voltage SCOMP increases, the slope of the ramp provided to the PWM comparator 100, ie the phase 2 comparator, increases and the respective duty cycle decreases. As a result, the ramp signal provided to the PWM comparator 100 before the gate pulse is provided to the high voltage side transistor due to the source current that reduces the phase 2 output current being limited to 25 microamps. The SCOMP precharge circuit is included in the precondition V (SCOMP) so that the duty cycle is equal to the duty cycle of the lamp 1.

  As shown in FIGS. 2 and 3, the fixed slope ramp is charged from a current source IROSC / 2 and the variable slope ramp is charged at IROSC, but this ramp is shunted by a variable current sink 190. This sink sinks current within the range of 0 to IROSC × 3/4. Therefore, the range of the current charging capacitor 120 is a range from 0 to IROSC / 4. That is, the range is from 2X to 1/2 of the charging rate of the capacitor 110 in the fixed slope ramp generation circuit.

  FIG. 4 shows PWM operating waveforms under various conditions for the first phase. The same applies to the second phase, but unlike the PWM lamp 1, the PWM lamp 2 is different in that the slope is variable. The CLK1 pulse is provided to the flip-flop 70.

  FIG. 4B shows the output voltage EAOUT of the error amplifier 50 under various load conditions. As shown in the left part of FIG. 4B, when the ramp voltage for the PWM comparator 90 indicated as PWM lamp 1 becomes equal to the output voltage of the error amplifier 50, as shown in FIGS. Is turned off and the low voltage side transistor is turned on.

  At the next clock pulse (CLK1), the output of the error amplifier increases. This indicates that the output voltage has decreased because a larger current is required. Thus, only after the ramp voltage has increased to a higher voltage level, the ramp voltage is equal to the error amplifier voltage. Therefore, it is ensured that the duty cycle of the high voltage side transistor is increased, that is, the pulse width is widened as shown in FIG. 4C, and therefore the output current supplied to the phase 1 inductor is increased. Therefore, as shown in FIG. 4D, the low voltage side transistor is turned off for a longer time.

  Due to the third clock pulse, the input signal of the error amplifier becomes almost zero as shown in FIG. 4, so that it can be seen that the current requirement is reduced or there is a failure.

  If the error amplifier output voltage drops below 0.55 volts, the 0% duty cycle comparator 160 (FIG. 2) also turns off the low side transistor. As shown, the high side transistor is also turned off during this period.

  With the fourth clock pulse of FIG. 4, the error amplifier output voltage increases again, the ramp is as shown in FIG. 4B, and the gate drive is as shown in FIGS. 4C and 4D. .

  As shown in FIG. 3C, the circuit of the present invention allows current distribution by adjusting the slope of the ramp voltage relative to at least one but not all of the PWM comparators.

  A two-phase converter only adjusts the slope of the lamp with respect to one phase. In the three-phase converter, the inclination of the two lamps is adjusted. The slope of the ramp provided to the non-inverting input of the first comparator 90 is always constant as shown by the fixed ramp 1 in FIG. 3D. For example, if the current required in phase 1 increases, this current is detected at the nodes of resistors RCS1 and CCS1.

  The increased current appears at the non-inverting input of amplifier 140, and this current is added to voltage VDAC by summing stage 170. The increased output signal of the summing stage 170 is provided to the non-inverting input of the distribution adjustment error amplifier 130 to increase the output signal of the distribution adjustment error amplifier. As a result, the current passing through the current source 190 increases and the current is shunted from the capacitor 120, so that the time taken to charge the capacitor 120 becomes longer.

  The slope is flat as shown in FIG. 3D due to the waveform of lamp 2 with a longer duty cycle. As a result, the output of the PWM comparator 100 remains low for a longer time, so that the flip-flop 80 remains set, and the high-voltage side transistor H2 is kept on for a longer time and is obtained from the second phase. It can be guaranteed to increase the current being generated.

  Thus, the second phase matches the increased current required by the first phase. As the second phase current increases, the first phase decreases to compensate for both phase currents being equal. This occurs because the error amplifier output decreases as the current supplied by the second phase increases.

  Similarly, if the current in the second phase increases as detected by detection voltage CSINP2, the output of amplifier 150 increases, so the inverting input to distribution adjustment error amplifier 130 also increases, and the distribution adjustment error amplifier's output increases. The output decreases. This reduces the current shunted by the current source 190 and charges the capacitor 120 more rapidly, thus increasing the ramp 2 voltage slope, as shown in FIG. 3D. Therefore, the output of the PWM comparator goes to high level more quickly, resetting the flip-flop 80, turning off the high voltage side transistor H2, and reducing the current supplied by the second phase.

  At the same time, since the output of the error amplifier 50 increases, the on-time of the high-voltage side transistors in both phases becomes longer. In order to compensate for the decrease in current caused by the reduced slope of the ramp 2, the first phase supplies current so that it matches the reduced current provided by the second phase. The current supplied by these two phases is driven so that the error across the input of the distributed adjustment error amplifier is zero.

  Conversely, if the current in phase 1 decreases, the non-inverting input of amplifier 130 decreases, reducing the output of amplifier 130, resulting in capacitor 120 being charged in a shorter time, The phase 2 high voltage side transistor is turned off in a shorter time and the phase 2 current is reduced to match the phase 1 current.

  If the current in phase 2 decreases, the voltage at the inverting input of amplifier 130 decreases, charging capacitor 120 for a longer time and increasing the current supplied by the phase 2 transistor. Phase 1 transistors compensate for these currents to decrease and match with phase 2 transistors. Once the amplifier 130 inputs are equal, the output phase currents are also equal.

  In either case, the output of the error amplifier 50 tracks the output current requirement (this output increases when the output current requirement increases and decreases when the output current requirement decreases). The distributed conditioning amplifier 130 operates to equalize the current in multiple phases.

  Thus, the error amplifier 50 operates to increase or decrease the current in all phases as required by the load, while the distributed adjustment amplifier is fed by all phases with a PWM comparator driven by a variable slope ramp signal. It operates to increase or decrease the current being applied to equalize the load current.

  FIG. 5 shows details of the VID control circuit for setting the output voltage of the converter.

  The VID code is received from the microprocessor at the VID input 12. In these VIDs, each input 12 is pulled up by an 18 μA current source that pulls up the input signal to 4.9 V, as indicated by a respective voltage source 300, eg, voltage source 301. Block 310 includes a plurality of VID input comparators 310A-310F having a threshold voltage 312 (one comparator for each VID input). Only one of these comparators 310A is shown.

  The threshold voltage 312 is determined by the input on VID_SEL. For an Intel VR-10 processor (HAMMER or ATHLON), the threshold is 0.6V, and for an AMD processor, the threshold is 1.5V for the AMD chip. When VID_SEL is open or at VCC, the threshold will be 1.5V. When VID_SEL is grounded, the threshold is set to 0.6V for the Intel VR-10 chip.

  When VID_SEL is at ground potential, the outputs of both comparators 320 and 330 are low. This tells the digital-to-analog converter (DAC) 340 that the VID code should be decoded for the Intel VR-10 chip. If both inputs 350 and 360 are low, DAC 340 defaults to the Intel VR-10 chip VID code. The low output of comparator 330 also selects the 0.6V threshold via switch 311.

  When VID_SEL is open, the output of the comparator 320 is low. When VID-SEL is open, current source 321 pulls VID-SEL down to a voltage lower than the 3.3V reference for comparator 320, so its output is low.

  However, since the output of the comparator 330 having a 1.2V reference is high, the input 360 is high and commands the DAC 340 to decode the VID code for the AMD HAMMER chip. At the same time, the high output of comparator 330 selects the 1.5 V threshold for VID input comparator 310 via switch 311.

  When VID_SEL is VCC, the outputs of the comparators 320 and 330 are both high, so the DAC 340 is notified that the VID code for the AMD ATHLON processor chip should be decoded. The high output of comparator 330 also selects the 1.5V threshold for VID input comparator 310.

  In response to the input VID bit as decoded by the comparator 310, the DAC 340 provides the reference voltage VDAC 380 via the transconductance DAC buffer 360 to the error amplifier 50 described with reference to FIGS. Set the voltage.

  The voltage on VDAC is trimmed to the output voltage of the error amplifier by EAOUT tied to FB through a precise resistor. This compensates for errors in the generation of FB bias current based on DAC buffer input offset, error amplifier input offset, and RROSC. This trimming method provides a system accuracy of 0.5%.

  The VID control circuit of FIG. 5 can accept changes in the VID code during operation and thus change the VDAC voltage. This circuit can detect VID changes and blank the output response of DAC 340 to 400 ns via blanking circuit 370 to prove that the new code is valid and not due to skew or noise.

  The sink / source capability of the VDAC buffer amplifier 362 is programmed by the same external resistor that sets the oscillation frequency RROSC. The slew rate of the voltage at the VDAC pin 380 can be adjusted by an external capacitor CDAC between the VDAC pin and the VOSNS pin. An RDAC resistor connected in series with this capacitor is used to compensate the VDAC buffer amplifier (see FIG. 1).

  As a result of the digital VID transient, the analog transient of the VDAC voltage and converter output voltage is smooth, and the inrush current and output voltage overshoot at the input and output capacitors are minimized.

  Adaptive voltage positioning is used to reduce the output voltage deviation during transients and the power dissipation of the load absorbing the maximum current. FIG. 2 shows this circuit in relation to voltage positioning. A resistor RFB is connected between the inverting input (pin FB) of the error amplifier 50 and the output voltage of the converter. An internal current source 200 whose value is programmed by the same external resistor that programs the oscillation frequency RROSC, pumps current from the FB pin.

  The FB bias current causes a pumping voltage drop across RFB, which reduces the converter output voltage to V (VDAC) -I (FB) × RFB and maintains balance at the input of error amplifier 50. The RFB is selected to program the desired value of the offset fixed voltage below the DAC voltage.

  The voltage at the VDR pin is the average value of both phase current sense amplifiers 140 and 150, which represents the sum of the VDR voltage and the average inductor current of all phases. The VDR pin is connected to the FB pin via a resistor RDRP. Error amplifier 50 equalizes the voltage on the FB pin to VDAC through the power loop. Thus, the current through RDRP is equal to (VDRP-VDAC) / RDRP.

  Thus, as the load current increases, the VDRP voltage also increases, resulting in an increase in RFB current and lower regulated output voltage, thus reducing the output voltage proportional to the increase in load current. Is done. Thus, the resistor RDRP can program the droop impedance or output impedance of the converter. The offset and slope of the converter output impedance are independent of the VDAC voltage.

  AMD specifies an acceptable power supply regulation window of ± 50 mV centered on the VID table voltage specified by AMD. This VID table voltage can be known from the specifications issued by the chip manufacturer.

  Intel specifies the VID table voltage as the absolute maximum power supply voltage for VR-10.0. In order to provide all three DAC options, the HAMMER and ATHLON DAC output voltages are pre-positioned 50 mV higher than the value that would be of interest in AMD's use document.

  During the test, a series resistor is inserted between EAOUT and FB to cancel an additional 50 mV from the digital to analog converter. An FB bias current equal to IROSC generates a 50 mV cancellation voltage.

  Trimming the VDAC voltage by monitoring V (EAOUT) with this 50 mV cancellation resistor in the circuit also trims errors in the FB bias current.

  The VDRP pin voltage represents a value obtained by adding the DAC voltage to the average current of the converter. The load current can be known by subtracting the VDAC voltage from the VDRP voltage.

  FIG. 5 illustrates that the present invention can determine or set other characteristics of the power supply besides the power supply output voltage. For example, according to the present invention, an OVP (overvoltage protection) limit value can be determined.

  As shown in FIG. 1, the control chip 10 has an OVP input 8. This OVP input 8 sets an overvoltage protection limit value for the power supply. For Intel chips, the OVP limit is 150 mV higher than VDAC, and for AMD, this value is 450 mV higher than VDAC.

  In order to do this, an OVP comparator 390 is provided that responds to the voltage FB (output voltage of the power supply) and a predetermined voltage VDAC + 150 mV or VDAC + 450 mV. If VID_SEL is VCC or is floating, line 360 is at a high level. Since this means that the load is an AMD chip, the switch 400 selects the reference voltage 410 (450 mV).

  If line 360 is low, the load is an Intel VR-10.0 chip and the reference voltage 420 (150 mV) is selected.

  The present invention has been described above by taking the example of controlling the output voltage and the OVP limit value, but according to the present invention, other outputs or characteristics of the power supply are similarly customized to the load. be able to.

  The present invention has been described above with reference to a two-phase converter. However, the present invention can also be used for any type of power source, for example, a single-phase converter, a converter having three or more phases, or a non-converter power source.

  Although the present invention has been described as selecting one of three load types (Intel VR-10.0, AMD ATHLON, and AMD HAMMER), those skilled in the art will be able to: It will be appreciated that the present invention can be extended to more than four types of loads, eg, more than four different microprocessor types. This can be accomplished by appropriately designing a selection circuit that is responsive to the VID_SEL pin so that the selection circuit can distinguish between four or more processor types.

For example, as shown in FIG. 5, the VID_SEL pin provides three levels for the select circuit: a ground level, a VCC level, and a floating level. To extend this circuit to accommodate four load types, VID_SEL is provided with a fourth level (eg, voltage level V _BIAS between ground level and VCC level), for example adding another comparator By doing so, the additional circuit can be appropriately redesigned.

  Although the invention has been described with reference to specific embodiments of the invention, many other variations and modifications and other uses will become apparent to those skilled in the art. Accordingly, the invention is not to be limited by the specific disclosure herein, but only by the claims.

1 is an overall schematic diagram of a switching regulator power supply for a two-phase converter for powering a portable computer such as a laptop. 1 is an overall schematic diagram of a switching regulator power supply for a two-phase converter for powering a portable computer such as a laptop. It is a block diagram of the two-phase converter of FIG. It is a block diagram of the two-phase converter of FIG. It is a figure which shows the waveform in the circuit of FIG. FIG. 3 is a diagram illustrating another waveform of the circuit of FIG. 2. FIG. 2 is a block diagram of the VID control portion of FIG. 1 for setting the converter output voltage and overvoltage protection limit value in accordance with the VID code and select input. FIG. 2 is a block diagram of the VID control portion of FIG. 1 for setting the converter output voltage and overvoltage protection limit value in accordance with the VID code and select input.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Control chip 14 1st phase 16 2nd phase 50 Error amplifier 60 Oscillator 70, 80 Flip-flop 90, 100 PWM comparator 110 Capacitor 130 Error amplifier 140 Current detection amplifier

Claims (58)

A power supply for supplying electrical load to generate load characteristic data that determines power supply characteristics to be provided from the power supply to the electrical load,
A voltage regulator that is responsive to a reference signal to set a power supply characteristic and generates an output voltage to be provided as an input voltage for powering the electrical load;
A control circuit for generating the reference signal for the regulator;
The control circuit is responsive to load characteristic data from the electrical load and a selection input for selecting an electrical load type from a plurality of electrical load types, the selection input being an electrical load type. A power supply adapted to determine the load characteristic data by the control circuit and to generate a reference signal for the regulator.   The power supply of claim 1, wherein the electrical load comprises a microprocessor load, and wherein the plurality of electrical load types comprises a plurality of microprocessor load types.   The power supply according to claim 1, wherein the power supply characteristic includes an output voltage of the power supply, and the reference signal includes a reference voltage of a voltage regulator.   The power supply according to claim 1, wherein the power supply characteristic has an overvoltage protection limit value, and the reference signal includes an overvoltage protection limit voltage.   The electrical load includes a microprocessor load, the plurality of electrical load types includes a plurality of microprocessor load types, and the load characteristic data includes the load types of the plurality of microprocessors. Each has a digital voltage identification (VID) code associated with it, and the control circuit includes a VID control circuit having a digital-to-analog converter that receives a selection input for converting an input VID code into the reference voltage. The power supply according to claim 3. The VID control circuit further includes
6. The power supply of claim 5, comprising a plurality of VID input comparators, each comparator having a respective bit of the VID code as an input for comparing the respective bit with a threshold voltage.   The plurality of VID input comparators have an input coupled to a threshold voltage and a second input coupled to receive respective bits of the VID code input, wherein the threshold voltage is responsive to the selection input. The power supply of claim 6, wherein the power supply is selectable from a plurality of threshold voltages.   The power supply of claim 7, wherein the digital-to-analog converter is adapted to receive inputs from the plurality of VID input comparators.   The power supply of claim 8, further comprising a buffer circuit for receiving an output from the digital to analog converter and providing the reference voltage to the regulator.   The power supply according to claim 8, wherein the regulator includes a switching regulator.   The power supply according to claim 8, wherein the switching regulator includes a buck converter.   The power supply according to claim 11, wherein the switching regulator includes a multiphase buck converter.   The power supply of claim 11, wherein the reference voltage is provided to an input of an error amplifier of the buck converter.   The comparator circuit further includes a comparator circuit that receives the selection input as an input signal, the comparator circuit receiving a first signal for enabling the digital-analog converter to convert the VID code into the reference voltage. The power supply of claim 7, wherein the power supply is provided to the analog converter and further provides a second signal to the plurality of VID comparators for selecting the threshold voltage for the plurality of VID input comparators. .   The power supply according to claim 14, wherein the plurality of VID input comparators further include a switching circuit that is responsive to the second signal for selecting the threshold voltage.   An overvoltage protection limit selection circuit including a comparator that is responsive to an OVP reference voltage and an output voltage of a power supply, and the OVP reference voltage is selected by a selection switch that is responsive to the selection input; The power supply according to claim 5. A method for powering an electrical load from a power source to generate load characteristic data that determines power supply characteristics to be provided to the electrical load,
Responsive to a reference signal for setting the power supply characteristic, generating an output voltage to be provided as an input voltage for powering the electrical load;
Responsive to a load input from the electrical load and a selection input for selecting an electrical load type from a plurality of electrical load types, generating the reference signal for the regulator, and thus the selection A method for powering an electrical load, further comprising: allowing an input to determine the type of electrical load and evaluating the load characteristic data to generate the reference signal for the regulator.   The method of claim 17, wherein the electrical load comprises a microprocessor load and the plurality of electrical load types comprises a plurality of microprocessor load types.   The method of claim 17, wherein the power supply characteristic comprises an output voltage of the power source and the reference signal includes a reference voltage of the voltage regulator.   The method of claim 17, wherein the power supply characteristic includes an overvoltage protection limit value and the reference signal includes an overvoltage protection limit voltage. The electrical load includes a microprocessor load, the plurality of electrical load types includes a plurality of microprocessor load types, and the load characteristic data includes a load type of the plurality of microprocessors. 18. The method of claim 17, comprising a digital voltage identification (VID) code associated with each one of
The method further comprising receiving the selection input and converting the digital input VID code to a reference voltage.   The method of claim 21, further comprising providing a plurality of VID input comparators having each bit of the VID code as an input to compare each bit to a threshold voltage.   Each of the plurality of VID input comparators has an input coupled to a threshold voltage and a second input coupled to receive respective bits of the VID code input, wherein the threshold voltage is the selected input. 23. The method of claim 21, further comprising: selecting from a plurality of threshold voltages in response to.   24. The method of claim 23, comprising receiving input from the plurality of input VID comparators prior to the converting step.   25. The method of claim 24, further comprising buffering the reference voltage and providing the buffered reference voltage to the regulator.   25. The method of claim 24, wherein the regulator comprises a switching regulator.   The method of claim 24, wherein the switching regulator comprises a buck converter.   28. The method of claim 27, wherein the switching regulator comprises a multiphase buck converter.   28. The method of claim 27, further comprising providing the reference voltage to an input of an error amplifier of the buck converter.   Receiving the selection input as an input signal, providing a first signal for enabling the digital-to-analog converter to convert the VID code to the reference voltage, and further for the plurality of VID input comparators 24. The power supply of claim 23, further comprising providing a second signal for selecting a threshold voltage to the plurality of VID comparators.   31. The method of claim 30, further comprising using a switching circuit to select the threshold voltage in response to the second signal.   21. The method of claim 20, further comprising selecting an overvoltage protection limit value for the power source in response to the selection input. A power supply for powering a microprocessor load that generates a digital voltage identification (VID) code that determines power supply characteristics to be provided from the power supply to the microprocessor load,
A voltage regulator that is responsive to a reference voltage for setting an output voltage and generates an output voltage to be provided as an input voltage for powering the microprocessor load;
A control circuit for generating the reference signal for the regulator, the control circuit selecting a digital VID code from the microprocessor load and a microprocessor type from a plurality of microprocessor load types Is responsive to a selection input for the microprocessor, so that the selection input determines the type of microprocessor load, enables the VID code to be evaluated by the VID code, and generates a reference signal for the regulator Power supply that is. The VID control circuit is
34. The power supply of claim 33, comprising a digital-to-analog converter that receives the select input for converting an input VID code to the reference voltage. The VID control circuit further includes:
35. The power supply of claim 34, comprising a plurality of VID input comparators, each comparator having a respective bit of the VID code as an input for comparing a respective bit with a threshold voltage.   Each of the plurality of VID input comparators has an input coupled to a threshold voltage and a second input coupled to receive a respective bit of the VID code input, wherein the threshold voltage is the selection input. 36. The power supply of claim 35, wherein the power supply is selectable from a plurality of threshold voltages.   38. The power supply of claim 36, wherein the digital to analog converter is adapted to receive inputs from the plurality of VID input comparators.   38. The power supply of claim 37, further comprising a buffer circuit for receiving an output from the digital to analog converter and providing the reference voltage to the regulator.   38. The power supply of claim 37, wherein the regulator comprises a switching regulator.   38. The power supply of claim 37, wherein the switching regulator comprises a buck converter.   41. The power supply of claim 40, wherein the switching regulator comprises a multiphase buck converter.   41. The power supply of claim 40, wherein the reference voltage is provided to an input of an error amplifier of the buck converter.   The comparator circuit further includes a comparator circuit that receives the selection input as an input signal, the comparator circuit receiving a first signal for enabling the digital-analog converter to convert the VID code into the reference voltage. 37. The power supply of claim 36, wherein the power supply is adapted to provide a second signal to the plurality of VID comparators for providing to the analog converter and for selecting the threshold voltage for the plurality of VID input comparators.   44. The power supply of claim 43, wherein the plurality of VID input comparators further comprise a switching circuit responsive to the second signal for selecting the threshold voltage.   The circuit further includes an overvoltage protection limit selection circuit including a comparator that is responsive to an OVP reference voltage and an output voltage of the power source, and the OVP reference voltage is selected by a selection switch that is responsive to the selection input. 34. A power source according to claim 33. A method for powering a microprocessor load that generates a digital voltage identification (VID) code that determines an input voltage to be provided to the microprocessor load from a power source, the method comprising:
Responsive to a reference voltage to set an output voltage and generating an output voltage to be provided as an input voltage for powering the microprocessor load;
Responsive to a digital VID code from the microprocessor load and a selection input for selecting a microprocessor load type from a plurality of microprocessor load types, generating the reference signal for the regulator; Thus, the microprocessor load further comprises the step of allowing the selection input to evaluate the digital VID code to determine the type of microprocessor load and generate the reference signal for the regulator. A method for supplying power.   49. The method of claim 46, further comprising receiving the selection input and converting a digital input VID code to a reference voltage.   48. The method of claim 47, further comprising providing a plurality of VID input comparators having each bit of the VID code as an input to compare each bit with a threshold voltage.   Each of the plurality of VID input comparators has an input coupled to a threshold voltage and a second input coupled to receive a respective bit of the VID code input, wherein the threshold voltage is the selection input. 48. The method of claim 47, further comprising: selecting from a plurality of threshold voltages in response to.   50. The method of claim 49, comprising receiving input from the plurality of input VID comparators prior to the converting step.   51. The method of claim 50, further comprising buffering the reference voltage and providing the buffered reference voltage to the regulator.   51. The method of claim 50, wherein the regulator comprises a switching regulator.   51. The method of claim 50, wherein the switching regulator comprises a buck converter.   54. The method of claim 53, wherein the switching regulator comprises a multiphase buck converter.   54. The method of claim 53, further comprising providing a reference voltage to an input of an error amplifier of the buck converter.   Receiving the selection input as an input; and providing a first signal that enables a digital-to-analog converter to convert the VID code to the reference voltage; and the threshold for the plurality of VID input comparators. 50. The method of claim 49, further comprising providing a second signal to the plurality of VID input comparators to select a voltage.   57. The method of claim 56, further comprising using a switching circuit to select the threshold voltage in response to the second sign.   48. The method of claim 46, further comprising selecting an overvoltage protection limit value for a power supply in response to the selection input.

Images