JP2008301275A - Video output apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video output apparatus and video output method which, even when a video stream to be reproduced is not in a complete 3-2 pull-down form, can reproduce and output a 24p video signal without delaying or advancing output timing thereof and can synchronize the 24p video signal with audio. <P>SOLUTION: When complete 3-2 pull-down is being performed on a video signal after subjected to decode processing, a total sum of differences between the numbers of fields included in video frames and the numbers of fields included in video frames after subjected to actual decode processing is calculated and based on a result of the calculation, it is discriminated whether output timing of the video frame after subjected to decode processing is delayed or advanced with respect to original output timing. If delayed, decode processing is skipped while if advanced, the same video frame after subjected to decode processing is iteratively output. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an improvement in a video playback apparatus and a video playback method for playing back and outputting a 24p video signal (a progressive video signal having a frame rate of 23.976 Hz) from a 3-2 pulled down video stream.

  As is well known, in recent years, an optical disk such as a DVD (digital versatile disk) has become widespread as a digital recording medium. At present, a high-definition next-generation DVD standard called HD (high definition) DVD, blue-ray disc, etc. that enables higher density recording than DVD has been completed.

  In the next-generation DVD standard, a progressive video signal having a frame rate of 23.976 Hz is generated from a 3-2 pull-down video stream [60i video signal: interlaced video signal having a frame rate of 29.97 Hz (field rate of 59.97 Hz)]. It is stipulated that it has a function to reproduce and output the video.

  By the way, this rule presupposes that a video stream to be reproduced is input in a complete 3-2 pull-down format. That is, when the video stream to be played back is input in an incomplete 3-2 pull-down format, the output timing of the 24p video signal is delayed or advanced.

  On the other hand, the audio output timing is the same whether the 60i video signal is output or the 24p video signal is output. For this reason, a delay or advance in the output timing of the 24p video signal means that the video displayed on the screen is delayed or advanced with respect to the played sound, and the video and the audio are not synchronized. It will be.

In Patent Document 1, when the pull-down pattern is disturbed and the sound track is lost in synchronization, the number of generated output frames is compared with 5/4 times the received input image field, and the difference is accumulated to some extent. A configuration is disclosed in which a frame to be discarded or a frame to be inserted is generated with respect to the screen as it goes on.
JP-A-6-292075

  Therefore, the present invention has been made in consideration of the above circumstances, and even when the video stream to be reproduced is not in the complete 3-2 pull-down format, the 24p video signal is delayed or advanced in its output timing. An object of the present invention is to provide a video output apparatus and a video output method that can be reproduced and output without being generated and synchronized with audio.

  The video output device according to the present invention is intended for a device that reproduces and outputs a 24p video signal from a 3-2 pulled-down video stream. An input means for inputting a video stream; a decoding means for obtaining a video signal in units of frames by decoding the video stream input to the input means; and for a video signal subjected to the decoding process by the decoding means Calculating means for calculating the sum of the difference between the number of fields included in each video frame and the number of fields included in each video frame after the actual decoding process when complete 3-2 pulldown is performed; Determining means for determining whether the output timing of the decoded video frame is delayed or advanced with respect to the original output timing based on the calculation result of the calculating means; determined by the determining means to be delayed If the decoding means skips the decoding process and the determining means determines that the process is proceeding, It is obtained as a control means for repeatedly outputting the same video frame after sense.

  The video output method according to the present invention is intended for a method of reproducing and outputting a 24p video signal from a 3-2 pulled down video stream. A first step of inputting a video stream; a second step of performing a decoding process on the video stream input in the first step to obtain a video signal in frame units; and a decoding process in the second step The difference between the number of fields included in each video frame and the number of fields included in each video frame after the actual decoding process when complete 3-2 pulldown is performed on the applied video signal A third step of calculating the sum; and determining whether the output timing of the decoded video frame is delayed or advanced with respect to the original output timing based on the calculation result calculated in the third step The fourth step; and if it is determined that the process is delayed in the fourth step, the decoding process in the second step is skipped, and if it is determined that the process proceeds in the fourth step, It is obtained so as to include a fifth step of repeatedly outputting the same video frame after cord treatment.

  According to the above-described invention, when complete 3-2 pulldown is performed on the video signal after the decoding process, the number of fields included in each video frame and the actual video frame after the decoding process are The sum of differences from the number of included fields is calculated, and based on the calculation result, it is determined whether the output timing of the decoded video frame is delayed or advanced with respect to the original output timing. When it is determined that it is delayed, the decoding process is skipped, and when it is determined that it is advanced, the same video frame after the decoding process is repeatedly output. Even when the video stream to be played is not in the complete 3-2 pull-down format, it is possible to play back and output a 24p video signal without causing delay or advance in its output timing and to synchronize with the audio. It can be.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an outline of an optical disk reproducing apparatus described in this embodiment. That is, recording data read from the optical disk 11 such as an HD DVD via the optical head 12 is supplied to the data processing unit 13.

  The data processing unit 11 extracts, from the input data, a program stream compliant with the MPEG (moving picture experts group) -2 standard called VOB (video object) and its management information (title information). . Among these, sub-video data used for video data, audio data, caption information, and the like are superimposed on the program stream in a packet format.

  This program stream is supplied to the demultiplexer 14. The demultiplexer 14 separates video packets, audio packets, and sub-video packets from the input program stream. Further, the demultiplexer 14 sends necessary data to an STC (system time clock) management unit 15 to generate an STC necessary for each unit.

  The audio packet separated by the demultiplexer 14 is temporarily stored in the input buffer 16 and then supplied to the audio decoder 17. That is, the audio decoder 17 reads out and decodes the audio packet stored in the input buffer 16, and when the STC reaches a display time (PTS: presentation time stamp) described in the audio packet, the decoded audio frame Is output.

  The audio frame output from the audio decoder 17 is converted into an analog signal by a DAC (digital analog converter) 18 and then derived to the outside through an audio output terminal 19 for audio reproduction by a speaker (not shown). The

  The sub-video packet separated by the demultiplexer 14 is temporarily stored in the input buffer 20 and then supplied to the sub-picture decoder 21. That is, the sub-picture decoder 21 includes a decode process unit 22, a memory 23, and a post process unit 24. Among these, the decoding process unit 22 reads and decodes the sub-video packet stored in the input buffer 20 and stores the decoded sub-video data in the frame buffer 25. In addition, the decoding process unit 22 writes display information related to the decoded sub-picture data in the memory 23 in a FIFO (first in first out) format. Then, based on the display information stored in the memory 23, the post-processing unit 24 executes the command execution time (SP_DCSQ_STM: sub-picture display control command execution) calculated from the display time (PTS) described in the sub-picture packet by the STC. When (time) is reached, the decoded sub-picture frame stored in the frame memory 25 is output.

  However, the sub-picture data display control command is executed only at the timing of the frame rate of 29.97 Hz. For this reason, when reproducing the 24p video signal, the sub-video data decoded at the timing of 29.97 Hz is output through the frame buffer 25 at the timing of the frame rate of 23.976 Hz.

  The video packet separated by the demultiplexer 14 is temporarily stored in the input buffer 26 and then supplied to the video decoder 27. That is, the video decoder 27 includes a decode core unit 28, a memory 29, and a post process unit 30. Among these, the decode core unit 28 reads and decodes the video packet stored in the input buffer 26, and stores the decoded video data in the frame buffer 31. Further, the decode core unit 28 writes display information regarding the decoded video data in the memory 29 in the FIFO format. In this case, the display information includes six items as shown in FIG. As will be described in detail later, the post-processing unit 30, when the STC reaches the command execution time calculated from the display time (PTS) described in the video packet, based on the display information stored in the memory 29. Then, the decoded video frame stored in the frame memory 31 is output.

  The sub video frame output from the sub video decoder 21 and the video frame output from the video decoder 27 are supplied to the video mixer 32, multiplexed, and supplied to an HDMI (high definition multimedia interface) output unit 33. Then, after being converted into a transmission format compliant with the HDMI standard, it is led out through the video output terminal 34 and used for video display by a monitor or the like (not shown).

  Further, the management information extracted by the data processing unit 11 describes attribute information of each elementary data included in the program stream. For example, for video data, an encoding method (MPEG-2, MPEG-4 AVC, SMPTE VC-1, etc.), playback time, title, head address information of each cell included in the title, and the like are described. There is also a flag indicating that the video stream is encoded in 24p in order to realize 24p display.

  This management information is supplied to the main processor 36 via the buffer 35. The main processor 36 performs overall control of the operation of the optical disc playback apparatus, and receives various requests from the user and controls each part so that the requested contents are reflected. For example, when an output request for a 24p video signal is received, if the management information indicates that the video stream is encoded in 24p, the sub-picture decoder 21, the video decoder 27, and the HDMI output unit 33 are notified. , 24p video signal output request is generated.

  The HDMI output unit 33 generates a field ID signal and a field synchronization (sync) signal for the sub video decoder 21 and the video decoder 27. As a result, an interlaced video signal synchronized with the field rate of 59.94 Hz is generated when a 60i video signal with a frame rate of 29.97 Hz is reproduced, and a frame rate of 23.976 Hz is generated when a 24p video signal with a frame rate of 23.976 Hz is reproduced. Generates a progressive video signal synchronized with the.

  Here, it will be described that when a 24p video signal (progressive video signal with a frame rate of 23.976 Hz) is reproduced from a 3-2 pulled-down video stream, a synchronization shift occurs between video and audio.

  FIG. 3 shows a playback operation to a 24p video signal when a video stream to be played is input in a complete 3-2 pull-down format. In this case, in the video stream (60i video signal) pulled down 3-2, the value of pic_struct (see FIG. 4) in the display information (see FIG. 2) indicating the display method is 5 → 4 → 6. → It is described correctly by repeating 3 (display order). In FIG. 3, T is the top, B is the bottom, white circles indicate the top line, and black circles indicate the bottom line. That is, video frames 0, 2, 4,... With a field number of 3 and video frames 1, 3, 5,. At this time, the 10 field period and the timing of the 4 frame period at the time of 24p video output coincide with each other at 60i display timing (timing of frame 4), and synchronization between video and audio is maintained.

  On the other hand, when the video stream to be reproduced is not in the complete 3-2 pull-down format, for example, as shown in FIG. 5, the value of pic_struct of the video stream (60i video signal) is 5 → 4 → When 4 → 4 →... (Display order) is described, the 24p display timing is delayed by one field at the 60i display timing. Since the audio output timing does not change during 60i video output or 24p video output, the video is delayed by one field at the 60i display timing.

  Also, as shown in FIG. 6, when the value of pic_struct of the video stream (60i video signal) is described as 5 → 6 → 5 → 6 → ...... (display order), the 24p display timing is 60i display. It will advance 2 fields at the timing. Since the audio output timing does not change when the 60i video is output or when the 24p video is output, the video advances by two fields at the 60i display timing.

  Therefore, in this embodiment, the video decoder 27 causes the output timing of the 24p video signal to be delayed or advanced even when the video stream to be reproduced is not in the complete 3-2 pull-down format. Measures are taken to enable playback and output without being synchronized with audio.

  That is, as shown in FIG. 7, the post-processing unit 30 of the video decoder 27 includes a display information analysis unit 37, a 3-2 pull-down display prediction unit 38, a difference unit 39, an adder 40, and a display control unit. 41. Among these, the 3-2 pull-down display prediction unit 38, the difference unit 39, and the adder 40 are used only when a 24p video signal is output.

  First, the display information analysis unit 37 reads display information for each video from the memory 29, determines the display order of video frames (the order of reading from the frame buffer 31) based on the display_order information in the display information, and determines it. Display information is supplied to the display control unit 41 according to the order. The display information analysis unit 37 calculates the number of display fields of each video frame based on the value of pic_struct when the 24p video signal is output, and supplies the calculated number of display fields to one input terminal of the differencer 39. is doing. Further, the display information analysis unit 37 supplies the display field number of the video frame displayed first to the 3-2 pull-down display prediction unit 38. Then, the 3-2 pull-down display prediction unit 38 is reset with the number of display fields given from the display information analysis unit 37.

  When the 24p video signal is output, the 3-2 pull-down display predicting unit 38 uses the reset display field number as an initial value, and when the complete 3-2 pull-down is performed, the field obtained in the display order of the video frames. A numerical prediction value (if the initial value is 3, then 2 → 3 → 2 → 3 →...) Is supplied to the other input terminal of the differencer 39. In the difference unit 39, the difference between the number of fields and the predicted value is calculated for each video frame, and the difference value is supplied to the adder 40 and added. In this way, the sum of the difference between the number of display fields of each video frame when complete 3-2 pulldown is performed and the number of display fields of each actual video frame present in the program stream is calculated, The value is supplied to the display control unit 41.

  Specifically, as shown in FIG. 8, for each video frame 0, 1, 2, 3,..., The predicted value of the number of fields obtained from the 3-2 pull-down display prediction unit 38 is 3, 2. , 3, 2,..., And when the actual number of display fields of each video frame changes to 3, 2, 2, 2,..., The sum of the differences is 0, 0, 1, 1, ...... and accumulated. In this case, it means that the output timing of the 24p video signal is delayed.

  Also, as shown in FIG. 9, for each video frame 0, 1, 2, 3,..., The predicted number of fields obtained from the 3-2 pull-down display prediction unit 38 is 2, 3, 2, 3 When the actual number of display fields of each video frame changes to 2, 3, 3, 3,..., The sum of the differences is 0, 0, -1, -1,. And accumulated. In this case, it means that the output timing of the 24p video signal is advanced.

  The display control unit 41 executes video output based on pic_struct included in the display information supplied from the display information analysis unit 37 when the 60i video signal is output. The display control unit 41 ignores pic_struct when outputting a 24p video signal, and executes video output based on a 24p frame synchronization signal.

  Here, when the display control unit 41 determines from the sum supplied from the adder 40 that the video is delayed with respect to the audio, when the sum reaches a preset threshold, A decode skip request is issued to the decode core unit 28. When receiving the decode skip request, the decode core unit 28 skips decoding of the non-reference video immediately after that. That is, the video packet read from the input buffer 26 is discarded without being decoded. For example, when the threshold value is 2 fields at a frame rate of 29.97 Hz, the decoding core unit 28 skips decoding of the non-reference video for 2 fields display when the sum is 2.

  Further, when the display control unit 41 determines from the sum supplied from the adder 40 that the video is proceeding with respect to the audio, the 24p video is displayed when the sum reaches a preset threshold. Based on the frame synchronization signal (23.976 Hz) of the signal, the same video frame is redundantly displayed to adjust the video to be synchronized with the audio. For example, in the case where the above threshold value is 5 fields at a frame rate of 29.97 Hz, when the sum reaches 5, repeat display is executed for an extra 2 frame periods at a frame rate of 23.976 Hz. That is, the same frame is displayed for three frame periods.

  10 to 15 are flowcharts summarizing the processing operation of the post-processing unit 30. FIG. FIG. 10 shows the overall processing operation. That is, when the process is started (step S1), it is determined in step S2 whether or not a 3-2 pull-down video stream (frame rate 29.97 Hz) is input and an output request for a 24p video signal is received. Determined. If YES is determined, a 24p video signal output process is executed in step S3. If NO is determined, a playback process other than the 24p video signal output is executed in step S4. The Thereafter, in step S5, it is determined whether or not a video output end request has been received. If NO is determined, the process returns to step S2. If YES is determined, the process ends ( Step S6).

  FIG. 11 shows an example of the process executed in step S3 described above. That is, if YES is determined in step S2, whether or not display information is received is determined in step S7. If YES is determined, the display information is read from the memory 29 in step S8. . Thereafter, in step S9, it is determined whether or not the read display information is display information of the first video in the decoding order. If YES is determined, in step S10, a predetermined initialization process (first_decoded_picture = 0, previous_picture_skipped = 0, and the addition value of the adder 40 is set to 0). If NO is determined, the video other than the head is processed in the decoding order in step S11. The process proceeds to step S5.

  FIG. 12 shows an example of the process executed in step S11 described above. That is, if NO is determined in step S9, display information is arranged so that display_order of the display information is in ascending order in step S12, and then whether or not skipped_flag ≠ 1 of the display information is determined in step S13. Determined. If YES is determined, a 3-2 pull-down display prediction process is performed in step S14, a process by the difference unit 39 and the adder 40 is performed in step S15, and a display control process is performed in step S16. Is performed, and the process proceeds to step S5. If NO is determined in step S13, the previous_picture_skipped = 1 is set in step S17, and the process proceeds to step S5.

  FIG. 13 shows an example of the process executed in step S14 described above. That is, if YES is determined in step S13, it is determined in step S18 whether or not previous_picture_skipped ≠ 1. If NO is determined, the process proceeds to step S15. If YES is determined in step S18, it is determined in step S19 whether the current display information is that of the first video in the display order. If YES is determined, in step S20, the number of display fields is calculated from the pic_struct of the display information, and the result is set as an initial value in the 3-2 pull-down display prediction unit 38 [predictor = f ( pic_struct)], the process proceeds to step S15. If NO is determined in step S19, the predicted value of the number of display fields in 3-2 pull-down is toggled in step S21. That is, if the previous value is “3”, “2” is set. If it is “2”, it is set to “3” (predictor = 5-predictor), and the process proceeds to step S15.

  FIG. 14 shows an example of the process executed in step S15 described above. That is, after step S14, in step S22, it is determined whether or not an addition (−5) is set from the display control unit 41. If NO is determined, in step S23, previous_picture_skipped ≠ 1. It is determined whether or not there is. If YES is determined, in step S24, delta = f (pic_struct) -predictor is set in the adder 40, and the process proceeds to step S16. If NO is determined in step S23, 2 is set as a threshold value in the adder 40 in step S25, and the process proceeds to step S16. Further, if “YES” is determined in step S22, −5 is set as a threshold value in the adder 40 in step S26, and the process proceeds to step S16.

  FIG. 15 shows an example of the process executed in step S16 described above. That is, after step S15, in step S27, a frame is read from the frame buffer indicated by frame_buffer_number of the display information, and in step S28, it is determined whether or not the value of the adder 40 is equal to or less than the threshold value −2. If YES is determined, the current frame is displayed for one frame period at 24 Hz in step S29, and a decode skip request is emitted to the decode core unit 28 in step S30. If NO is determined in step S28, it is determined in step S31 whether the value of the adder 40 is +5 or more. If YES is determined, in step S32, the current frame is displayed for one frame period at 24 Hz, and in step S33, the adder −5 is set to −5. Further, if NO is determined in step S31, the current frame is displayed at 24 Hz for one frame period in step S34. After step S30, S33 or S34, in step S35, the previous_picture_skipped = 0 is set, and the process proceeds to step S5.

  FIG. 16 shows a flowchart summarizing the processing operations of the decode core unit 28. That is, when the process is started (step S36), skip_decode_instruction_flag = 0 is set in step S37, and in step S38, it is determined whether or not a decode skip request is received from the display control unit 41, and YES is determined. If so, skip_decode_instruction_flag = 1 is set in step S39. Then, after step S39 or if NO is determined in step S38, the video packet is read from the input buffer 26 in step S40, and the header of the picture layer or higher is decoded in step S41. Done.

  Thereafter, in step S42, it is determined whether or not skip_decode_instruction_flag = 1. If YES is determined, in step S43, the current video is a video that is not referenced and is displayed for two field periods. Is determined. If YES is determined, the data below the picture layer is discarded without being decoded in step S44, skipped_flag = 1 is set in step S45, and skip_decode_instruction_flag = 0 is set in step S46. .

  If NO is determined in step S42 or S43, the data in the layer below the picture layer is decoded and written in the frame buffer 31 in step S47, and skipped_flag = 0 is set in step S48.

  Then, after step S46 or S48, in step S49, information acquired from the header above the picture layer and skipped_flag are written in the memory 29, and in step S50, it is determined whether a video output end request has been received. If NO is determined, the process returns to step S38. If YES is determined, the process ends (step S51).

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by variously modifying the constituent elements without departing from the scope of the invention in the implementation stage. Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements according to different embodiments may be appropriately combined.

1 is a block diagram illustrating an outline of an optical disk reproducing device according to an embodiment of the present invention. The figure shown in order to demonstrate the display information used with the optical disk reproducing device in the embodiment. The figure shown in order to demonstrate the reproduction | regeneration operation | movement to the 24p video signal of the 3-2 pulldown video stream which the optical disk reproducing device in the embodiment performs. The figure shown in order to demonstrate pic_struct in the display information used with the optical disk reproducing | regenerating apparatus in the embodiment. The figure shown in order to demonstrate that there is a delay in the 24p video signal reproduced from the 3-2 pull-down video stream by the optical disc playback apparatus in the embodiment. The figure shown in order to demonstrate that progress arises in the 24p video signal reproduced | regenerated from the 3-2 pulldown video stream by the optical disk reproducing device in the embodiment. The block block diagram shown in order to demonstrate an example of the video decoder of the optical disk reproducing | regenerating apparatus in the embodiment. The figure shown in order to demonstrate the method of discriminating the delay of a 24p video signal by the video decoder of the optical disk reproducing device in the embodiment. The figure shown in order to demonstrate the method of discriminating the advance of 24p video signal by the video decoder of the optical disk reproducing device in the embodiment. The flowchart shown in order to demonstrate the 1st part of the processing operation of the post process part which the video decoder of the optical disk reproducing device in the embodiment has. The flowchart shown in order to demonstrate the 2nd part of the processing operation of the post process part which the video decoder of the optical disk reproducing device in the embodiment has. The flowchart shown in order to demonstrate the 3rd part of the processing operation of the post process part which the video decoder of the optical disk reproducing device in the embodiment has. 10 is a flowchart shown for explaining a fourth part of the processing operation of the post-processing unit included in the video decoder of the optical disc playback apparatus in the embodiment. The flowchart shown in order to demonstrate the 5th part of the processing operation of the post process part which the video decoder of the optical disk reproducing device in the embodiment has. The flowchart shown in order to demonstrate the remainder of the processing operation of the post process part which the video decoder of the optical disk reproducing device in the embodiment has. The flowchart shown in order to demonstrate the processing operation of the decoding core part which the video decoder of the optical disk reproducing device in the embodiment has.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Optical disk, 12 ... Optical head, 13 ... Data processing part, 14 ... Demultiplexer, 15 ... STC management part, 16 ... Input buffer, 17 ... Audio | voice decoder, 18 ... DAC, 19 ... Audio | voice output terminal, 20 ... Input buffer , 21 ... Sub-picture decoder, 22 ... Decode process section, 23 ... Memory, 24 ... Post-process section, 25 ... Frame buffer, 26 ... Input buffer, 27 ... Video decoder, 28 ... Decode core section, 29 ... Memory, 30 ... Post-processing unit, 31 ... frame buffer, 32 ... video mixer, 33 ... HDMI output unit, 34 ... video output terminal, 35 ... buffer, 36 ... main processor, 37 ... display information analysis unit, 38 ... 3-2 pull-down display prediction 39, difference unit, 40 ... adder, 41 ... display control unit.

Claims (8)

A video output device that reproduces and outputs a 24p video signal from a 3-2 pulled down video stream,
Input means for inputting the video stream;
Decoding means for performing a decoding process on the video stream input to the input means to obtain a video signal in units of frames;
The number of fields included in each video frame when a complete 3-2 pulldown is performed on the video signal decoded by the decoding means, and included in each video frame after the actual decoding process An arithmetic means for calculating a sum of differences from the number of fields generated;
Based on the calculation result of the calculation means, a determination means for determining whether the output timing of the decoded video frame is delayed or advanced with respect to the original output timing;
Control means for skipping the decoding process by the decoding means when determined to be delayed by the determining means, and for repeatedly outputting the same video frame after the decoding processing when determined to be advanced by the determining means; A video output device comprising: The computing means is
Predicting means for calculating the number of fields included in each video frame when complete 3-2 pulldown is performed based on display information included in each video frame after decoding processing;
An acquisition means for acquiring the number of fields included in each video frame after the actual decoding process based on the display information;
Difference means for obtaining a difference between the number of fields calculated by the prediction means and the number of fields acquired by the acquisition means;
The video output apparatus according to claim 1, further comprising an adding unit that adds the differences obtained by the difference unit.   The discriminating unit discriminates whether the output timing of the decoded video frame is delayed or advanced with respect to the original output timing when the sum calculated by the calculating unit reaches a preset threshold value. The video output apparatus according to claim 1, wherein: The control means includes
When the threshold for determining that the discrimination means is delayed is set to 2 fields at a frame rate of 29.97 Hz, the decoding process by the decoding means is skipped by 2 fields,
When the threshold for determining that the determination means is advanced is set to 5 fields at a frame rate of 29.97 Hz, video frames having a frame rate of 23.976 Hz after decoding are repeatedly displayed for 3 frames. The video output device according to claim 3. A video output method for reproducing and outputting a 24p video signal from a 3-2 pulled down video stream,
A first step of inputting the video stream;
A second step of performing a decoding process on the video stream input in the first step to obtain a video signal in units of frames;
The number of fields included in each video frame when the video signal subjected to the decoding process in the second step is completely 3-2 pulled down, and each video frame after the actual decoding process A third step of calculating a sum of differences from the number of fields included in
A fourth step of determining whether the output timing of the decoded video frame is delayed or advanced with respect to the original output timing based on the calculation result calculated in the third step;
If it is determined that the process is delayed in the fourth process, the decoding process in the second process is skipped. If it is determined that the process is advanced in the fourth process, the same video frame after the decoding process is performed. And a fifth step of repeatedly outputting the video output method. The third step includes
A prediction step of calculating the number of fields included in each video frame when complete 3-2 pulldown is performed based on display information included in each video frame after the decoding process;
Based on the display information, an acquisition step of acquiring the number of fields included in each video frame after the actual decoding process;
A difference step for obtaining a difference between the number of fields calculated in the prediction step and the number of fields acquired in the acquisition step;
6. The video output method according to claim 5, further comprising an addition step of adding the differences obtained in the difference step.   In the fourth step, when the sum calculated in the third step reaches a preset threshold, the output timing of the decoded video frame is delayed or advanced with respect to the original output timing. 6. The video output method according to claim 5, wherein it is determined whether or not the video is being played. The fifth step includes
When the threshold for determining that it is delayed in the fourth step is set to 2 fields at a frame rate of 29.97 Hz, the decoding process in the second step is skipped by 2 fields,
When the threshold value for determining that the process proceeds in the fourth step is set to 5 fields at a frame rate of 29.97 Hz, video frames having a frame rate of 23.976 Hz after decoding are repeatedly displayed for 3 frames. The video output method according to claim 7.

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