JP2008294318A - Semiconductor device, and manufacturing method thereof - Google Patents

Semiconductor device, and manufacturing method thereof Download PDF

Info

Publication number
JP2008294318A
JP2008294318A JP2007139939A JP2007139939A JP2008294318A JP 2008294318 A JP2008294318 A JP 2008294318A JP 2007139939 A JP2007139939 A JP 2007139939A JP 2007139939 A JP2007139939 A JP 2007139939A JP 2008294318 A JP2008294318 A JP 2008294318A
Authority
JP
Japan
Prior art keywords
semiconductor
wiring
semiconductor chip
semiconductor device
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007139939A
Other languages
Japanese (ja)
Inventor
Katsumi Abe
勝巳 阿部
Yoichi Oshima
洋一 大嶋
Kenichiro Fujii
健一郎 藤井
Toshinobu Kokatsu
俊亘 小勝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2007139939A priority Critical patent/JP2008294318A/en
Publication of JP2008294318A publication Critical patent/JP2008294318A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the quality deterioration of high-frequency signals without using complicated steps in a semiconductor device that is formed by stacking a plurality of semiconductor chips. <P>SOLUTION: Semiconductor chips 1 and 2 are cut out from a semiconductor wafer in such a state that both of the chips are connected to a connection wiring 10 between the chips. Conductor bumps 12 are formed on the wiring layer at the uppermost layer. A thermosetting resin is coated on the semiconductor chip 1 [Fig.(a)], and the semiconductor chip 2 is folded and bonded onto the semiconductor chip 1 [Fig.(b)]. The semiconductor chip is bonded onto a substrate 3 by an adhesive 4 [Fig(c)]. After the semiconductor chip 1 and the substrate 3 are connected by a bonding wire 6 and sealed by a sealing resin 7, an external terminal 9 is formed on the back face of the substrate 3 [Fig.(d)]. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置およびその製造方法に関し、特に複数の半導体チップを積層した構造を有する半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a structure in which a plurality of semiconductor chips are stacked and a manufacturing method thereof.

電子機器の小型・軽量・薄型化や高速・高機能化の進展に伴い、表面実装技術の高度化が要求されている。それに連れて、実装半導体装置の主流は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）に代表されるリード付きの周辺外部端子タイプからＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）等、裏面に電極を有する面外部端子タイプに移行しつつある。また、チップ実装面積削減のために、複数の半導体チップを積層し樹脂封止した、ＳｉＰ（Ｓｙｓｔｅｍ Ｉｎ Ｐａｃｋａｇｅ）と言われる、ＢＧＡ型部品が使われるようになってきた。
図６は、従来の代表的なＳｉＰの断面構造図である。図６（ａ）に示す例では、基板１０３上に接着剤１０４を介して、半導体チップ１０１、および、半導体チップ１０２が積層されている。各半導体チップの電極はボンディングワイヤ１０６により基板側電極パッドと電気的に接続され、基板内配線により、各半導体チップ間や外部端子１０９との電気的接続がなされている。これに対し、図６（ｂ）に示す例では、上側の半導体チップ２と下側の半導体チップ１との間を導電体バンプ１１２を介して電気的に接続する、所謂、フリップチップ（ＦＣ）接続を行っている。すなわち、半導体チップ１−２間は導電体バンプ１１２を介して接続され、そして半導体チップ１と外部端子１０９との間は、下側の半導体チップ１に接続されたボンディングワイヤ１０６および基板内配線により電気的に接続されている。これらの半導体装置において、半導体チップ１、２は、封止樹脂１０７により封止されている。また、図６（ｂ）に示す例では、半導体チップ１−２間はアンダーフィルとしての熱硬化性樹脂１０５により充填されている。 As electronic devices become smaller, lighter, thinner, and faster and more advanced, surface mounting technology is required to become more sophisticated. Accordingly, the mainstream of mounted semiconductor devices is shifting from peripheral external terminal types with leads typified by QFP (Quad Flat Package) to surface external terminal types having electrodes on the back surface, such as BGA (Ball Grid Array). is there. In order to reduce the chip mounting area, a BGA type component called SiP (System In Package) in which a plurality of semiconductor chips are stacked and sealed with resin has been used.
FIG. 6 is a sectional structural view of a conventional typical SiP. In the example illustrated in FIG. 6A, the semiconductor chip 101 and the semiconductor chip 102 are stacked on the substrate 103 with an adhesive 104 interposed therebetween. The electrodes of each semiconductor chip are electrically connected to the substrate-side electrode pads by bonding wires 106, and are electrically connected between the semiconductor chips and to the external terminals 109 by in-substrate wiring. On the other hand, in the example shown in FIG. 6B, a so-called flip chip (FC) in which the upper semiconductor chip 2 and the lower semiconductor chip 1 are electrically connected via the conductor bumps 112. Connecting. That is, the semiconductor chips 1-2 are connected via the conductor bumps 112, and the semiconductor chip 1 and the external terminal 109 are connected by the bonding wires 106 connected to the lower semiconductor chip 1 and the wiring in the substrate. Electrically connected. In these semiconductor devices, the semiconductor chips 1 and 2 are sealed with a sealing resin 107. In the example shown in FIG. 6B, the space between the semiconductor chips 1-2 is filled with a thermosetting resin 105 as an underfill.

図６（ａ）に示される従来例では、半導体チップ１０１と半導体チップ１０２間の信号の伝達は、二本のボンディングワイヤ、および、基板内配線を介して行われるため、その信号経路は高い配線抵抗を有し、大きな寄生容量がつく。この半導体チップ間にて授受される信号が、周波数の高い信号である場合、その配線抵抗、寄生容量が大きいために信号品質が劣化する恐れがある。これに対し、図６（ｂ）に示される技術では、半導体チップ１０１と半導体チップ１０２は、導電体バンプ１１２を介して電気的に接続されているため、両チップ間の信号伝達経路は低い配線抵抗の構造となっている。そして、配線に付く寄生容量も小さいため、高周波信号が劣化することを防ぐことができる。しかしながら、フリップチップ接続を行うためには、チップ間を精度良く位置決めをして圧接する必要が有るため、工程が煩雑となり、さらに、バンプ数が多くなると製造歩留りが低下するために、コストアップの要因となる。   In the conventional example shown in FIG. 6A, since signal transmission between the semiconductor chip 101 and the semiconductor chip 102 is performed via two bonding wires and wiring in the substrate, the signal path is high wiring. Has resistance and large parasitic capacitance. When a signal transmitted / received between the semiconductor chips is a signal having a high frequency, there is a risk that the signal quality is deteriorated because the wiring resistance and parasitic capacitance are large. On the other hand, in the technique shown in FIG. 6B, since the semiconductor chip 101 and the semiconductor chip 102 are electrically connected via the conductor bump 112, the signal transmission path between the two chips is a low wiring. It has a resistance structure. And since the parasitic capacitance attached to wiring is also small, it can prevent that a high frequency signal deteriorates. However, in order to perform flip chip connection, it is necessary to position and press the chips with high precision, so that the process becomes complicated, and further, as the number of bumps increases, the manufacturing yield decreases, which increases the cost. It becomes a factor.

そこで、前工程が完了した半導体ウエハを、個片化する前に、半導体ウエハの表面上に絶縁膜、配線パターン等を形成し、複数の半導体チップ間の電気的接続を取る方式が提案されている（例えば、特許文献１、２参照）。図７は、特許文献１にて提案された方式を示す説明図である。図７（ａ）、（ｂ）に示すように、半導体ウエハの回路形成面側に内部に配線パターンが形成され、外表面に外部端子が形成された絶縁膜２３０を形成し、半導体ウエハに溝を開け、個別の半導体チップ２２０に分離する。その後、図７（ｃ）に示すように、１つの半導体装置を構成する半導体チップ２２０ごとに絶縁膜２３０を裁断してスタッキング構造の構成部２１０を作成する。そして、図７（ｄ）に示すように、半導体チップ２２０を、接着剤２５０を介して積層してスタッキング構造の半導体装置を製造する。その際、最下層の半導体チップ上に形成された絶縁膜２３０の表面には予め外部端子２４０が形成されている。また、図８は、特許文献８にて提案された製造方法を示す説明図である。同図において縦の点線は半導体チップ３１０の区画部を示す。図８（ａ）に示すように、半導体ウエハ３１０の回路形成面側に内部に配線パターンが形成され、外表面に外部端子３４０が形成された絶縁膜３３０を形成する。次に、図８（ｂ）に示すように、半導体ウエハ３１０に溝３５０を形成し、続いて図８（ｃ）に示すように、絶縁膜３３０と半導体ウエハ３１０の両方を切断して、複数の半導体チップ３１０からなる、半導体装置を形成する単位毎のユニットに分離する。その後、図８（ｄ）に示すように、半導体ウエハ３１０から個別に分離されたユニットを折り曲げて半導体装置３００を形成する。
特開２００１−６８６１９号公報 特開２００５−５１１４４号公報 Therefore, a method has been proposed in which an insulating film, a wiring pattern, and the like are formed on the surface of a semiconductor wafer and electrical connection between a plurality of semiconductor chips is performed before the semiconductor wafer that has been subjected to the previous process is singulated. (For example, refer to Patent Documents 1 and 2). FIG. 7 is an explanatory diagram showing the method proposed in Patent Document 1. In FIG. As shown in FIGS. 7A and 7B, an insulating film 230 in which a wiring pattern is formed on the circuit forming surface side of the semiconductor wafer and an external terminal is formed on the outer surface is formed, and a groove is formed in the semiconductor wafer. Is opened and separated into individual semiconductor chips 220. Thereafter, as shown in FIG. 7C, the insulating film 230 is cut for each semiconductor chip 220 constituting one semiconductor device, thereby forming a stacking structure component 210. Then, as shown in FIG. 7D, semiconductor chips 220 are stacked with an adhesive 250 interposed therebetween to manufacture a semiconductor device having a stacking structure. At this time, external terminals 240 are formed in advance on the surface of the insulating film 230 formed on the lowermost semiconductor chip. Moreover, FIG. 8 is explanatory drawing which shows the manufacturing method proposed by patent document 8. In FIG. In the figure, the vertical dotted lines indicate the partition portions of the semiconductor chip 310. As shown in FIG. 8A, an insulating film 330 in which a wiring pattern is formed inside on the circuit forming surface side of the semiconductor wafer 310 and an external terminal 340 is formed on the outer surface is formed. Next, as shown in FIG. 8B, a groove 350 is formed in the semiconductor wafer 310, and subsequently, as shown in FIG. 8C, both the insulating film 330 and the semiconductor wafer 310 are cut to obtain a plurality of grooves. The semiconductor chip 310 is divided into units for each unit forming the semiconductor device. After that, as shown in FIG. 8D, the unit individually separated from the semiconductor wafer 310 is bent to form the semiconductor device 300.
JP 2001-68619 A JP 2005-511144 A

特許文献１、２に記載された、半導体ウエハ上に形成された配線層を利用して積層された半導体チップ間を接続する方式によると、ワイヤボンディングや、フリップチップ接続を行わずに電気的接続をとることができるため、低コストで、半導体チップ間の配線長の比較的短い実装構造を得ることができる。しかしながら、電気信号の周波数が高くなるほど配線抵抗による信号劣化が顕著になるため、近年の電子機器の高速化の趨勢に対応して配線抵抗をより低くすることが課題となっている。
本発明の目的は、複数の半導体チップを積層した半導体装置に対し、高周波信号の劣化を抑制できるようにすることであり、また煩雑な工程を用いることなくその実装構造を実現できるようにすることである。 According to the method described in Patent Documents 1 and 2 for connecting semiconductor chips stacked using a wiring layer formed on a semiconductor wafer, electrical connection without wire bonding or flip chip connection is performed. Therefore, a mounting structure with a relatively short wiring length between semiconductor chips can be obtained at low cost. However, signal degradation due to wiring resistance becomes more noticeable as the frequency of the electrical signal becomes higher. Therefore, it is a problem to lower the wiring resistance in response to the recent trend of higher speed electronic devices.
An object of the present invention is to enable a semiconductor device in which a plurality of semiconductor chips are stacked to suppress deterioration of a high-frequency signal, and to realize a mounting structure without using a complicated process. It is.

上記の目的を達成するため、本発明によれば、二つの半導体チップがそれぞれの回路形成面同士が対向するように積層され、各半導体チップの最上層の配線同士が導電体バンプを介して接続されると共に、一配線層において各半導体チップの配線パターンの延長部同士が接続されていることを特徴とする半導体装置、が提供される。   In order to achieve the above object, according to the present invention, two semiconductor chips are laminated so that their circuit forming surfaces face each other, and the wirings on the uppermost layer of each semiconductor chip are connected via conductor bumps. In addition, a semiconductor device is provided in which the extension portions of the wiring patterns of the respective semiconductor chips are connected to each other in one wiring layer.

〔作用〕
本発明によれば、積層した半導体チップ間の電気的接続をとる方法として、半導体チップの配線層領域の配線パターンと、半導体チップ表面の導電体バンプを選択することができる。したがって、配線長が長くなることで電気的特性が劣化する信号、すなわち、高周波信号には、導電体バンプによる短距離の電気的連結を適用し、それ以外の信号には、配線層領域の配線パターンによる長距離の電気的連結を適用することができる。半導体チップ間に位置決め用のダミー配線を設けておくことにより、折り返したときの位置ずれ量を小さくすることができ、しかも、導電体バンプの数を最小としているため、バンプの大きさ、バンプの間隔を大きくすることができるため、高精度の位置決めを行なうことなく、半導体チップ表面の導電体バンプの接続を行うことができる。 [Action]
According to the present invention, a wiring pattern in a wiring layer region of a semiconductor chip and a conductor bump on the surface of the semiconductor chip can be selected as a method for establishing an electrical connection between stacked semiconductor chips. Therefore, short-distance electrical connection using conductor bumps is applied to signals whose electrical characteristics deteriorate due to long wiring length, that is, high-frequency signals, and wiring in the wiring layer region is applied to other signals. A long distance electrical connection by pattern can be applied. By providing dummy wirings for positioning between semiconductor chips, the amount of misalignment when folded can be reduced, and the number of conductor bumps is minimized, so the size of the bumps, Since the interval can be increased, it is possible to connect the conductor bumps on the surface of the semiconductor chip without performing highly accurate positioning.

本発明によれば、半導体チップ間の電気的接続に関し、配線長を短くする必要がある信号線は半導体チップ表面の導電体バンプ、それ以外の信号線は半導体チップの配線層の配線と選択することができるために、高周波信号の劣化を抑制することができる。それと共に、通常のフリップチップ接続と比べて導電体バンプのバンプ数を低減することができるため、本発明によれば、設計の自由度があがり、製造工程が簡素化されかつ製造歩留まりを上げることができる。また、本発明によれば、従来のように上側半導体チップに対しワイヤボンディングした場合に比べて、樹脂封止後の部品高さを低くすることができる。
これらにより、低コストで部品高さの低い高周波信号の劣化の抑制された半導体装置を実現することができる。 According to the present invention, regarding electrical connection between semiconductor chips, a signal line that needs to be shortened is selected as a conductor bump on the surface of the semiconductor chip, and other signal lines are selected as wirings in the wiring layer of the semiconductor chip. Therefore, deterioration of the high frequency signal can be suppressed. At the same time, the number of conductor bumps can be reduced as compared with the normal flip chip connection. Therefore, according to the present invention, the degree of design freedom is increased, the manufacturing process is simplified, and the manufacturing yield is increased. Can do. Further, according to the present invention, it is possible to reduce the height of the component after resin sealing as compared with the conventional case of wire bonding to the upper semiconductor chip.
As a result, it is possible to realize a semiconductor device in which deterioration of a high-frequency signal with a low component height and low cost is suppressed.

次に、本発明の実施の形態について図面を参照して詳細に説明する。
〔第１の実施の形態〕
図１は、本発明の第1の実施の形態を示す図であって、図１（ａ）は本実施の形態の断面図〔図１（ｂ）のＡ−Ａ′線での断面図〕であり、図１（ｂ）は、封止樹脂を除去してみた上面図、図１（ｃ）は、図１（ａ）のチップ折り返し部を拡大した断面図、図１（ｄ）は、図１（ｃ）を右側から見た側面図である。但し、図を見やすくするために、図（ｃ）、（ｄ）では封止樹脂および基板が除去されている。
図１に示されるように、基板３上に半導体チップ１は裏面を接着剤４で固定された状態で搭載されている。その半導体チップ１とチップ間接続配線１０と位置決め機能を有する補強用ダミー配線１１で接続された半導体チップ２は、半導体チップ１と表層配線領域を対向するように、熱硬化性樹脂５を介して、張り合わされている。ここで、半導体チップ１の一部が、半導体チップ２と対向しないように設計されており、半導体チップ１の表面が露出した領域は、電極パッドが設けられたボンディングエリア１ａとなされており、その電極パッドは、基板３上の電極パッドとボンディングワイヤ６を介して電気的に接続されている。尚、半導体チップ１と半導体チップ２は、配線層に設けられた配線パターンだけではなく、半導体チップ表面に形成された導電体バンプ１２で電気的に接続されており、配線長を短くする必要がある信号線は、これを介して接続されている。基板３上に搭載された、半導体チップ１、半導体チップ２、ボンディングワイヤ６、チップ間接続配線１０、補強用ダミー配線１１は、封止樹脂７により封止されており、外部雰囲気および衝撃から保護されている。基板裏面に、基板表面に設けたワイヤボンディング用電極パッドと基板内配線を介して電気的に接続された電極パッド８が設けられており、電極パッド８上にははんだボールである外部端子９が設置されている。尚、図１（ｂ）、（ｄ）に示す、補強用ダミー配線１１は、チップを折り返した際の応力、特にねじれ方向の応力が、チップ間接続配線に加わらないように、チップ間接続配線をはさむように形成され、チップ間接続配線よりも配線長が短くなっており、十分な強度を確保するために、チップ間接続配線に比べて幅広の配線となっている。
本発明の特徴は、図１（ｃ）に示されるように、半導体チップは折り返して積層されており、チップ間の電気的接続は、半導体チップの一配線層からの延長部であるチップ間接続配線１０とチップ表面の導電体バンプ１２で行うことにある。 Next, embodiments of the present invention will be described in detail with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG. 1A is a cross-sectional view of the present embodiment (a cross-sectional view taken along line AA ′ in FIG. 1B). 1 (b) is a top view of the sealing resin removed, FIG. 1 (c) is an enlarged cross-sectional view of the chip folding portion of FIG. 1 (a), and FIG. It is the side view which looked at FIG.1 (c) from the right side. However, in order to make the drawing easier to see, the sealing resin and the substrate are removed in FIGS.
As shown in FIG. 1, the semiconductor chip 1 is mounted on the substrate 3 with the back surface fixed with an adhesive 4. The semiconductor chip 2 connected to the semiconductor chip 1 and the inter-chip connection wiring 10 by the reinforcing dummy wiring 11 having a positioning function is interposed through the thermosetting resin 5 so that the semiconductor chip 1 and the surface wiring area are opposed to each other. , Are stuck together. Here, a part of the semiconductor chip 1 is designed so as not to face the semiconductor chip 2, and a region where the surface of the semiconductor chip 1 is exposed is a bonding area 1a provided with electrode pads. The electrode pad is electrically connected to the electrode pad on the substrate 3 through the bonding wire 6. The semiconductor chip 1 and the semiconductor chip 2 are electrically connected not only by the wiring pattern provided in the wiring layer but also by the conductor bumps 12 formed on the surface of the semiconductor chip, and it is necessary to shorten the wiring length. A certain signal line is connected through this. The semiconductor chip 1, the semiconductor chip 2, the bonding wire 6, the inter-chip connection wiring 10, and the reinforcing dummy wiring 11 mounted on the substrate 3 are sealed with a sealing resin 7 and are protected from the external atmosphere and impact. Has been. On the back surface of the substrate, there are provided electrode pads 8 electrically connected to the electrode pads for wire bonding provided on the front surface of the substrate through wiring in the substrate, and external terminals 9 which are solder balls are provided on the electrode pads 8. is set up. The reinforcing dummy wirings 11 shown in FIGS. 1B and 1D are connected to each other so that stress when the chip is folded, particularly stress in the twisting direction, is not applied to the interchip connecting wiring. The wiring length is shorter than the inter-chip connection wiring, and the wiring is wider than the inter-chip connection wiring to ensure sufficient strength.
As shown in FIG. 1C, the feature of the present invention is that the semiconductor chips are folded and stacked, and the electrical connection between the chips is an inter-chip connection that is an extension from one wiring layer of the semiconductor chip. The wiring 10 and the conductor bumps 12 on the chip surface are used.

（製法の説明）
次に、図２、図３を参照して本発明の第１の実施の形態の製造方法について説明する。図２は、本実施の形態の製造方法の前半部分で、Ｓｉウエハの状態で、ダイシングが完了するまでの工程を示している。図３は、本実施の形態の製造方法の後半部分で、ダイシングが完了してから、半導体装置が完成するまでの工程を示している。特に、図２では、本発明の特徴を分かりやすく示すために、半導体チップの折り返し領域近傍を拡大して示してある。
図２において、点線に挟まれた領域が折り返し領域であり、その左側が半導体チップ１領域、その右側が半導体チップ２領域である。図２（ａ）は、一般的な半導体装置製造プロセスの前工程により、半導体ウエハ１３の表面領域内に不純物拡散領域（図示なし）が形成され、その上に第一絶縁層、第一配線層１５、第二絶縁層、第二配線層１６、第三絶縁層１７が順次形成された後の断面図である。第一配線層１５を形成する際に、折り返し領域にダイシングストッパ用ダミー配線１４を形成しておく。ダミー配線１４は、レイアウト上の追加で形成可能であり、これを形成するために特に製造工程を増やす必要はない。 (Description of manufacturing method)
Next, a manufacturing method according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 2 shows a process until dicing is completed in the state of the Si wafer in the first half of the manufacturing method of the present embodiment. FIG. 3 shows the process from the completion of dicing to the completion of the semiconductor device in the latter half of the manufacturing method of the present embodiment. In particular, in FIG. 2, the vicinity of the folded region of the semiconductor chip is shown in an enlarged manner for easy understanding of the features of the present invention.
In FIG. 2, a region sandwiched between dotted lines is a folded region, a left side thereof is a semiconductor chip 1 region, and a right side thereof is a semiconductor chip 2 region. In FIG. 2A, an impurity diffusion region (not shown) is formed in the surface region of the semiconductor wafer 13 by a pre-process of a general semiconductor device manufacturing process, and a first insulating layer and a first wiring layer are formed thereon. 15 is a cross-sectional view after a second insulating layer, a second wiring layer 16, and a third insulating layer 17 are formed in order. When the first wiring layer 15 is formed, a dicing stopper dummy wiring 14 is formed in the folded region. The dummy wiring 14 can be additionally formed on the layout, and it is not necessary to increase the number of manufacturing steps in order to form the dummy wiring 14.

図２（ｂ）は、図２（ａ）で形成された第三絶縁層１７に対し、第二配線層１６と第三配線層を電気的に接続するためのビアホールを形成する工程である。第三絶縁層１７上にパターニングされたフォトレジスト膜１８を形成し、これをマスクにエッチングすることにより、所定の個所にビアホールを開設し、第二配線層１６の表面を露出させる。このとき、折り返し領域に凹形状を設けるためのくぼみを形成する。尚、折り返し領域の凹形状は、チップ間接続配線を形成する箇所に設けるが、位置決め用となる補強用ダミー配線を形成する箇所には設けない。
図２（ｃ）は、第三配線層を形成する工程である。図２（ｂ）の工程でビアホールおよびくぼみを形成した後、例えば、下地層形成とめっきにより第三配線層１９を形成する。このとき、ビアホールと折り返し領域のくぼみの幅は大きく異なるため、ビアホールは導電体で埋め込まれるものの、くぼみは、側面および底面に導電層が形成されるのみで、埋め込まれることはない。したがって、折り曲げ領域に凹形状のチップ間接続配線を形成することができる。凹形状を持つチップ間接続配線よりも、凹形状を持たない補強用ダミー配線の方が、配線長が短くなるため、折り返したときの応力は、補強用ダミー配線に集中し、チップ間接続配線において断線が発生する可能性は低くなる。
尚、第二配線層に凹部の底となる配線パターンを形成し、この両端に、第三配線層と第二配線層を電気的に接続するビアを形成することでも、凹形状のチップ間接続配線を形成することは可能である。しかし、別々の工程で配線を形成するために密着力が低いことから、互いの接続面において断線が起こりやすくなる。 FIG. 2B is a step of forming a via hole for electrically connecting the second wiring layer 16 and the third wiring layer to the third insulating layer 17 formed in FIG. A patterned photoresist film 18 is formed on the third insulating layer 17 and is etched using this as a mask, thereby opening a via hole at a predetermined location and exposing the surface of the second wiring layer 16. At this time, a recess for forming a concave shape in the folded region is formed. The concave shape of the folded region is provided at a location where the inter-chip connection wiring is formed, but is not provided at a location where the reinforcing dummy wiring for positioning is formed.
FIG. 2C shows a step of forming a third wiring layer. After forming the via holes and the recesses in the step of FIG. 2B, the third wiring layer 19 is formed by, for example, forming a base layer and plating. At this time, since the width of the recess of the via hole and the folded region is greatly different, the via hole is filled with the conductor, but the recess is not filled only with the conductive layer formed on the side surface and the bottom surface. Therefore, a concave interchip connection wiring can be formed in the bent region. The length of the dummy wiring for reinforcement that does not have a concave shape is shorter than that of the wiring that has a concave shape, and the stress when folded is concentrated on the dummy wiring for reinforcement. In this case, the possibility of disconnection is reduced.
It is also possible to form a concave interchip connection by forming a wiring pattern that forms the bottom of the recess in the second wiring layer and forming vias that electrically connect the third wiring layer and the second wiring layer at both ends thereof. It is possible to form wiring. However, since the contact force is low because the wiring is formed in a separate process, disconnection is likely to occur at the connection surfaces.

図２（ｄ）は、第四配線層を形成する工程である。第三配線層１９の形成工程と同様、一般的な半導体素子製造プロセスの前工程における配線形成工程で、第四絶縁層２０、第四配線層２１、第五絶縁層２２を順次形成する。ここでは、後工程で、導電体バンプを形成し圧接するために、表層の第五絶縁層２２を研磨により平坦化している。
図２（ｅ）は、チップ折り返し時に、妨げとなるチップ間接続配線上の絶縁層を除去する工程である。第五絶縁層２２の表面にパターニングされたフォトレジスト膜２３を形成し、これをマスクに、折り返し領域の第五、第四絶縁層をウエット法にてエッチングする。このとき、第三配線層を完全に露出させる必要はなく、折り返し時に抵抗とならない程度に絶縁層を薄くすればよい。その後、半導体チップ厚を薄くするためにウエハ表面に保護用膜を貼付したのち、ウエハ裏面を研削加工する。 FIG. 2D is a step of forming the fourth wiring layer. Similar to the formation process of the third wiring layer 19, the fourth insulating layer 20, the fourth wiring layer 21, and the fifth insulating layer 22 are sequentially formed in the wiring forming process in the previous process of the general semiconductor element manufacturing process. Here, in the subsequent step, the surface of the fifth insulating layer 22 is flattened by polishing in order to form a conductor bump and press-contact it.
FIG. 2E shows a step of removing the insulating layer on the inter-chip connection wiring that becomes an obstacle when the chip is folded back. A patterned photoresist film 23 is formed on the surface of the fifth insulating layer 22, and using this as a mask, the fifth and fourth insulating layers in the folded region are etched by a wet method. At this time, it is not necessary to completely expose the third wiring layer, and the insulating layer may be thinned so as not to become a resistance when folded. Thereafter, in order to reduce the thickness of the semiconductor chip, a protective film is applied to the wafer surface, and then the back surface of the wafer is ground.

図２（ｆ）は、半導体チップ表面に導電体バンプを形成し、半導体ウエハから、各半導体チップに個片化する工程である。図２（ｄ）の研磨工程により、第四配線層２１表面は露出しているため、簡単に洗浄した後、所定箇所に導電体バンプを形成することができる。半導体チップを折り返した際、互いに向かい合うように、半導体チップ１、半導体チップ２上にそれぞれ導電体バンプ１２を形成する。導電体バンプは、例えばスクリーン印刷法若しくは転写法を用いて導電性ペーストを塗布することによって形成することができる。次に、一般的な半導体前工程のダイシング工程と同様に、半導体ウエハを切断する。互いに電気的に接続された半導体チップをグループとし、グループごとに、切断を行う。その後、切り出された半導体個片を、チップ間接続配線を切断することなく、Ｓｉ層のみを切断する。すなわち、半導体チップ１と半導体チップ２の間の折り返し領域に対し、例えばレーザビームを照射し、半導体チップ裏面より、溶断していく。Ｓｉ層を完全に切断したところで、ダイシングストッパ用ダミー配線１４が露出してくる。これを検知し、切断をとめる。これにより、配線にダメージを与えることなく、チップ間接続用配線１０下部のＳｉ層を切断することができる。   FIG. 2F shows a process of forming conductor bumps on the surface of the semiconductor chip and dividing the semiconductor wafer into individual semiconductor chips. Since the surface of the fourth wiring layer 21 is exposed by the polishing process of FIG. 2D, the conductor bumps can be formed at predetermined positions after simple cleaning. Conductor bumps 12 are formed on the semiconductor chip 1 and the semiconductor chip 2 so as to face each other when the semiconductor chip is folded. The conductor bump can be formed by applying a conductive paste using, for example, a screen printing method or a transfer method. Next, the semiconductor wafer is cut in the same manner as the dicing process in the general semiconductor pre-process. Semiconductor chips that are electrically connected to each other are grouped, and cutting is performed for each group. Thereafter, only the Si layer is cut from the cut semiconductor piece without cutting the inter-chip connection wiring. That is, the folded region between the semiconductor chip 1 and the semiconductor chip 2 is irradiated with, for example, a laser beam and melted from the back surface of the semiconductor chip. When the Si layer is completely cut, the dicing stopper dummy wiring 14 is exposed. Detect this and stop cutting. Thereby, the Si layer under the inter-chip connection wiring 10 can be cut without damaging the wiring.

図３（ａ）、（ｂ）は、チップ折り返し工程である。個片化された半導体チップ１の表面に、熱硬化性樹脂５を塗布する。その後、半導体チップ２を吸着し、半導体チップ１と対向するように折り返し、圧接を行う。本発明によれば、半導体チップ１と半導体チップ２は、完全に分断されてはおらず、配線で接続されており、位置決め機能を有する補強用ダミー配線の長さで折り返し点が決まるため、高精度の位置決めを行なうことなくチップ間の接続を実現することができる。次工程のマウントの際に、問題がないように、半導体チップ１と半導体チップ２の裏面は、できるだけ平行になるように保持することが望ましい。このため、接続用の導電体バンプを、圧接の際に応力が均一に分散する位置に配置することが望ましい。半導体チップ１に対し半導体チップ２のチップサイズを小さくすることで、半導体チップ１の表面の露出した部分、ボンディングエリアを設けることができる。通常、半導体ウエハ厚を薄くした場合、チップを個片化した際、Ｓｉと配線層の熱膨張係数の違いにより反りが発生し、また抗折強度が低下するが、本発明によれば、チップの層構成は、対称構造となるため、熱膨張率差により反りの発生はなく、抗折強度も比較的高く保たれる。   3A and 3B show a chip folding process. A thermosetting resin 5 is applied to the surface of the separated semiconductor chip 1. Thereafter, the semiconductor chip 2 is adsorbed, folded back so as to face the semiconductor chip 1, and pressed. According to the present invention, the semiconductor chip 1 and the semiconductor chip 2 are not completely separated and are connected by wiring, and the turn-around point is determined by the length of the reinforcing dummy wiring having a positioning function. It is possible to realize the connection between the chips without positioning. It is desirable to hold the back surfaces of the semiconductor chip 1 and the semiconductor chip 2 so as to be as parallel as possible so that there is no problem when mounting in the next process. For this reason, it is desirable to arrange the conductor bumps for connection at positions where the stress is uniformly dispersed during the pressure contact. By reducing the chip size of the semiconductor chip 2 with respect to the semiconductor chip 1, an exposed portion of the surface of the semiconductor chip 1 and a bonding area can be provided. Normally, when the semiconductor wafer thickness is reduced, when the chip is separated into pieces, warpage occurs due to the difference in thermal expansion coefficient between Si and the wiring layer, and the bending strength is reduced. Since this layer structure has a symmetrical structure, there is no warpage due to the difference in thermal expansion coefficient, and the bending strength is kept relatively high.

図３（ｃ）、（ｄ）は、半導体チップのパッケージング工程である。一般的な半導体の後工程と同様に、配線パターンが形成された基板３上に、折り返して熱硬化性樹脂で接着された半導体チップ１、２を、接着剤４を介して固定する。基板３の裏面には、外部接続用の電極パッド８が面状に配置されている。その後、半導体チップ１上に形成された電極パッドと基板上の電極パッドとをボンディングワイヤ６を介して接続する。さらに、半導体チップ１、２、チップ間接続配線１０、補強用ダミー配線１１、ボンディングワイヤ６を、熱硬化性樹脂からなる封止樹脂７により封止した後、基板裏面の電極パッド８上に外部端子９を設ける。以上により、本発明の第１の実施の形態の半導体装置を製造することができる。   3C and 3D show a semiconductor chip packaging process. Similar to a general semiconductor post-process, the semiconductor chips 1 and 2 that are folded back and bonded with a thermosetting resin are fixed on the substrate 3 on which the wiring pattern is formed via the adhesive 4. On the back surface of the substrate 3, electrode pads 8 for external connection are arranged in a planar shape. Thereafter, the electrode pads formed on the semiconductor chip 1 and the electrode pads on the substrate are connected via bonding wires 6. Further, after the semiconductor chips 1 and 2, the inter-chip connection wiring 10, the reinforcing dummy wiring 11, and the bonding wire 6 are sealed with a sealing resin 7 made of a thermosetting resin, the semiconductor chip 1 and 2, the inter-chip connecting wiring 10 Terminal 9 is provided. As described above, the semiconductor device according to the first embodiment of the present invention can be manufactured.

ここでは、半導体チップの配線層数を四層とし、チップ間接続配線を第三層から引き出しているが、配線層数は四層に限られず、またチップ間接続配線を引き出す配線層はいずれでも可能である。また、チップ間接続配線１０と補強用ダミー配線１１は、同一配線層にて形成していたが、必ずしもそのようにする必要はなく、例えば、チップ間接続配線の上層に補強用ダミー配線を形成し、チップを折り返したときに、補強用ダミー配線がチップ間接続配線の内側にくるようにしてもよい。また、上記実施の形態では、半導体ウエハの裏面を研磨してウエハを薄層化した後に導電体パッドを形成していたが、この方法に代え、導電体パッドを形成した後にウエハ裏面の研磨を行なうようにしてもよい。その場合には、導電体パッドはめっき法などにより形成することが望ましい。さらに、上記実施の形態では、半導体ウエハをグループごとに切り出した後に、折り返し領域のＳｉ層を切断していたが、この順番を逆にしてもよい。   Here, the number of wiring layers of the semiconductor chip is four layers, and the inter-chip connection wiring is drawn out from the third layer. However, the number of wiring layers is not limited to four layers, and any wiring layer for drawing out the inter-chip connection wiring can be used. Is possible. Further, although the inter-chip connection wiring 10 and the reinforcing dummy wiring 11 are formed in the same wiring layer, it is not always necessary to do so. For example, the reinforcing dummy wiring is formed in the upper layer of the inter-chip connection wiring. However, when the chip is folded, the reinforcing dummy wiring may be located inside the inter-chip connection wiring. Further, in the above embodiment, the conductor pad is formed after the back surface of the semiconductor wafer is polished and the wafer is thinned. Instead of this method, the back surface of the wafer is polished after the conductor pad is formed. You may make it perform. In that case, the conductor pad is preferably formed by a plating method or the like. Further, in the above-described embodiment, the Si layer in the folded region is cut after the semiconductor wafer is cut out for each group, but this order may be reversed.

〔第２の実施の形態〕
図４は、本発明の第２の実施の形態を示す図であって、図４（ａ）〜（ｄ）は、それぞれ第１の実施の形態の図１（ａ）〜（ｄ）に対応する図である。図４において、第１の実施の形態を示す図１と同等の部分には同一の参照符号を付し、重複する説明は省略する。本実施の形態においては、図４（ｄ）に示すように、チップ間接続配線１０を斜めに引き出している。このように構成することにより、単にくぼみ（溝形状）を設けた場合と比較して、チップ間接続配線長をより長くすることができる。そのため、配線の屈曲性が増し、チップ折り返しによって生じる配線の応力を低下させることができひずみを緩和することができる。この場合、チップ間の配線数を多くとることができないため、チップ間の信号線数の少ない条件に限定される。製造方法については、チップ間接続配線のパターン変更のみで、第１の実施の形態と同様にして製造することが可能である。
第２の実施の形態は、チップ間の配線パターンを斜行させることで、配線の屈曲性を高めていたが、これに代え、配線パターンは第１の実施の形態のようにチップの辺に直交させ、折り返し領域に設ける下層絶縁層でのくぼみを複数個として、チップ間接続配線を凹、凸部が複数の波型形状とすることで、配線長を長くして、配線の屈曲性を高めるようにしてもよい。 [Second Embodiment]
FIG. 4 is a diagram showing a second embodiment of the present invention. FIGS. 4A to 4D correspond to FIGS. 1A to 1D of the first embodiment, respectively. It is a figure to do. In FIG. 4, the same reference numerals are given to the same parts as those in FIG. 1 showing the first embodiment, and the duplicated explanation is omitted. In the present embodiment, as shown in FIG. 4D, the inter-chip connection wiring 10 is drawn obliquely. By configuring in this way, it is possible to further increase the inter-chip connection wiring length as compared with the case where a dent (groove shape) is simply provided. For this reason, the flexibility of the wiring is increased, the stress of the wiring caused by chip folding can be reduced, and the strain can be reduced. In this case, since the number of wirings between chips cannot be increased, the condition is limited to a condition where the number of signal lines between chips is small. As for the manufacturing method, it is possible to manufacture in the same manner as in the first embodiment only by changing the pattern of the interchip connection wiring.
In the second embodiment, the wiring pattern between the chips is skewed to improve the flexibility of the wiring. Instead, the wiring pattern is arranged on the side of the chip as in the first embodiment. By making a plurality of indentations in the lower insulating layer provided in the folded region orthogonal to each other, the inter-chip connection wiring has a concave shape, and the convex portions have a plurality of corrugated shapes, thereby increasing the wiring length and improving the flexibility of the wiring. You may make it raise.

〔第３の実施の形態〕
図５は、本発明の第３の実施の形態を示す断面図である。本実施の形態においては、図５に示されるように、積層された半導体チップは、多層配線基板２４の内部に実装される。この実装構造は次のようにして作製される。基板の表裏面に配線パターンを有する両面配線基板２５が予め作製されている。両面配線基板２５の上に、半導体チップ１、２を収容する開口が開設された中間基板２６を接着する。そして、図３（ｂ）に示すように加工された半導体チップ１、２を両面配線基板２５上に接着剤４を介して接着する。続いて、半導体チップが収容された開口内を封止樹脂７にて充填して半導体チップの樹脂封止を行なう。次に、封止樹脂７の一部を除去して半導体チップ１上の電極パッドを露出させ、中間基板２６の一部を除去して両面配線基板２５上のランドパターンを露出させる。その後、めっき法などを用いて、露出させた電極パッドおよびランドパターンとそれぞれ電気的に接続するビア２７、２８を形成すると共に、封止樹脂７および中間基板２６上に配線を形成する。その上に、プリプレグを積層するなどして樹脂絶縁層２９を形成する。その後、ビアホールの開孔工程、配線形成工程を経て多層配線基板２４が作製される。このように、第３の実施の形態によれば、半導体チップを内蔵した配線基板を製造することができる。前述したように、半導体チップのＳｉ層厚を薄くした場合においても、折り返したときの層構成が対称であるために、チップ反りを抑制することができる。そのため、積層半導体チップを内蔵した配線基板を容易に製造することができる。 [Third Embodiment]
FIG. 5 is a sectional view showing a third embodiment of the present invention. In the present embodiment, as shown in FIG. 5, the stacked semiconductor chips are mounted inside the multilayer wiring board 24. This mounting structure is manufactured as follows. A double-sided wiring board 25 having a wiring pattern on the front and back surfaces of the board is prepared in advance. On the double-sided wiring substrate 25, an intermediate substrate 26 having an opening for accommodating the semiconductor chips 1 and 2 is bonded. Then, the semiconductor chips 1 and 2 processed as shown in FIG. 3B are bonded onto the double-sided wiring board 25 via the adhesive 4. Subsequently, the inside of the opening in which the semiconductor chip is accommodated is filled with the sealing resin 7 to perform resin sealing of the semiconductor chip. Next, part of the sealing resin 7 is removed to expose the electrode pads on the semiconductor chip 1, and part of the intermediate substrate 26 is removed to expose the land pattern on the double-sided wiring board 25. Thereafter, vias 27 and 28 that are electrically connected to the exposed electrode pads and land patterns are formed by using a plating method or the like, and wirings are formed on the sealing resin 7 and the intermediate substrate 26. A resin insulating layer 29 is formed thereon by, for example, laminating a prepreg. Thereafter, the multilayer wiring substrate 24 is manufactured through a via hole opening process and a wiring forming process. Thus, according to the third embodiment, a wiring board having a built-in semiconductor chip can be manufactured. As described above, even when the Si layer thickness of the semiconductor chip is reduced, the warp of the chip can be suppressed because the layer configuration when folded is symmetrical. Therefore, it is possible to easily manufacture a wiring board incorporating a laminated semiconductor chip.

本発明の第１の実施の形態の説明図。Explanatory drawing of the 1st Embodiment of this invention. 本発明の第１の実施の形態の製造方法の前半を示す工程順断面図。Sectional drawing in order of a process which shows the first half of the manufacturing method of the 1st Embodiment of this invention. 本発明の第１の実施の形態の製造方法の後半を示す工程順断面図。Sectional drawing in order of a process which shows the second half of the manufacturing method of the 1st Embodiment of this invention. 本発明の第２の実施の形態の説明図。Explanatory drawing of the 2nd Embodiment of this invention. 本発明の第３の実施の形態の断面図。Sectional drawing of the 3rd Embodiment of this invention. 一般的なＳｉＰの断面図。Sectional drawing of general SiP. 従来技術（特許文献１）の説明図。Explanatory drawing of a prior art (patent document 1). 従来技術（特許文献２）の製造方法を示す工程順断面図。Sectional drawing in order of a process which shows the manufacturing method of a prior art (patent document 2).

符号の説明Explanation of symbols

１、２ 半導体チップ
１ａ ボンディングエリア
３ 基板
４ 接着剤
５ 熱硬化性樹脂
６ ボンディングワイヤ
７ 封止樹脂
８ 電極パッド
９ 外部端子
１０ チップ間接続配線
１１ 補強用ダミー配線
１２ 導電体バンプ
１３ 半導体ウエハ
１４ ダイシングストッパ用ダミー配線
１５ 第一配線層
１６ 第二配線層
１７ 第三絶縁層
１８、２３ フォトレジスト膜
１９ 第三配線層
２０ 第四絶縁層
２１ 第四配線層
２２ 第五絶縁層
２４ 多層配線基板
２５ 両面配線基板
２６ 中間基板
２７、２８ ビア
２９ 樹脂絶縁層 DESCRIPTION OF SYMBOLS 1, 2 Semiconductor chip 1a Bonding area 3 Board | substrate 4 Adhesive 5 Thermosetting resin 6 Bonding wire 7 Sealing resin 8 Electrode pad 9 External terminal 10 Interchip connection wiring 11 Reinforcing dummy wiring 12 Conductor bump 13 Semiconductor wafer 14 Dicing Dummy 15 for stopper 15 First wiring layer 16 Second wiring layer 17 Third insulating layers 18 and 23 Photoresist film 19 Third wiring layer 20 Fourth insulating layer 21 Fourth wiring layer 22 Fifth insulating layer 24 Multilayer wiring board 25 Double-sided wiring board 26 Intermediate board 27, 28 Via 29 Resin insulation layer

Claims (15)

二つの半導体チップがそれぞれの回路形成面同士が対向するように積層され、各半導体チップの最上層の配線同士が導電体バンプを介して接続されると共に、一配線層において各半導体チップの配線パターンの延長部同士が接続されていることを特徴とする半導体装置。 Two semiconductor chips are laminated so that their circuit formation surfaces face each other, and the uppermost wirings of each semiconductor chip are connected to each other through conductor bumps, and the wiring pattern of each semiconductor chip in one wiring layer A semiconductor device characterized in that extensions of the two are connected. 各半導体チップが、前記配線パターン以外の補強用ダミー配線により連結されていることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the semiconductor chips are connected by a reinforcing dummy wiring other than the wiring pattern. 前記補強用ダミー配線が、前記一配線層若しくはそれより上層の配線層において形成されていることを特徴とする請求項２に記載の半導体装置。 The semiconductor device according to claim 2, wherein the reinforcing dummy wiring is formed in the one wiring layer or a wiring layer higher than the one wiring layer. 前記補強用ダミー配線は、前記配線パターンより幅広でかつ半導体チップ間での長さが前記配線パターンのそれより短いことを特徴とする請求項２または３に記載の半導体装置。 4. The semiconductor device according to claim 2, wherein the reinforcing dummy wiring is wider than the wiring pattern and has a length between semiconductor chips shorter than that of the wiring pattern. 前記補強用ダミー配線は、前記配線パターンを挟んでその外側に形成されていることを特徴とする請求項２から４のいずれかに記載の半導体装置。 5. The semiconductor device according to claim 2, wherein the reinforcing dummy wiring is formed outside the wiring pattern. 前記半導体チップ間を接続する前記配線パターンが、前記半導体チップの辺に対し斜行して形成されていることを特徴とする請求項１から５のいずれかに記載の半導体装置。 6. The semiconductor device according to claim 1, wherein the wiring pattern for connecting the semiconductor chips is formed obliquely with respect to a side of the semiconductor chip. 一方の半導体チップ上に形成された電極パッドを露出させるように二つの半導体チップが積層されていることを特徴とする請求項１から６のいずれかに記載の半導体装置。 7. The semiconductor device according to claim 1, wherein two semiconductor chips are stacked so as to expose an electrode pad formed on one semiconductor chip. 前記一方の半導体チップが絶縁基板側となるようにして、積層された半導体チップが前記絶縁基板上に搭載され、半導体チップ上に形成された前記電極パッドと前記絶縁基板上に形成されたパッドとがボンディングワイヤにより接続されており、両半導体チップはボンディングワイヤを含めて前記絶縁基板上にて樹脂封止されていることを特徴とする請求項７に記載の半導体装置。 The stacked semiconductor chips are mounted on the insulating substrate so that the one semiconductor chip is on the insulating substrate side, the electrode pads formed on the semiconductor chip, and the pads formed on the insulating substrate; The semiconductor device according to claim 7, wherein the semiconductor chips are sealed with resin on the insulating substrate including the bonding wires. 前記絶縁基板の半導体チップが搭載されていない側の面には外部接続端子が面状に配置されていることを特徴とする請求項８に記載の半導体装置。 The semiconductor device according to claim 8, wherein external connection terminals are arranged in a planar shape on a surface of the insulating substrate on which the semiconductor chip is not mounted. 積層された半導体チップが多層配線基板内に実装されていることを特徴とする請求項１から６のいずれかに記載の半導体装置。 7. The semiconductor device according to claim 1, wherein the laminated semiconductor chips are mounted in a multilayer wiring board. 一方の半導体チップ上に形成された電極パッドを露出させるように二つの半導体チップが積層されて樹脂封止されており、その封止樹脂に開けられた前記電極パッド上のビアホールを介して当該電極パッドが封止樹脂上に引き出されていることを特徴とする請求項１０に記載の半導体装置。 Two semiconductor chips are laminated and resin-sealed so as to expose the electrode pads formed on one semiconductor chip, and the electrodes are connected via via holes on the electrode pads opened in the sealing resin. The semiconductor device according to claim 10, wherein the pad is drawn on the sealing resin. 二つの半導体チップがその表層配線層が対向するように折り返されて積層されている半導体装置の製造方法であって、
（１）半導体ウエハのチップ形成領域内に回路を作り込む工程と、
（２）前記半導体ウエハ上に複数層の配線層を形成する工程と、
（３）最上層の配線層上にバンプを形成する工程と、
（４）前記半導体ウエハから半導体チップを切り出すと共にペアとなる半導体チップを連結する半導体層を除去する工程と、
（５）ペアとなる半導体チップ同士を積層し両者を接着する工程と、
を有し、前記第（２）の工程における一配線層の形成工程においてはペアとなる半導体チップ同士の配線が接続されるように形成され、前記第（５）の工程においては前記バンプを介して半導体チップの最上層の配線同士が接続されることを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device in which two semiconductor chips are folded and stacked so that their surface wiring layers are opposed to each other,
(1) forming a circuit in a chip formation region of a semiconductor wafer;
(2) forming a plurality of wiring layers on the semiconductor wafer;
(3) forming bumps on the uppermost wiring layer;
(4) cutting a semiconductor chip from the semiconductor wafer and removing a semiconductor layer connecting the paired semiconductor chips;
(5) a step of stacking semiconductor chips to be paired and bonding them together;
And in the step of forming one wiring layer in the step (2), the wirings of the paired semiconductor chips are connected to each other, and in the step (5), the bumps are interposed. A method for manufacturing a semiconductor device, characterized in that the uppermost wirings of the semiconductor chip are connected to each other. 前記一配線層の形成工程に先立って、ペアとなる半導体チップ同士間を接続する配線の形成領域の絶縁膜の少なくとも一部がエッチング除去されることを特徴とする請求項１２に記載の半導体装置の製造方法。 13. The semiconductor device according to claim 12, wherein at least a part of an insulating film in a wiring formation region that connects between paired semiconductor chips is removed by etching prior to the step of forming the one wiring layer. Manufacturing method. 前記絶縁膜の少なくとも一部がエッチング除去される工程は、ビアホール形成工程を兼ねていることを特徴とする請求項１３に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 13, wherein the step of removing at least a part of the insulating film also serves as a via hole forming step. ペアとなる半導体チップ同士間を接続する配線の形成領域において、当該配線の下層にダイシングのストッパとなるダミー配線が形成されることを特徴とする請求項１２から１４のいずれかに記載の半導体装置の製造方法。 15. The semiconductor device according to claim 12, wherein a dummy wiring serving as a dicing stopper is formed in a lower layer of the wiring in a wiring formation region for connecting between the paired semiconductor chips. Manufacturing method.
JP2007139939A 2007-05-28 2007-05-28 Semiconductor device, and manufacturing method thereof Pending JP2008294318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007139939A JP2008294318A (en) 2007-05-28 2007-05-28 Semiconductor device, and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007139939A JP2008294318A (en) 2007-05-28 2007-05-28 Semiconductor device, and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JP2008294318A true JP2008294318A (en) 2008-12-04

Family

ID=40168711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007139939A Pending JP2008294318A (en) 2007-05-28 2007-05-28 Semiconductor device, and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2008294318A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012056661A1 (en) * 2010-10-25 2012-05-03 パナソニック株式会社 Electronic components assembly

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012056661A1 (en) * 2010-10-25 2012-05-03 パナソニック株式会社 Electronic components assembly
US9204530B2 (en) 2010-10-25 2015-12-01 Panasonic Corporation Electronic components assembly

Similar Documents

Publication Publication Date Title
US8766425B2 (en) Semiconductor device
US6960826B2 (en) Multi-chip package and manufacturing method thereof
JP5042591B2 (en) Semiconductor package and stacked semiconductor package
US7550835B2 (en) Chip stack package utilizing a dummy pattern die between stacked chips for reducing package size
JP4808408B2 (en) Multi-chip package, semiconductor device used for the same, and manufacturing method thereof
KR100626618B1 (en) Semiconductor chip stack package and related fabrication method
JP5529371B2 (en) Semiconductor device and manufacturing method thereof
US20030122244A1 (en) Integrated chip package structure using metal substrate and method of manufacturing the same
US20090127682A1 (en) Chip package structure and method of fabricating the same
US20120146216A1 (en) Semiconductor package and fabrication method thereof
US7642632B2 (en) Pad redistribution chip for compactness, method of manufacturing the same, and stacked package using the same
US8860215B2 (en) Semiconductor device and method of manufacturing the same
JP2004172323A (en) Semiconductor package and stacked semiconductor package
US20110031606A1 (en) Packaging substrate having embedded semiconductor chip
US20100140801A1 (en) Device
JP3651346B2 (en) Semiconductor device and manufacturing method thereof
KR20130123747A (en) Package of electronic device with bump buffer spring pad and method for manufacturing the same
WO2014203739A1 (en) Semiconductor device and method for manufacturing same
US20100136747A1 (en) Method for manufacturing semiconductor package
JP2008103725A (en) Flexible film, semiconductor package using the flexible film and method for manufacturing the semiconductor package
US8975745B2 (en) Packaged microelectronic devices recessed in support member cavities, and associated methods
JP2008294318A (en) Semiconductor device, and manufacturing method thereof
KR101673585B1 (en) Package on Package and The fabricating method of the same
US20110006412A1 (en) Semiconductor chip package and method for manufacturing thereof and stack package using the same
KR101068305B1 (en) Stack semiconductor package and manufacturing method therof