JP2008293230A - Data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption while avoiding having any adverse influence on data transfer processing. <P>SOLUTION: This slave device 1 connected to an I2C bus 50 for transferring data with a master device connected to the I2C bus 50 is provided with a state machine control part 2 for receiving an SCL clock on the I2C bus 50, and for controlling a data transfer state; an SDA control part 3 for performing the reception processing of data from a master device and the transmission processing of data to the master device; a buffer part 4 for storing reception data from the master device and transmission data to the master device; and a CLK control part 6 for controlling the presence/absence of the supply of a clock signal to the SDA control part 3 and the buffer part 4 according to the data transfer state. The CLK control part 6 stops the supply of the clock signal to the SDA control part 3 and the buffer part 4 when the data transfer state is such a state that data transfer is not operated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data transfer apparatus used by connecting to an I2C (Inter Integrated Circuit) bus, and more particularly to a data transfer apparatus that operates as a slave device in accordance with control from a master device connected to an I2C bus.

  As a bus format for bidirectional communication between a plurality of devices, a bus format called I2C bus developed by Philips is known. The I2C bus is composed of a simple bidirectional two-wire bus having a clock supply line SCL (serial clock line) and a data transfer line SDA (serial data line). A plurality of devices can be connected to the I2C bus. Among the plurality of devices connected to the I2C bus, a device functioning as a master device supplies a clock to other devices to change the entire data communication state. Control.

  FIG. 4 is a diagram illustrating a configuration example of the I2C bus system. As shown in the figure, a plurality of devices 53 to 56 are connected to the SDA 51 and SCL 52 of the I2C bus 50, and each device is a master state having the authority to control data communication, or a slave state that operates according to the control of the master device. It is set to either state. A unique slave address is set for each device in the slave state. FIG. 4 shows a case where the devices 53, 54 and 56 are in the slave state and the device 55 is in the master state.

  Then, in the above state, the master device 55 transmits the slave address of the slave device to which data is to be transmitted / received and information specifying the data transmission direction (Write or Read) through the SDA 51, whereby the designated slave device And data transfer between the master device 55 and the master device 55 (see, for example, Patent Document 1).

  FIG. 5 is a diagram illustrating state transition of a conventional slave device. When the reset or the data transfer ends, the slave device transitions to the idle state A and waits for a start condition (start condition). Thereafter, when a start condition is detected, the state transits to the start state B, and subsequently, the state transits to the address reception state C.

  When the received slave address is different from the address value assigned to the own device, the slave address is invalidated and the state transits to the idle state A. On the other hand, when both addresses match, the state transits to either the data reception state D or the data transmission state E depending on whether the request is Write or Read. When data reception or data transmission is completed, the state transitions again to the idle state A and waits for the next start condition.

  As described above, when the I2C bus is used, data transfer between a plurality of interconnected devices can be controlled with a simple bus configuration. However, in the I2C bus system, the start condition is synchronized with the SCL clock. Since information, slave addresses, and the like are transmitted, it is necessary to transmit an SCL clock to all devices. For this reason, the SCL clock is supplied not only to the device that performs data transfer, but also to the device that does not perform data transfer or the device that has completed data transfer, increasing the power consumption of the entire system. There was a problem that it was easy.

  Therefore, as described in Patent Document 2, a bus system that controls the SCL clock and the power supply to each device in accordance with the data transfer state has been proposed. This bus system includes stop condition detection means for detecting a stop condition (end condition), switch means for setting the level of the SCL clock to Low level, and power control means for switching ON / OFF of the power supply of the slave device. When the stop condition is detected, the SCL clock is forcibly switched to the low level and the power supply to the slave device is cut off. According to the bus system, since the operation of the slave device is stopped when there is no need for data transfer, unnecessary power consumption can be avoided.

JP 2004-534322 A JP 2004-310401 A

  However, in the bus system described in Patent Document 2, a stop condition is detected in units of I2C bus lines, and the SCL clock level and power ON / OFF are changed, so that not only a specific device but also an I2C bus is connected. There is a problem that it affects all devices that have been used. In particular, in order to resume data transfer after changing the clock level and the power supply state, it is necessary to return the clock to the original state and turn on the power supply again. May cause adverse effects such as failure to perform normal data transfer after recovery.

  In the I2C bus system, there are cases where a plurality of master devices are connected, and data transfer is continuously performed while determining the priority order. In such a state, at the end of data transfer of one master device, If the SCL clock is forcibly set to the Low level, there arises a problem that the data transfer of the next master device cannot be started quickly. That is, forcibly setting the SCL clock to the Low level is an unintended operation from the next master device, so the next master device waits for data transfer until the SCL clock state returns to the original state. Need arises.

  Therefore, the present invention has been made in view of the problems in the above-described conventional technology, and is a data transfer apparatus capable of reducing power consumption while avoiding adverse effects on data transfer processing. The purpose is to provide.

  In order to achieve the above object, the present invention provides a data transfer device connected to an I2C bus and transferring data to and from a master device connected to the I2C bus, and receiving an SCL clock on the I2C bus. A state machine control unit that controls a data transfer state, a data control unit that performs a process of receiving data from the master device and a process of transmitting data to the master device, and sends data to the data control unit according to the data transfer state A clock control unit that controls whether or not a clock signal is supplied, and the clock control unit stops supply of the clock signal to the data control unit when the data transfer state is a state in which data transfer is not performed. It is characterized by doing.

  According to the present invention, when the data transfer is not performed, the supply of the clock signal to the data control unit is stopped, so that the power consumption can be reduced without adversely affecting the data transfer process. Is possible.

  In the data transfer apparatus, the data transfer device further comprises request target determination means for determining whether a request from the master device is intended for the own device, and the clock control unit receives the request from the master device by the request target determination means. When it is determined that the request is not for the device itself, the supply of the clock signal to the data control unit can be stopped. According to this configuration, when the request from the master device targets another device, and the self device does not need to perform data transfer, it is possible to avoid excessive power consumption.

  In the data transfer apparatus, the data transfer device further comprises request end detection means for detecting a stop condition indicating that a request from the master device has ended, and the clock control unit is configured to detect when the stop condition is detected by the request end detection means. The supply of the clock signal to the data control unit can be stopped. According to this configuration, it is possible to avoid excessive power consumption after the request from the master device is completed and the data transfer is completed.

  The data transfer apparatus includes interruption detection means for detecting that data transmission from the master device or data reception at the master device is interrupted, and the clock control unit is connected to the master device by the interruption detection means. When the interruption of the data transfer is detected, the supply of the clock signal to the data control unit can be stopped. According to this configuration, it is possible to avoid consuming excess power during the period from when data transfer is interrupted to when it is restored.

  In the data transfer apparatus, the data control unit stores data received from the master device and data to be transmitted to the master device, receives data from the master device, and sends the received data to the buffer unit. And an SDA control unit that reads data from the buffer unit and sends the data to the master device, so that the clock control unit stops supplying a clock signal to at least one of the buffer unit and the SDA control unit. Can be configured.

  As described above, according to the present invention, it is possible to reduce power consumption while avoiding adverse effects on data transfer processing.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is an overall configuration diagram of a slave device as a data transfer apparatus according to the present invention. The slave device 1 includes a state machine control unit 2, an SDA control unit 3, a buffer unit 4, a function unit 5, And a CLK control unit 6. Similar to the slave devices 53 and 54 shown in FIG. 4, the slave device 1 is connected to the IC2 bus 50 (SDA 51 and SCL 52) together with a master device having a function conforming to the I2C standard.

  The state machine control unit 2 is connected to the I2C bus 50 and performs I2C bus control and transfer start / stop detection based on a signal sent from the master device via the I2C bus 50 and conforms to the I2C bus standard. Generate a sequence of slave devices. As shown in FIG. 1, the state machine control unit 2 includes, for example, an I2C bus control unit 20, a start / stop detection circuit 21, an ACK (acknowledge signal) confirmation unit 22, a data number counter 23, a state machine unit 24, and the like. Is done.

  The I2C bus control unit 20 determines the data fetch timing from the I2C bus 50 and the data transmission timing to the I2C bus 50, and sends an operation timing signal to the subsequent block. The start / stop detection circuit 21 detects a start condition and a stop condition, which are a start condition and an end condition for performing transfer with the I2C bus 50, and sends detection information.

  The ACK confirmation unit 22 monitors an acknowledge signal indicating that data has been received when performing a read operation with the master device. The data number counter 23 counts the number of bits of data to be transferred, and monitors whether or not data having a bit length specified by the I2C standard has been prepared. The state machine unit 24 is connected to the I2C bus control unit 20, the start / stop detection circuit 21, the ACK confirmation unit 22, and the data number counter 23, and generates a slave sequence according to the I2C bus standard.

  The SDA control unit 3 is connected between the state machine control unit 2 and the buffer unit 4, and sends a Read request and a Write request to the buffer unit 4 in accordance with a data transmission and reception command from the upper level. Send and receive. Further, the SDA control unit 3 monitors the slave address transferred via the I2C bus 50 and determines whether the data on the I2C bus 50 is destined for the own device. As shown in FIG. 1, the SDA control unit 3 includes, for example, a serial / parallel (S / P) conversion circuit 31, a slave address generation unit 32, a buffer address generation unit 33, a write data generation unit 34, and a latch timing generation unit. 35, a parallel / serial (P / S) conversion circuit 36, a read data generation unit 37, a read timing generation unit 38, and the like.

  The S / P conversion circuit 31 converts serial data transferred from the I2C bus into parallel data, and sends the converted data to the slave address generation unit 32, the buffer address generation unit 33, and the write data generation unit 34. The slave address generation unit 32 compares the transferred slave address value with the slave address value assigned to the device itself, and if they are different, notifies the CLK control unit 6 to that effect. The buffer address generation unit 33 designates the address space of the buffer unit 4 in which the data at the time of writing is to be written, the write data generation unit 34 sends the data at the time of writing to the buffer unit 4, and the latch timing generation unit 35 The timing for writing the write data to the buffer unit 4 is designated.

  The P / S conversion circuit 36 converts the parallel data read from the buffer unit 4 into serial data in response to a request from the master device, and sends the serial data to the I2C bus control unit 20. The Read data generation unit 37 receives data at the time of Read from the buffer unit 4, and the Read timing generation unit 38 specifies a timing for reading data from the buffer unit 4 when a Read request is generated.

  The buffer unit 4 is for storing data to be transferred. In the case of a write request, the buffer unit 4 stores the data transmitted from the write data generation unit 34 in a designated address space, and in the case of a read request. In this case, data in the designated address space is sent to the Read data generation unit 37.

  The CLK control unit 6 is connected to the start / stop detection circuit 21 and the ACK confirmation unit 22 of the state machine control unit 2, the slave address generation unit 32 of the SDA control unit 3, and the buffer unit 4. Based on the outputs of the ACK confirmation unit 22 and the slave address generation unit 32, the presence / absence of clock supply to the SDA control unit 3 and the buffer unit 4 is controlled.

  Next, the operation of the slave device 1 will be described with reference to FIGS. In the following description, prior to the description of the specific operation of each configuration of the slave device 1, first, the operation of the entire slave device 1 will be schematically described.

  The sequence of the I2C slave operation when the slave device 1 according to the present invention is used includes an idle state A, a start state B, an address reception state C, a data reception state D, and a data transmission state, as shown in FIGS. Transition is made between six states consisting of E and sleep state F. The state transition is controlled by the SCL clock from the master device.

  In this sequence, when reset or power-on reset is performed, the slave device 1 enters the idle state A and waits for data transfer to start. Thereafter, when a start condition (start state) is detected, a transition is made to a start state B, followed by a transition to an address reception state C that receives information indicating a slave address and a data transmission direction (Write or Read).

  If the slave address does not match the address value assigned to the device after receiving the slave address, the state transits to the sleep state F and the clock is stopped. The clock stop will be described later in detail. Thus, when the state transitions to the sleep state F, the state is maintained until the next start condition is detected. When the start condition is detected, the state transitions to the start state B.

  On the other hand, if the received slave address matches the address of the own device, it is determined whether the request is a write request or a read request based on information indicating the data transmission direction. As a result of the determination, if the request is a write request, the state transits to the data reception state D, and thereafter, the data reception state D is maintained while the master device transmits data (while writing). When a start condition is detected, the state transitions to the start state B, and when a stop condition is detected, the state transitions to the sleep state F.

  On the other hand, when the request is a read request, the state transits to the data transmission state E. Even in this case, while the master device requests reception of data (while reading), the data transmission state E is maintained and the start condition is set. When it detects, it changes to the start state B, and when it detects a stop condition, it changes to the sleep state F. In the data transmission state E, the state transits to the sleep state F even when a data reception error occurs.

  Next, specific operations of each component of the slave device 1 will be described.

  When data transfer is started and data is transmitted to the slave device 1 through the I2C bus 50, the I2C bus control unit 20 determines the data capture timing and output timing based on the transmitted data, and indicates them. The timing signal is sent to the ACK confirmation unit 22, the data counter 34, the state machine unit 24, and the SDA control unit 3. At the same time, information indicating the transfer start / stop is sent to the start / stop detection circuit 21, and the start / stop detection circuit 21 determines whether or not the transfer is started.

  When the transfer start information is detected, the start information is sent to the state machine unit 24. The state machine of the state machine unit 24 transitions from the idle state A immediately after the reset to the start state B, and subsequently to the address reception state C. Transition.

  In the I2C sequence, after a start condition, a 7-bit slave address and a 1-bit request determination bit (Write request / Read request) are usually transferred. Therefore, the data to be transmitted is counted up by the data number counter 23, and first, the 7-bit data is converted into parallel data by the S / P conversion circuit 31.

  Thereafter, the slave address generation unit 32 temporarily holds the parallel-converted data, and compares the data with the slave address assigned to the own device. If the addresses do not match as a result of the comparison, it is determined that the request is not for the device itself, and address invalid information is transmitted to the state machine unit 24. When the state machine unit 24 receives the address invalid information, the state machine unit 24 transits from the address reception C state to the sleep F state.

  When the state transits to the sleep state F, the CLK control unit 6 stops supplying the clock to the SDA control unit 3 and the buffer unit 4 and stops the operations of the SDA control unit 3 and the buffer unit 4. At this time, the operation of the state machine control unit 2 is not stopped, and the reception of the SCK clock from the SCL 52 is continued.

  On the other hand, if the received slave address matches the slave address assigned to the own device, this is a request for the own device, so the request determination bit of the eighth bit is referred to and the requested processing is Write. It is determined whether there is a read or a read.

  As a result of the determination, if the request is a write request, the subsequent data is transferred as write data, so the state machine state of the state machine unit 24 transitions to the data reception D state. Then, the transmitted data is counted up by the data number counter 23, and parallel-converted in units of 8 bits in the S / P conversion circuit 31. Thereafter, the converted data is buffered in the buffer unit 4 by the buffer address generation unit 33, the write data generation unit 34, and the latch timing generation unit 35.

  When transmission of the write data from the master device is completed and a stop condition is transmitted, the start / stop detection circuit 21 detects it and transmits information on the completion of transfer to the state machine unit 24. In response to this, the state machine unit 24 transits from the address reception D state to the sleep F state, and stops supplying the clock to the SDA control unit 3 and the buffer unit 4 by the CLK control unit 6 as described above. To do.

  On the other hand, in the case of a Read request, it is necessary to send Read data from the own device, so the state machine unit 24 transitions from the address reception state C to the data transmission state E. Then, 8-bit serial data is sent to the I2C bus 50 through the data number counter 23, the Read data generation unit 37, the Read timing generation unit 38 and the P / S conversion circuit 36.

  Data transmission continues until a stop condition is detected. If a reception error is transmitted from the master device in the middle of the transmission, the ACK confirmation unit 22 detects the reception error, and the state machine unit 24 transmits the address. Transition from state E to sleep state F Similarly to the above, the CLK control unit 6 stops the clock supply to the SDA control unit 3 and the buffer unit 4.

  When transmission of the Raid data is completed without receiving a reception error and a stop condition is transmitted from the master device, the start / stop detection circuit 21 detects it and transmits information on the completion of transfer to the state machine unit 24. Also at this time, the state machine unit 24 transitions from the address reception D state to the sleep F state, and the CLK control unit 6 stops supplying the clock to the SDA control unit 3 and the buffer unit 4.

  As described above, according to the present embodiment, the SDA control is performed when the request is not for the device itself, when a data transfer stop condition is detected, and when a data transfer is interrupted due to a reception error. Since the supply of clocks to the unit 3 and the buffer unit 4 is stopped and their operations are stopped, the power consumption can be reduced. In particular, since the presence or absence of data transfer is determined for each device and the clock supply state is changed only within the device, even if the operation is stopped, it is avoided that all devices connected to the I2C bus are affected. Is possible. At that time, the operation of the entire slave device 1 is not stopped, and only the operations of the SDA control unit 3 and the buffer unit 4 are stopped. be able to.

  Furthermore, in this embodiment, since the level of the SCL clock on the SCL 52 is not changed, data transfer can be performed smoothly when a plurality of master devices are connected to the I2C bus 50 to perform continuous data transfer. It becomes possible.

  In the above embodiment, the supply of clocks to the SDA control unit 3 and the buffer unit 4 is stopped, but it is not always necessary to stop the supply of clocks to both the SDA control unit 3 and the buffer unit 4. The supply of the clock to either one of them may be stopped.

  In the above embodiment, in the case of a Read request, it is determined whether or not a data reception error has occurred on the master device side, and the clock supply is stopped when a reception error occurs. Alternatively, it may be determined whether a data transmission error has occurred on the master device side, and the clock supply may be stopped when a transmission error occurs.

1 is an overall configuration diagram of a slave device as a data transfer apparatus according to the present invention. It is a figure which shows the state transition of the slave device of FIG. It is a figure for demonstrating operation | movement of the slave device of FIG. It is a figure which shows the structural example of an I2C bus system. It is a figure which shows the state transition of the conventional slave device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Slave device 2 State machine control part 3 SDA control part 4 Buffer part 5 Function part 6 CLK control part 20 I2C bus control part 21 Start stop detection circuit 22 ACK confirmation part 23 Data number counter 24 State machine part 31 S / P conversion circuit 32 Slave address generation unit 33 Buffer address generation unit 34 Write data generation unit 35 Latch timing generation unit 36 P / S conversion circuit 37 Read data generation unit 38 Read timing generation unit 50 I2C bus 51 SDA
52 SCL
53, 54 Slave device 55 Master device 56 Master / slave device

Claims (5)

A data transfer device connected to an I2C bus and transferring data to and from a master device connected to the I2C bus,
A state machine control unit that receives the SCL clock on the I2C bus and controls a data transfer state;
A data control unit that performs data reception processing from the master device and data transmission processing to the master device;
A clock control unit that controls whether or not a clock signal is supplied to the data control unit according to the data transfer state;
The data transfer apparatus according to claim 1, wherein the clock control unit stops supply of a clock signal to the data control unit when the data transfer state is a state in which data transfer is not performed. Comprising a request target determining means for determining whether the request from the master device is intended for the own device;
The clock control unit stops supply of a clock signal to the data control unit when the request target determination unit determines that the request from the master device is not intended for the device itself. The data transfer device according to claim 1. Request end detection means for detecting a stop condition indicating that the request from the master device has ended,
3. The data transfer according to claim 1, wherein the clock control unit stops the supply of a clock signal to the data control unit when the stop condition is detected by the request end detection unit. apparatus. Comprising interruption detection means for detecting that data transmission from the master device or data reception at the master device is interrupted,
The clock control unit stops supply of a clock signal to the data control unit when the interruption detection unit detects interruption of data transfer with the master device. 2. The data transfer device according to 2 or 3. The data control unit stores data received from the master device and data to be transmitted to the master device; receives data from the master device; sends the received data to the buffer unit; and the buffer unit An SDA control unit that reads data from the master device and sends the data to the master device,
5. The data transfer device according to claim 1, wherein the clock control unit stops supply of a clock signal to at least one of the buffer unit and the SDA control unit.

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