JP2008278151A - Ts signal transmission delay time adjusting device, its operation method and terrestrial digital broadcast transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform inter-system delay adjustment without interrupting TS signals even during a normal operation, to make the quick restoration of an SFN network possible and to improve maintainability. <P>SOLUTION: The TS signal transmission delay time adjusting device 10 adjusts a transmission delay time of the TS signals by inputting transmitted TS signals together with clock signals and delaying and outputting the TS signals in synchronism with the clock signals. A memory 11 for delay adjustment writes TS data forming inputted TS signals in synchronism with a data write clock, and reads the TS data in synchronism with a data read clock. A PLL circuit 12 generates a data write clock in synchronism with inputted clock signals, and a PLL circuit 13 generates a data read clock of a variably set frequency in synchronism with the data write clock. A control circuit 14 variably sets the frequency of the data read clock corresponding to the transmission delay time of the TS signals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a TS signal transmission delay time adjusting device that adjusts the transmission time of a TS signal, an operation method thereof, and a terrestrial digital broadcast transmission system.

  In the terrestrial digital broadcasting system, it is possible to construct an SFN network (Single Frequency Network) that can be received without interference on the receiving side even when broadcasting is performed from a plurality of transmitting stations at the same frequency. SFN is effective for effective use of tight radio wave resources. In order to perform SFN, it is necessary that the reception timing of radio waves from each transmitting station is within a certain range (within a guard interval). For this reason, a terrestrial digital broadcast transmission system usually requires a device or a circuit for adjusting the delay time. A block diagram of a general digital terrestrial broadcasting transmission system is shown in FIGS.

  FIG. 3 is a block diagram of a digital terrestrial broadcast transmission system when performing SFN using a plurality of microwave (wireless) lines. This terrestrial digital broadcast transmission system includes a broadcasting station head office (studio) system 110 placed at the broadcasting station head office shown in FIG. 3A and a plurality of transmitting stations shown in FIG. 1 and 2).

  In the broadcasting station head office system 110 shown in FIG. 3A, a plurality of TS signals constituting broadcast TS (Transport Stream) data are multiplexed by a digital terrestrial broadcasting studio Re-MUX (remultiplexing) device 111. . The multiplexed TS signal is digitally modulated by a 64QAM (Quadrature Amplitude Modulation) modulator 112 together with a reference clock signal, and converted into an IF (Intermediate Frequency) signal. Further, the IF signal is converted into an RF (Radio Frequency) signal by the transmission converter 113, and the RF signal is transmitted via the microwave line via the transmission antenna 114.

  In the transmitting station system 120 shown in FIG. 3B, when an RF signal transmitted via a microwave line is received by the receiving antenna 121 for each transmitting station, the RF signal is converted into an IF signal by the receiving converter 122. Converted. The IF signal is digitally demodulated by the 64QAM demodulator 123 and converted into a TS signal and a clock signal. Then, the delay time is adjusted according to the clock signal by the delay adjusting device 124 for the converted TS signal. The delay-adjusted TS signal is transmitted to the SFN reception area by the digital television transmitter 125 via the transmission antenna 126.

  FIG. 4 is a block diagram of a terrestrial digital broadcast transmission system when performing SFN using a plurality of optical lines. The terrestrial digital broadcast transmission system shown in the figure includes a broadcast station head office (studio) system 210 placed at the broadcast station head office shown in FIG. 4A and a plurality of transmission stations shown in FIG. 4B (examples in the figure). Has a transmitting station system 220 placed at the transmitting station 1, 2).

  In the broadcasting station head office system 210 shown in FIG. 4A, a plurality of TS signals constituting the broadcasting TS data are multiplexed by the terrestrial digital broadcasting studio Re-MUX device 211. The multiplexed TS signal is converted into an IF signal by a 64QAM modulator 212 provided in parallel for each of a plurality of optical lines (optical lines 1 and 2 in the example in the figure) together with a reference clock signal. The IF signal is converted from an electrical signal to an optical signal by an E / O (Electrical / Optical) converter (optical terminal) 213, and the optical signal is transmitted for each optical line.

  In the transmitting station system 220 shown in FIG. 4B, an optical signal transmitted via an optical line for each transmitting station is transmitted by an O / E (Optical / Electrical) converter (optical terminal station) 211. An electrical signal is converted into an IF signal. The IF signal is converted into a TS signal and a clock signal by the 64QAM demodulator 222. Then, the delay time is adjusted according to the clock signal by the delay adjusting device 223 for the converted TS signal. The delay-adjusted TS signal is transmitted to the SFN reception area by the digital television transmitter 224 via the transmission antenna 225.

  3 and 4, broadcast TS (Transport Stream) data sent to the transmitting station is set for each transmitting station by the delay adjusting devices 124 and 223 before being input to the digital television transmitters 125 and 224. Time is given. In terrestrial digital broadcasting, since the entire system needs to operate in synchronization with the same clock, not only the TS signal but also the clock signal is transmitted.

  FIG. 5 is a block diagram showing the internal configuration of the delay adjusting device used in the above-mentioned terrestrial digital broadcast transmission system.

  A delay adjustment device 300 shown in FIG. 5 includes a delay time adjustment memory (hereinafter, “delay memory”) 301 and a PLL (Phase Locked) that generates a TS signal processing clock (data write / read clock) from an input clock signal. Loop) circuit 302.

  The PLL circuit 302 includes a phase comparator, a loop filter, and a voltage controlled oscillator (VCO). The phase comparator detects a phase difference between the input clock signal serving as a reference signal and the VCO output serving as the comparison signal (or an output obtained by dividing the VCO output by a frequency divider). The VCO is feedback controlled so that its phase difference is constant, and its oscillation frequency is adjusted. As a result, the PLL circuit 302 generates a VCO output synchronized with the clock signal, that is, a TS signal processing clock, and supplies it to the delay memory 301.

  The delay memory 301 writes the input TS data at a timing synchronized with the TS signal processing clock from the PLL circuit 302, that is, the data write / read clock. The delay memory 301 reads the written TS data at a timing synchronized with the data write / read clock from the PLL circuit 302.

  FIG. 6 is a diagram for explaining a delay operation of the delay adjustment device 300 shown in FIG. In the example of FIG. 6, since 5-byte TS data is stored in the delay memory 301 and read out, the delay circuit has a delay time of 5 clocks. As shown in the figure, input TS data (DATA 1 to 15) is written for each byte of data in the delay memory 301 in synchronization with a data write / read clock from the PLL circuit 302.

  In the example of FIG. 6, according to the timing synchronized with the data write / read clock, TS data (DATA 1 to 5) of 5 bytes from the top is sequentially written. Next, the 5-byte TS data (DATA 1 to 5) written in the delay memory 301 is sequentially read from the next data write / read clock. The next TS data (DATA 6 to 10) is sequentially written in the delay memory 301. As a result, the TS data written in the delay memory 301 is read at a data read timing delayed by 5 clocks from the data write timing.

  Here, when constructing an SFN network using a plurality of transmission systems and transmitters, it is necessary to strictly manage the transmission timing from each transmitting station. For this reason, if a transmission delay time variation of the transmission path, which is a reason for line abnormality or path switching, occurs during the system operation, it is necessary to adjust the TS signal transmission delay time between a plurality of transmission systems again. .

  FIG. 7 explains the operation at the time of delay adjustment of the delay adjustment device 300 shown in FIG. 5 in such a case. In the example of FIG. 7, when the TS signal transmission delay time is reduced, for example, a case where the clock signal is changed from 5 clocks (see FIG. 6) to 4 clocks will be described. In this case, one byte of TS data (DATA4) in the middle of the five bytes of TS data (DATA1 to 5) written in the delay memory 301 in synchronization with the data write / read clock is discarded, and the remaining 4 Read byte TS data (DATA 1 to 3 and 5). Thereby, the transmission delay time is changed.

  On the other hand, when the TS signal transmission delay time is increased, for example, when changing from 5 clocks to 6 clocks, 5 bytes of TS data (DATA 1 to 5) written in the delay memory 301 is 1 byte in the middle. Read with waiting time corresponding to TS data read time. Thereby, the TS signal transmission delay time is changed.

In relation to the delay time adjustment as described above, Patent Document 1 discloses an OFDM signal delay in which an OFDM (Orthogonal Frequency Division Multiplex) signal is delayed by an arbitrary time to eliminate a time difference between a plurality of transmitting stations. An apparatus is described. The delay device includes an A / D converter that receives an OFDM signal and converts the signal into a digital signal, a memory device that stores the digital signal in a memory area according to a predetermined time given from the outside, and reads the digital signal again. And a D / A converter that converts the digital signal into an analog signal.
JP 2000-269927 A

  In the TS signal transmission delay time adjustment method as described above, if there is a transmission delay time fluctuation in the transmission line due to line abnormality or path switching during operation, TS signal transmission between multiple transmission systems is performed again. It is necessary to adjust the delay time. For this reason, it is necessary to abandon the data in the delay memory of the delay adjustment device or to include a read waiting time.

  In either case, since the TS data read from the delay memory output is discontinuous, the reception area covered by the transmitting station that performs the delay time correction cannot temporarily receive, that is, the received image has block noise or the like. There is a problem of appearing. For this reason, it is necessary to adjust the delay when the delay time is shifted while the broadcast is suspended. In this case, since the timing of radio waves received from each transmitting station remains shifted, there is a possibility that broadcasts cannot be received in the SFN reception area until delay adjustment is performed. The reason is that the same and fixed frequency clock is used for writing and reading data to the delay memory of the delay adjusting device.

  As described above, when the transmission delay time is adjusted due to the occurrence of a transmission path or a line failure, data reading is skipped (when the delay time is shortened) and waiting for reading (when the delay is increased). For this reason, TS data is interrupted, causing a temporary reception failure, and there arises a problem that it is difficult to perform delay adjustment during broadcasting.

  An object of the present invention is to enable delay adjustment between systems without interrupting TS signals even during normal operation, and to enable quick restoration of the SFN network and improve maintainability so that TS signal transmission delay can be achieved. It is an object of the present invention to provide a time adjustment device, an operation method thereof, and a terrestrial digital broadcast transmission system.

  In order to achieve the above object, a TS signal transmission delay time adjusting device according to the present invention inputs a transmitted TS signal together with a clock signal, and delays and outputs the TS signal in synchronization with the clock signal. Is a device for adjusting the transmission delay time of a TS signal by the delay, wherein the TS data constituting the input TS signal is written in synchronization with the data write clock and the written TS data is read in synchronization with the data read clock A time adjustment memory; first clock generation means for generating the data write clock in synchronization with the input clock signal; and reading the data at a frequency that is variably set in synchronization with the data write clock. Second clock generation means for generating a clock, and the transmission delay time of the TS signal according to the transmission delay time. The frequency of the data reading clock generated by the second clock generating means and having a control means for variably setting.

  In the present invention, when the transmission delay time of the TS signal is a predetermined time, the control means sets the frequency of the data read clock to be the same as the frequency of the data write clock, and sets the transmission delay time of the TS signal to the predetermined time. When the time is smaller than the time, the frequency of the data read clock may be variably set to be higher than the frequency of the data write clock. The control means may variably set the frequency of the data read clock to be lower than the frequency of the data write clock when the transmission delay time of the TS signal is made longer than the predetermined time. The first clock generation means is composed of a first PLL circuit, and the second clock generation means is a second PLL that variably sets the frequency of the data read clock according to a given frequency setting value. It may be configured by a circuit.

  The operation method of the TS signal transmission delay time adjusting device according to the present invention is such that the transmitted TS signal is input together with the clock signal, and the TS signal is delayed and output in synchronization with the clock signal, thereby transmitting the TS signal. An operation method of an apparatus for adjusting a delay time, wherein a data write clock is generated in synchronization with an input clock signal, a data read clock having a variably set frequency is generated in synchronization with the data write clock. The TS data that is generated and input is written in the delay time adjusting memory in synchronization with the data write clock, and the TS data written in the delay time adjusting memory is synchronized with the data read clock. The frequency of the data read clock is set according to the transmission delay time of the TS signal. And having to varying settings.

  In the present invention, when the transmission delay time of the TS signal is a predetermined time, the frequency of the data read clock is the same as the frequency of the data write clock, and the transmission delay time of the TS signal is made smaller than the predetermined time. In this case, the frequency of the data read clock may be variably set to be higher than the frequency of the data write clock. When the transmission delay time of the TS signal is made longer than the predetermined time, the frequency of the data read clock may be variably set to be lower than the frequency of the data write clock.

  A terrestrial digital broadcast transmission system according to the present invention includes the TS signal transmission delay time adjusting device described above.

  According to the present invention, it is possible to adjust the delay between systems without interrupting the TS signal even during normal operation, and it is possible to quickly restore the SFN network and improve the maintainability. It is possible to provide a time adjustment apparatus, an operation method thereof, and a terrestrial digital broadcast transmission system.

  Hereinafter, a TS signal transmission delay time adjustment device, an operation method thereof, and a terrestrial digital broadcast transmission system according to an embodiment of the present invention will be described in detail with reference to the drawings.

  Referring to FIG. 1, a TS signal transmission delay time adjustment device (hereinafter referred to as “delay adjustment device”) 10 according to the present embodiment is applied to a terrestrial digital broadcast transmission system. For example, when used in the transmitting station system 120 of the digital terrestrial broadcasting transmission system using the microwave line shown in FIG. Further, when used in the transmitting station system 220 of the terrestrial digital broadcast transmission system using the optical line shown in FIG. Other configurations are the same as those in FIG. 3 and FIG.

  The delay adjustment circuit 10 of this embodiment shown in FIG. 1 inputs the transmitted TS signal together with the clock signal, delays the TS signal in synchronization with the clock signal, and outputs the delayed TS signal, thereby reducing the transmission delay time of the TS signal. adjust. Specifically, a delay time adjustment memory (hereinafter referred to as “delay memory”) 11 and a PLL circuit 12 that generates a TS signal processing clock (hereinafter referred to as data write clock) having a predetermined frequency in synchronization with the input clock signal. And have.

  In addition to this configuration, the delay adjustment circuit 10 of this embodiment is a frequency setting function that is a variable frequency PLL that generates a data read clock having a predetermined frequency that is variably set in synchronization with the TS signal processing clock from the PLL circuit 12. The PLL circuit 13 has a frequency setting control circuit 14 that sets a frequency for the PLL circuit 13.

  The delay memory 11 writes the TS data forming the TS signal input to the delay adjustment circuit 10 at a timing synchronized with the data write clock from the PLL circuit 12. The delay memory 11 reads the written TS data at a timing synchronized with a data read clock from the PLL circuit 13 and outputs the read TS data from the delay adjustment circuit 10.

  The PLL circuit 12 includes a phase comparator, a loop filter (low-pass filter), and a voltage controlled oscillator (VCO). The phase comparator detects a phase difference between the input clock signal serving as the reference signal and the VCO output serving as the comparison signal (or the VCO output divided by the frequency divider). The oscillation frequency of the VCO is adjusted by feedback control so that the phase difference is constant. As a result, the PLL circuit 12 generates a VCO output of a predetermined frequency synchronized with the clock signal, that is, a data write clock, and supplies the data write clock to the delay memory 11 and the PLL circuit 13. The PLL circuit 12 corresponds to the first clock generation means and the first PLL circuit of the present invention.

  In addition to the phase comparator, the loop filter (low-pass filter), and the voltage controlled oscillator (VCO), the PLL circuit 13 generates a VCO output as a comparison signal of the phase comparator according to the frequency setting value of the control circuit 14 in this embodiment. And a variable frequency divider (programmable frequency divider) that divides the frequency by the variable frequency dividing number (integer value). The phase comparator detects the phase difference between the data write clock, which is the reference signal input from the PLL circuit 12, and the VCO output, which is the comparison signal, divided by the variable frequency divider. The oscillation frequency of the VCO is adjusted by feedback control so that the phase difference is constant. As a result, the PLL circuit 13 generates a VCO output having a variably set frequency, that is, a data read clock, in synchronization with the data write clock, and supplies the data read clock to the delay memory 11. The PLL circuit 13 corresponds to the second clock generation means and the second PLL circuit of the present invention.

  The control circuit 14 has a function of variably setting the frequency of the data read clock serving as the VCO output of the PLL circuit 13 by, for example, variably setting the frequency division number of the variable frequency divider in the PLL circuit 13. The control circuit 14 corresponds to the control means of the present invention.

  Next, the operation of this embodiment will be described with reference to FIG.

  First, in the terrestrial digital broadcast transmission system, a TS signal is transmitted together with a clock signal from the broadcasting station head office system to each transmitting station (see above). The transmitted TS signal data is input to the delay adjustment circuit 10 in the transmitting station system, and the TS input (TS data) is sequentially written in the delay memory 11. At this time, the TS data write operation in the delay memory 11 is performed in synchronization with a data write clock having a predetermined frequency generated by the PLL circuit 12 in synchronization with the clock signal.

  The TS data written in the delay memory 11 in this way is read with a delay of the transmission delay time of the TS signal set for each transmitting station, is output from the delay adjustment circuit 10, and becomes a TS output. At this time, the TS data read operation from the delay memory 11 is performed in synchronization with the data read clock generated by the PLL circuit 13 in synchronization with the data write clock. In this case, the frequency of the data read clock from the PLL circuit 13 is the same as the frequency of the data write clock from the PLL circuit 12. In the example of FIG. 2, the delay adjustment circuit 10 accumulates and reads 5 bytes of data in the delay memory 11, and thus is a delay circuit with a transmission delay time of 5 clocks (predetermined time).

  Here, during operation of the digital terrestrial broadcasting transmission system, transmission delay time fluctuations of the transmission line occur due to line abnormalities, path switching, etc., and transmission delay times between multiple transmission systems are again measured at each transmitting station. A case of adjustment will be described.

  First, in the delay adjustment operation, a case where the TS signal transmission delay time of the delay adjustment circuit 10 is made smaller than a predetermined time (5 clocks), for example, a case of changing from 5 clocks to 4 clocks will be considered. In this case, the frequency setting of the control circuit 14 temporarily increases the frequency of the data read clock from the PLL circuit 13 to be higher than the frequency of the data write clock, as shown in FIG. That is, the data reading speed is made faster than the data writing speed to the delay memory 11. As a result, since the number of data stored in the delay memory 11 decreases, when the data in the delay memory 11 becomes 4 bytes, the frequency of the data read clock is changed to the original frequency, that is, the frequency of the data write clock. return. Thereby, the delay adjustment operation is terminated. Therefore, in this case, since it is not necessary to discard (read) the data in the delay memory 11, the TS signal transmission delay time can be changed without interrupting the TS signal.

  On the other hand, when the TS signal transmission delay time of the delay adjustment circuit 10 is made longer than a predetermined time (5 clocks), for example, a case of changing from 5 clocks to 6 clocks is considered. In this case, the frequency of the data read clock from the PLL circuit 13 is temporarily lowered so as to be lower than the frequency of the data write clock by setting the frequency of the control circuit 14. That is, the data reading speed is made slower than the data writing speed to the delay memory 11. As a result, since the number of data stored in the delay memory 11 increases, when the data in the delay memory 11 becomes 6 bytes, the frequency of the data read clock is changed to the original frequency, that is, the frequency of the data write clock. return. Thereby, the delay adjustment operation is terminated. Therefore, in this case, since it is not necessary to put a read waiting time, the TS signal transmission delay time can be changed without interrupting the TS signal.

  As described above, in this embodiment, in addition to the clock generation PLL circuit 12 used for writing TS data to the delay memory 11, the clock generation PLL used for reading TS data from the delay memory 11. It has the circuit 13 independently. That is, a PLL circuit 13 that is a variable frequency PLL is prepared for delay time adjustment, and its output is used as a data read clock from the delay memory 11. Thus, when the transmission delay time of the TS signal is reduced, the frequency of the data read clock from the delay memory 11 is temporarily increased, and when the transmission delay time of the TS signal is increased, the data read clock Set the frequency temporarily low. Then, when the adjustment is completed to the target TS signal transmission delay time, the frequency of the data read clock is made the same as the original frequency, that is, the frequency of the data write clock. In this way, the delay adjustment operation is completed.

  Therefore, according to the present embodiment, when adjusting the TS signal transmission delay time, the frequency of the data read clock is varied according to the input / output delay time of the TS signal. By doing this, it is not necessary to discard the TS data in the delay memory 11 or to put a read waiting time, so that the transmission delay time can be changed without interrupting the TS signal. As described above, since the TS signal is not interrupted even when the transmission delay time is adjusted, the delay time can be automatically adjusted during operation (broadcasting) even when the line delay fluctuates due to a line abnormality or the like. For this reason, the SFN network can be quickly restored.

  As mentioned above, although the Example of this invention was described in detail, this invention is not limited to the above-mentioned Example illustrated typically, and those skilled in the art will be based on description content of a claim. The present invention can be modified and changed into various modes without departing from the gist of the present invention. These modified examples and modified examples also belong to the scope of the right of the present invention.

  The present invention can be applied to the use of a delay adjusting device in a transmitting station system arranged at each transmitting station of a digital terrestrial broadcasting transmission system.

It is a block diagram which shows the structure of the TS signal transmission delay time adjustment apparatus which concerns on the Example of this invention. It is a figure explaining the delay adjustment operation | movement of the TS signal transmission delay time adjustment apparatus which concerns on the Example of this invention. (A) And (b) is a block diagram which shows an example of the terrestrial digital broadcast transmission system using a microwave line. (A) And (b) is a block diagram which shows an example of the terrestrial digital broadcast transmission system using an optical line. It is a block diagram which shows the internal structure of the delay adjustment apparatus used with a terrestrial digital broadcast transmission system. FIG. 6 is a diagram illustrating a delay operation of the delay adjustment device illustrated in FIG. 5. It is a figure explaining the operation | movement at the time of the delay adjustment of the delay adjustment apparatus shown in FIG.

Explanation of symbols

10 Delay adjustment device (TS signal transmission delay time adjustment device)
11 Delay time adjustment memory (delay memory)
12 PLL circuit (first clock generation means, first PLL circuit)
13 PLL circuit with frequency setting function (second clock generation means, second PLL circuit)
14 Frequency setting control circuit (control means)
110 broadcasting station head office (studio) system 111 Re-MUX device 112 64QAM modulator 113 transmitting converter 114 transmitting antenna 120 transmitting station system 121 receiving antenna 122 receiving converter 123 64QAM demodulator 124 delay adjusting device 125 digital television transmitter 126 transmitting Antenna 210 Broadcasting Station Head Office (Studio) System 211 Re-MUX Device 212 64QAM Modulator 213 E / O Converter (Optical Terminal)
220 Transmitting station system 221 O / E converter (optical terminal)
222 64QAM demodulator 223 delay adjustment device 224 digital television transmitter 225 transmission antenna 300 delay adjustment device 301 delay time adjustment memory 302 PLL circuit

Claims (8)

An apparatus for adjusting a transmission delay time of a TS signal by inputting the transmitted TS signal together with a clock signal and delaying and outputting the TS signal in synchronization with the clock signal,
A delay time adjusting memory for reading TS data constituting the input TS signal in synchronization with a data write clock and reading out the written TS data in synchronization with a data read clock;
First clock generation means for generating the data write clock in synchronization with the input clock signal;
Second clock generation means for generating the data read clock having a variably set frequency in synchronization with the data write clock;
A TS signal transmission delay time adjusting device, comprising: control means for variably setting the frequency of the data read clock generated by the second clock generation means in accordance with the transmission delay time of the TS signal.   When the transmission delay time of the TS signal is a predetermined time, the control means sets the frequency of the data read clock to be the same as the frequency of the data write clock, and makes the transmission delay time of the TS signal smaller than the predetermined time. 2. The TS signal transmission delay time adjusting device according to claim 1, wherein the frequency of the data read clock is variably set so as to be higher than the frequency of the data write clock.   The control means variably sets the frequency of the data read clock to be lower than the frequency of the data write clock when the transmission delay time of the TS signal is longer than the predetermined time. Item 3. The TS signal transmission delay time adjustment device according to Item 2. The first clock generation means includes a first PLL circuit,
4. The method according to claim 1, wherein the second clock generation means includes a second PLL circuit that variably sets the frequency of the data read clock according to a given frequency setting value. 2. The TS signal transmission delay time adjusting device according to item 1. An operation method of an apparatus for adjusting a transmission delay time of a TS signal by inputting the transmitted TS signal together with a clock signal and delaying and outputting the TS signal in synchronization with the clock signal,
A data write clock is generated in synchronization with the input clock signal,
Synchronize with the data write clock and generate a data read clock with a variably set frequency,
The TS data constituting the input TS signal is written in the delay time adjustment memory in synchronization with the data write clock, and the TS data written in the delay time adjustment memory is read in synchronization with the data read clock,
A method for operating a TS signal transmission delay time adjusting apparatus, comprising: variably setting a frequency of the data read clock according to a transmission delay time of the TS signal.   When the transmission delay time of the TS signal is a predetermined time, the frequency of the data read clock is the same as the frequency of the data write clock, and when the transmission delay time of the TS signal is smaller than the predetermined time, the data 6. The operation method of the TS signal transmission delay time adjusting device according to claim 5, wherein the frequency of the read clock is variably set so as to be higher than the frequency of the data write clock.   7. The data read clock frequency is variably set so as to be lower than the frequency of the data write clock when the transmission delay time of the TS signal is made longer than the predetermined time. Operation method of TS signal transmission delay time adjusting device.   A terrestrial digital broadcast transmission system comprising the TS signal transmission delay time adjusting device according to any one of claims 1 to 4.

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