JP2008278012A - Bitstream replacing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bitstream replacing device capable of performing smooth replacement free of a screen shock in video reproduction when a bitstream is replaced. <P>SOLUTION: Bitstreams of at least two systems are input, and alternated and output to replace the bitstream of the first system with the bitstream of the second system. A code sequence thinning-out means thins out a code sequence for the bitstream of the second system according to thinning-out control information. A code sequence delay means selectively delay the transmission timing of a prescribed code sequence in the bitstream for the output of the code sequence thinning-out means according to delay control information. For example, a main video bitstream of a digital broadcast is replaced with a CM video bitstream. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a bit stream replacement device that replaces a part of a bit stream obtained by encoding a video signal with a bit stream obtained by encoding another video signal.

  In recent years, digitizing techniques for high-definition television signals such as BS, CS, and terrestrial digital broadcasting have been put into practical use. In this digital broadcasting, it is indispensable to perform signal processing such as switching, synchronization, and multiplexing of bitstreams encoded by the encoding method standardized by MPEG2 (Moving Picture Coding Experts Group 2). Several techniques have been proposed for this purpose.

  For example, the conventionally proposed bitstream switching system allows smooth switching without causing screen shock by matching the phase of each GOP (Group Of Picture) in advance when switching two bitstreams. (See Patent Document 1).

In another prior art, it has been proposed to thin out picture frames in order to adjust the buffer amount when switching two bit streams, thereby preventing interruption of a reproduced image at the time of switching (Patent Document). 2).
Japanese Patent Laid-Open No. 2001-145022 JP 2001-285868 A

  However, in the bit stream switching system in Patent Document 1, it has been proposed that the phases of the GOPs be matched in advance when switching between the two systems of bit streams as described above. In order to realize smooth switching that does not occur, not only the phase of GOP is matched, but also reproduction output time management information called PTS (Presentation Time Stamp) included in the stream and decoding called DTS (Decoding Time Stamp) The time management information must also be sequentially continuous before and after switching. When two bitstreams are encoded by the same encoder, it is possible to switch to a relatively smooth state by simply matching the GOP phase. However, when different encoders are used, the playback time can be adjusted even if the GOP phases are matched. There are cases where inconsistencies occur, such as back and forth, and in reality there is a problem that smooth switching is difficult.

  In Patent Document 2, as described above, when switching between two bit streams, it is proposed to thin out picture frames in order to adjust the buffer amount. However, in order to perform thinning, resolution in the time direction during that period is proposed. There is a problem that goes down.

  The present invention has been made in order to solve the conventional problems, and its purpose is to reproduce a video when a part of a bit stream obtained by encoding a video signal is replaced with a bit stream obtained by encoding another video signal. It is an object of the present invention to provide a bitstream replacement device that can suppress the occurrence of screen shock as much as possible and ensure the resolution in the time direction and can perform practically smooth switching.

  The bit stream replacement device of the present invention receives at least two types of bit streams and selectively outputs one of them by switching one of the two types of bit streams, thereby converting the first type of bit stream into the second type of bit stream. A code sequence decimation unit that performs decimation of a code string in accordance with decimation control information with respect to the bit stream of the second system, and delay control for an output of the code sequence decimation unit Code string delay means for selectively delaying the transmission timing of a predetermined code string in the bit stream according to the information.

  With this configuration, smooth image switching can be realized as described below. That is, when switching between the first system bit stream and the second system bit stream is simply performed in units of GOPs, the rear end frame of the first system bit stream and the second system bit stream The front end frames of the two systems of bit streams overlap in time. Even in such a case, at the front end of the second system bit stream, the code stream unnecessary for video reproduction of the second system bit stream is discarded on the bit stream by thinning-out processing, The position in the time axis direction on the bit stream of the code string that has not been thinned out is delayed. As a result, the rear end frame of the first system bit stream and the front end frame of the second system bit stream are prevented from overlapping in time, and resolution degradation in the time axis direction due to thinning is also avoided. Thus, smooth image switching can be realized.

  Further, the bit stream switching device of the present invention generates the thinning control information and the delay control information according to the replacement timing information of the bit stream, and sends them to the code string thinning means and the code string delay means, respectively. A replacement control unit for supplying, and the replacement control unit thins out a code string of a frame by inter-frame bi-directional predictive coding at a front end portion of the bit stream of the second system as the thinning-out control information. Control information is supplied, and as the delay control information, control information for delaying a code string of a frame by intraframe encoding at the front end portion of the bit stream of the second system is supplied.

  With this configuration, in the front end frame of the second system bit stream, the frame by the inter-frame bidirectional encoding which is not necessary for the video reproduction of the second system bit stream is discarded on the bit stream, and the frame The position in the time axis direction on the bit stream of the frame by the inner coding is delayed. It is preferable that the frame by intra-frame coding is delayed before the frame by the immediately subsequent inter-frame forward predictive coding. Thereby, it is possible to avoid the temporally overlapping of the rear end frame of the first system bit stream and the front end frame of the second system bit stream, thereby realizing smooth image switching.

  In the bit stream replacement device of the present invention, the first system bit stream is a main video bit stream, and the second system bit stream is a CM video bit stream. With this configuration, smooth image switching from the main video to the CM video can be realized.

  Further, the bit stream replacement device of the present invention comprises a bit stream switching means provided at the subsequent stage of the code string delay means, and a PCR processing unit provided at the subsequent stage of the bit stream switching means, and the PCR The processing unit adds the PCR packet during a period when the code string thinning unit thins out and becomes blank. With this configuration, a bit stream that complies with the arrival interval of PCR packets in the MPEG standard can be provided.

  Further, the bit stream replacement device of the present invention comprises a bit stream switching means provided at the subsequent stage of the code string delay means, and a PCR processing unit provided at the subsequent stage of the bit stream switching means, and the PCR The processing unit is configured so that a PCR value of a rear end frame of the second stream of bit streams and a PCR value of a front end frame of the first stream of bit streams subsequent thereto are continuous values. The PCR value after the front end frame of the bit stream of one system is rewritten.

  With this configuration, if there is a large difference between the PCR value of the rearmost frame of the second system bitstream and the PCR value of the frontmost frame of the first system bitstream that deviates from the MPEG standard, The PCR values after the front end frame of the first system bit stream are rewritten so that the PCR value of the rear end frame of the first system bit stream and the PCR value of the front end frame of the first system bit stream are continuous. Thus, it is possible to provide a bit stream complying with the jitter error of the PCR packet in the MPEG standard.

  The bit stream replacement device according to the present invention includes a VBV buffer comparison unit that measures and compares a VBV buffer amount that is a buffer fullness of both the first system bit stream and the second system bit stream, A rate calculation unit controlled by an output of the VBV buffer comparison unit; and a rate change unit controlled by the output of the rate calculation unit and configured to change the rate of the bit stream of the second system.

  With this configuration, the bit stream can be transmitted within a predetermined period by transmitting the bit stream at a rate higher than the normal setting rate within the bit stream period of the second system, and as a result, on the receiver. And smooth display can be realized.

  Further, the bit stream replacement device of the present invention is provided at a subsequent stage of the code string thinning means, and at a boundary where the bit stream of the second system is switched to the first system bit stream at the rear end of the second system bit stream, It has a packet inserter for inserting a TS packet in which the value of discontinuity_indicator existing in the Adaptation Field area in the TS packet is set to “1”.

  With this configuration, the value of discontinuity_indicator existing in the Adaptation Field area in the TS packet at the boundary when switching from the rear end of the second stream of bit streams to the first stream of bit streams after the code stream decimation means After inserting the TS packet set to "1", the continuity_counter value of both systems is always synchronized when switching between the multiple system bit streams by continuously passing through the next bit stream. Therefore, the continuity_counter value in the main video bitstream can be always set to the same value in both systems. This allows the continuity_counter value to be the same in both systems even when there are multiple system switching systems when considering system redundancy. It is possible to provide a bit stream that can prevent image shock on the receiver side.

  In addition, the bitstream replacement device of the present invention is separately provided with a PCR progress calculation means for calculating the progress of the PCR value included in the input bitstream, and the PCR progress obtained by the PCR progress calculation means as inputs. A PCR controller that controls the reference clock, and the PCR progress calculating means calculates the progress of the PCR value from the PCR value included in the input bit stream and the arrival time of the packet of the input bit stream, and the PCR The clock control unit controls the reference clock so that the degree of advance matches a reference value determined separately.

  With this configuration, the progress of the PCR value included in the transport stream based on the MPEG2 encoding method is calculated, and the reference clock of the present system is controlled based on the PCR progress. Control may be performed on the original oscillator of the system so that the progress of the PCR matches the reference value. As a result, the progress of the PCR included in the input transport stream and the progress of the internal clock of the system can be matched, and the PCR error can be reduced.

  According to another aspect of the present invention, at least two systems of bit streams are input, and one of them is switched and selectively output, whereby the first system bit stream is converted to the second system bit stream. A bit stream replacement method for replacing the bit stream with respect to the second stream of bit streams according to thinning control information, and delay control for the bit stream subjected to the thinning process The transmission timing of a predetermined code string in the bit stream is selectively delayed according to the information. This method also provides the advantages of the present invention described above.

  As described above, the present invention deletes a less important frame in a bit stream as described above, and adds a packet during a blank period in the bit stream to switch between two bit streams. It is possible to provide a bitstream replacement device that has an effect that smooth switching can be performed while suppressing occurrence of a screen shock as much as possible during reproduction and ensuring resolution in the time direction.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows the configuration of the main part of the bitstream replacement device according to the embodiment of the present invention, and FIG. 2 shows the overall configuration of the bitstream replacement device. Although not particularly limited, the present embodiment will be described by replacing the main video in a television program with a CM video.

  First, the overall configuration of the bitstream replacement device will be described with reference to FIG. As shown in FIG. 2, the bitstream replacement device includes a first TS distributor 2 to which a first input TS1 (main part) is input and a second TS distributor 7 to which a second input TS6 (CM) is input. Each of the first TS distributor 2 and the second TS distributor 7 is connected to the first input buffer 3 and the second input buffer 8. The first input buffer 3 is connected to the TS switch 12 via the first CM replacement unit 4 and the first output buffer 5. The second input buffer 8 is connected to the TS switching unit 12 via the second CM replacement unit 9 and the second output buffer 10. Then, the TS switching unit 12 outputs the output TS13 (after replacement).

  In FIG. 2, a first input TS6 (main part) is a main part video bit stream called an MPEG2-encoded transport stream (hereinafter, TS) for transmitting a main part picture in a television program. . Similarly to the first input TS1, the second input TS6 (CM) is a CM video bitstream obtained by MPEG2 encoding a CM video in a television program. The first TS distributor 2 distributes the inputted main video bit stream and supplies it to the first input buffer 3 and the second input buffer 8. The second TS distributor 7 distributes the input CM video bit stream and supplies it to the first input buffer 3 and the second input buffer 8.

  The first input buffer 3 inputs the main video bit stream distributed by the first TS distributor 2 and the CM video bit stream distributed by the second TS distributor 7, and temporarily stores each bit. Extracts and manages the arrival times of packets making up the stream.

The first CM replacement unit 4 is configured to perform CM replacement, and switches between the main video bit stream and the CM video bit stream output from the first input buffer 3 based on the CM replacement timing information 11 and replaces them. It outputs to the 1st output buffer 5 as a finished bit stream. The first output buffer 5 temporarily stores the replaced bit stream and sends out the packets constituting the bit stream at a predetermined rate.

  On the other hand, the second input buffer 8, the second CM replacement unit 9 and the second output buffer 10 have the same configurations as the first input buffer 3, the first CM replacement unit 4 and the first output buffer 5, respectively. Works the same way. The replaced bit stream output from the first output buffer 5 and the replaced bit stream output from the second output buffer 10 are input to the TS switch 12, where either bit stream is selected, The output TS (after replacement) 13 is output.

  As described above, in the present embodiment, a plurality of systems having the same configuration are provided. This is to ensure the reliability of the system. When an abnormality occurs in one system, the output system is switched to the other system using the TS switch 12.

  Next, detailed configurations of the first CM replacement unit 4 and the second CM replacement unit 9 will be described with reference to FIG.

  FIG. 1 shows a detailed configuration of the first CM replacement unit 4 or the second CM replacement unit 9 in FIG. As described above, the first CM replacement unit 4 and the second CM replacement unit 9 have the same configuration, and therefore each has the configuration of FIG. Below, the 1st CM replacement part 4 and the 2nd CM replacement part 9 are simply called CM replacement part, without distinguishing. As shown in FIG. 1, the main video bitstream 21 and the CM video bitstream 25 are input to the CM replacement unit, and these bitstreams are replaced.

  The main video bitstream 21 is input to the first code string thinning unit 22. A control signal generated by the CM replacement control unit 29 based on the CM replacement timing information 11 is input to the first code string thinning unit 22. In accordance with this control signal, the first code string thinning unit 22 performs a process of thinning out a code string that is unnecessary in the CM replacement process. Here, when a process of thinning out a code string that is unnecessary for CM replacement is performed, the value of continuity_counter, which is a continuity index included in the bitstream, becomes discontinuous by the thinning process. For this reason, the output of the first code string thinning unit 22 is input to the first DI adding unit 23. The first DI adding unit 23 inserts a TS packet having a discontinuity_indicator of 1 in the Adaptation Field area in a portion where the value of continuity_counter is discontinuous. Thereby, it can be indicated in the standard that the data before the packet and the data after the packet are not continuous, and processing is performed so as not to violate the MPEG standard even if the continuity cannot be maintained. The output of the first DI adding unit 23 is sent to the first code string delay unit 24. Also in the first code string delay unit 24, the control signal generated by the CM replacement control unit 29 based on the CM replacement timing information 11 is input. Here, after the first code string delay unit 24 selectively delays the transmission timing of a predetermined code string in the bit stream in accordance with the control signal from the CM replacement control unit 29, the output is the code string switch 33. Is input.

  On the other hand, the CM video bitstream 25 is input to the second code string thinning unit 26. The second code string thinning unit 26 operates in accordance with the control signal input from the CM replacement control unit 29, thins out a code string that is not necessary for replacement, and inputs the thinned bit stream to the second DI adding unit 27. To do. The second DI adding unit 27 inserts a TS packet having a discontinuity_indicator of 1 in the Adaptation Field area at a portion where the value of continuity_counter becomes discontinuous. Then, the second code string delay unit 28 selectively delays the transmission timing of a predetermined code string in the bitstream according to the control signal from the CM replacement control unit 29. The output of the second code string delay unit 28 is rate-converted to a predetermined value by the rate converter 32 and then input to the code string switch 33.

  Also in the code string switch 33, the control signal generated by the CM replacement control unit 29 based on the CM replacement timing information 11 is input. In the code string switch 33, the main video bit stream and the CM video bit stream are selected and switched based on the CM replacement timing information, and output as a replaced bit stream.

  The code string switch 33 outputs the replaced bit stream to the PCR processing unit 34. In the replaced bit stream, when the main video bit stream and the CM bit stream are switched in the replacement bit stream, the PCR processing unit 34 inserts a PCR packet so as to fill the blank period.

  In addition, the PCR processing unit 34 performs the subsequent frame of the main video bitstream so that the PCR value of the rear frame of the CM video bitstream and the PCR value of the front frame of the main video bitstream are continuous. The process of rewriting the PCR value is also performed.

  An empty frame adding unit 35 is provided at the next stage of the PCR processing unit 34. The empty frame adding unit 35 fills the empty period of the frame because the receiver operation becomes unstable when an empty period occurs in the frame of the decoded video signal when the replaced bit stream is decoded. The video information of zero motion vector called empty frame is inserted into the bit stream. Then, the bit stream that has passed through the empty frame adding unit 35 is output as a replaced bit stream 36 from the CM replacing unit.

  A VBV (Video Buffering Verifier) buffer comparison unit 30 compares the VBV buffer amounts of both the main video bitstream 21 and the CM video bitstream 25. Based on the comparison result, the rate calculation unit 31 calculates the rate in the CM replacement period according to the size of the buffer. The output of the rate calculation unit 31 is input to the rate conversion unit 32, and the rate conversion unit 32 converts the rate of the CM video bitstream. The rate conversion unit 32 converts the rate so that the bit stream is transmitted at a rate higher than the normal set rate within the CM video bit stream period, and thereby the CM video bit stream is completely cut out within the predetermined period.

  The CM replacement control unit 29 is configured to control CM replacement by the CM replacement unit. CM replacement timing information 11 is input to the CM replacement control unit 29 from the outside. The CM replacement timing information 11 is a signal for instructing switching from the outside. As described in the above description, the CM replacement control unit 29 generates a control signal based on the CM replacement timing information 11, and the first code string thinning unit 22 and the second code string thinning unit. 26, the first code string delay unit 24, the second code string delay unit 28, and the code string switch 33.

  A control signal that the CM replacement control unit 29 supplies to the first code string thinning unit 22 and the second code string thinning unit 26 is referred to as thinning control information. The decimation control information is a signal for controlling decimation of the code sequence. Specifically, as will be described in detail later, the decimation control sequence of the B frame at the front end portion of the bit stream after replacement is thinned out. Control information. A control signal supplied from the CM replacement control unit 29 to the first code string delay unit 24 and the second code string delay unit 28 is referred to as delay control information. The delay control information is a signal that selectively delays the transmission timing of a predetermined code string in the bit stream with respect to the output after the thinning process, and specifically, as described in detail later, This is control information for delaying the I-frame code string in the front end portion of the replaced bitstream until the immediately preceding P-frame. Further, a control signal that the CM replacement control unit 29 supplies to the code string switch 33 is referred to as switching control information. The switching control information is a signal for switching between the main video stream and the CM video stream according to the CM replacement timing information.

  The configuration of the bitstream replacement device according to the present embodiment has been described above. Next, the operation of the bitstream replacement device will be described.

  FIG. 3 shows a bit stream to be subjected to replacement processing in the bit stream replacement device. In FIG. 3, in order from the top, the original video (101) of the main video, the bitstream (102) after MPEG2 encoding of the main video, the original image (201) of CM video, and the bitstream of the CM video after MPEG2 encoding (202). The horizontal position of each signal is shifted in accordance with the timing (the same applies to other drawings).

  In the figure, I, P, and B indicate frames in the GOP structure in the MPEG2 encoding system, and are respectively an I frame by intraframe encoding, a P frame by interframe forward prediction encoding, and bidirectional prediction. The B frame by encoding is represented. The numbers following I, P, and B indicate the order of the time axis, and the smaller the number, the more the past. As shown in the figure, in the bit stream after MPEG encoding, code sequences are arranged in the order of I2, B0, B1, and P5, and the order of the code sequences is changed compared to the original image.

  Next, FIG. 4 and FIG. 5 show the basic operation of bitstream replacement in the present embodiment. FIG. 4 shows a situation where duplication of the main video and CM video occurs, and FIG. 5 shows the thinning and delay processing of the present invention for preventing such duplication.

  Before explaining the thinning and delay processing, first, the end position of the main video before switching will be described. In the example of FIG. 4, the bit stream 102 of the main video ends in units of P frames. Specifically, the process ends at P8. The reason is as follows. When replacing the main video with a CM video in the TS state, switching is usually performed in units of GOPs as in the prior art. However, since the GOP is normally configured in units of 0.5 seconds (15 frames), it is difficult to match the timing in applications where the start time is important, such as CM replacement. For this reason, the present invention is configured not to control in units of GOP but to end the video before replacement in units of P frames in the GOP and then start the video after replacement from the I frame. Thus, for example, if the GOP has a configuration such as IBBPBBPBBPBBPBB, since P frames appear every two frames, an error in the CM start timing can be suppressed to a maximum of two frames.

  Next, processing of the CM video bitstream 202 at the switching part will be described. In this embodiment, since the bit stream is replaced in the TS state, the main video bit stream 102 and the CM video bit stream 202 are to be switched. When this is switched as it is, reference numeral 301 in FIG. As shown in FIG. 3, the rear end frame of the main video bit stream 102 and the front end frame of the CM video bit stream 202 may overlap in time. In this case, as indicated by reference numeral 302, since the I frame is not transmitted, it cannot be reproduced from the CM start position.

  As a countermeasure, it is conceivable to send the start time of the bit stream 202 of the CM video. However, if this is performed, the CM start time is shifted in the decoded image after the CM replacement, which is preferable from the viewpoint of CM organization. Absent.

  In order to solve this problem, in this embodiment, as shown in FIG. 5, the B1 and B2 frames unnecessary for CM playback are discarded on the bitstream in the front end frame of the CM video bitstream 202. At the same time, the position in the time axis direction on the bit stream of the I2 frame is delayed before the immediately following P5 frame. Then, switching to the bit stream of the CM video after the decimation and delay is performed by the code string switch 33 in FIG. 1, and a replacement bit stream is obtained. In FIG. 5, reference numeral 401 denotes a bit stream at the time of CM replacement in a state where overlap is avoided, and reference numeral 402 denotes a decoded image after CM replacement.

  Through the processing as described above, the rear end frame of the main video bit stream 102 and the front end frame of the CM video bit stream 202 can be prevented from overlapping in time, and smooth image switching can be realized. it can.

  In the above replacement operation, when the position in the time axis direction on the bit stream of the I2 frame is changed, when the PCR is included in the I2 frame, the value is also changed in the time axis direction. It is changed by minutes.

  In the above description, the case where the bit stream of the main video and the CM video corresponds to the bit streams of the first and second systems in the present invention is taken as an example, and at the time of switching from the main video to the CM video, Thinning and delay are performed on the front end of the bit stream of the CM video, and this processing is performed by the second code string thinning unit 26 and the second code string delay unit 28 in FIG. On the other hand, the present invention may be applied when switching from the CM video to the main video. In this case, the first code stream thinning unit 22 and the first code stream delay unit 24 in FIG. Thinning and delay processing are performed on the front end of the bit stream of the main video that switches after the video. The detailed contents of the processing are the same as described above. As described above, the present invention may be applied not only to switching from the main video to the CM video but also to switching from the CM video to the main video (hereinafter the same).

  Next, a second operation example of the bitstream replacement device according to this embodiment will be described with reference to FIG. 6 and FIG. Here, the operation of inserting a PCR packet by the PCR processing unit 34 in FIG. 2 will be described. The rate conversion operation by the rate conversion unit 32 and the like in FIG. 2 will be described.

  In FIG. 6, as a difference from FIG. 4 described above, the relationship between the reception timing of the main video bit stream and the playback time of the main video is the relationship between the reception timing of the CM video bit stream information and the playback time of the CM period. It is relatively slower than the relationship. This is represented in FIG. 6 by the amount of deviation in the horizontal direction (time axis direction), and the deviation in the horizontal direction of the reception timing and playback time differs between the main video and the CM video, and the main video is larger. . This difference occurs due to a difference in setting when MPEG2 video is encoded, and should be allowed within the buffer range in the MPEG2 standard.

  In this case, as indicated by reference numeral 312 in FIG. 6, in the frame at the leading edge of the CM replacement, the P8 frame at the end of the main part and the I2 frame at the start of the CM are adjacent to each other in the decoded image after the CM replacement. Easy. However, as indicated by reference numeral 311, when considering bit stream information, a TS blank period is generated from the B7 frame at the end of the main part to the I2 frame at the start of CM, and PCR ( Program Clock Reference) The packet arrival interval may be out of the range defined by the MPEG standard, which is not preferable for the operation of the receiver.

  Further, at the rear end of the CM replacement, as shown by reference numeral 311, if the overlap between the CM packet position and the main packet position on the TS is prevented, a period during which the frame cannot be transmitted occurs. At the rear end of the decoded image after CM replacement, a blank will be generated from the last P5 frame of the CM video to the I2 frame at the start of the main part. During this period, the receiver is in an unstable operation state, and the receiver is abnormal. This is not preferable because there is a risk that the operation will occur.

  The process of the present invention for this countermeasure is shown in FIG. In the present invention, as indicated by reference numeral 411, a process for eliminating a blank period is performed by newly creating and superimposing a PCR packet in a blank period of a bit stream at the time of switching. The PCR packet is empty information of only PCR, and this processing is performed by the PCR processing unit 34 in FIG. As a result, it is possible to comply with the standard of the PCR transmission interval and to prevent an abnormal operation of the receiver.

  In addition, in order to prevent a blank from occurring at the rear end of the decoded image after CM replacement between the frame at the end of the CM video and the frame at the start of the main part, the rate conversion unit 32 and the like operate as shown by reference numeral 411. During the period, a predetermined data transmission amount is secured for the CM video by transmitting the bit stream at the time of CM replacement at a rate higher than the normal set rate. As a result, it is possible to complete the CM bit stream within the CM period, and as a result, B6, B7, and P8 frames are displayed on the receiver as indicated by reference numeral 412 to prevent the occurrence of blanks at the CM end portion. It becomes possible. If there is still a gap (gap) at the playback image display timing between the P8 frame at the rear end of the CM and the I2 frame at the front end of the main part, the empty frame adding section 35, as shown in FIG. Inserting an empty frame with zero motion vector at the end stabilizes the receiver operation and prevents malfunction of the receiver. At this time, if necessary, a PCR packet is newly inserted in the same manner as described above in order to comply with the standard of the PCR transmission interval.

  Next, an operation of inserting a TS packet by the first DI adding unit 23 and the second DI adding unit 27 will be described.

  As shown in the present embodiment, in general, when CM replacement is performed, system redundancy is provided in view of its economic importance. In such a configuration, it is a general usage to prepare a plurality of systems, cause them to perform the same processing, and switch to another system when an abnormality occurs in one system. In this case, in order to prevent shock at the receiver side when the system is switched, each system must be completely synchronized at the clock level and the same signal must be output at the same time. There is a problem that the price of the system increases because the circuit scale increases when the operation is realized.

  In order to avoid an increase in circuit scale as described above, the following processing is performed in the present embodiment. Here, since the bit stream is discretely transmitted in the time axis direction in units of TS packets, the system is switched at the timing when TS packets are not transmitted or when invalid packets called NULL packets are transmitted. When the system is implemented and both systems transmit signals at almost the same timing, no abnormality can be detected from the viewpoint of the receiver.

  Therefore, in the present invention, a TS packet in which the discontinuity_indicator value existing in the Adaptation Field area in the TS packet is set to “1” is inserted at the boundary when switching from the CM video to the main video, and then the main video bitstream is continued. The output is made through.

  FIG. 8 shows the continuity_counter values of both systems at the time of CM replacement. Reference numeral 501 indicates a normal operation when switching from the CM video period to the main video period, and reference numeral 502 indicates the CM video in the present invention. The operation at the time of switching from the period to the main video period is shown. System 1 and system 2 in the figure correspond to the two systems in FIG.

  In the example of FIG. 8, as indicated by reference numeral 501, the continuity_counter values of the 1st system and the 2nd system do not match in the CM video period. It does not agree with.

  On the other hand, with reference numeral 502 representing the processing of the present embodiment, even if the continuity_counter values of both systems are different during the CM period, the TS packet in which the discontinuity_indicator value is once set to “1” when returning from the CM to the main part. The main part TS is continuously transmitted with the continuity_counter value originally assigned to the main part since the insertion. This allows the receiver to recognize that the discontinuity of the continuity_counter value of the TS is not a problem in the standard, and the continuity_counter value in the main video bitstream can be forcibly set to the same value in both systems. As an effect, it is possible to prevent occurrence of a shock on the receiver side even when system switching is performed.

  Next, PCR value rewriting processing by the PCR processing unit 34 will be described. This rewriting process satisfies such a request by paying attention to the necessity of ensuring the continuity of the PCR value during the main period and the CM period when the above-described CM replacement is performed.

  FIG. 9 and FIG. 10 show the relationship between the elapsed time and the PCR counter value. First, a case where PCR rewriting according to the present embodiment is not performed will be described with reference to FIG. It is conceivable that the encoder to be encoded is different between the main period and the CM period. In this case, the progress of the PCR value in time units may be different between the main period (a) and the CM period (b). . In the graph, the difference in PCR progress is represented by the difference in the slope of the straight line in the main period (a) and the CM period (b). Next, when returning from the CM period (b) to the main period (c), the input TS is output as it is for the main period, and therefore the position extended from the main period (a) with the same inclination on the graph. Is connected to the main period (c). However, since the slope of the CM period (b) is different, the PCR value is greatly different at the timing of switching from the CM period (b) to the main period (c). This change in the PCR value is detected as PCR jitter on the receiver side, which may cause a problem such as a deviation from the standard.

  In order to prevent this, in the embodiment of the present invention, as shown in FIG. 10, the main period (c) is such that the last PCR value in the CM period (b) and the first PCR value in the main period (c) are continuous. Rewrite the PCR value). As a result, even if CM replacement is performed, PCR jitter does not occur, and CM replacement with stable receiver operation is realized.

Next, different embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 11 is a block diagram showing an embodiment of a bitstream replacement device according to the present invention. In FIG. 11, the configuration of the parts common to FIG. 2 is appropriately omitted. In addition, FIG. 11 shows the configuration of the present embodiment with respect to the first system of FIG. Of course, a similar configuration is provided in the second system, and the same processing may be performed.

  In FIG. 11, the first input buffer 3, the first CM replacement unit 4, and the first output buffer 5 have the same configuration as the above-described embodiment and operate in the same manner. That is, the first input buffer 3 is an input buffer for receiving and temporarily storing a transport bit stream (hereinafter referred to as TS) according to the MPEG2 encoding method. The first input TS 1 (main video bit stream) and the first input buffer 3 Two-input TS2 (CM video bitstream) is input to the first CM replacement unit 4. The first CM replacement unit 4 replaces the bit stream. The replaced bit stream is temporarily stored in the first output buffer 5 and then output as the output TS 13 (after replacement) via the TS switch 12 (not shown in FIG. 11) in FIG. The

  In the present embodiment, a first PCR progress calculation unit 41, a first clock control unit 42, a second PCR progress calculation unit 43, and a second clock control unit 44 are further added.

  The first PCR progress calculation unit 41 calculates the progress of the PCR included in the first input TS1 (main part). The first clock control unit 42 controls the reference clock of this system based on the PCR progress obtained by the first PCR progress calculation unit 41. When the first input buffer 3 captures the first input TS1 (main video bitstream), the arrival time of the packet of the input TS is extracted, and the first PCR progress calculation unit 41 calculates the PCR value and the arrival time of the packet. The progress of the PCR value is calculated. When the progress of the PCR is different from the reference value (27 MHz in the MPEG2 standard), the first clock control unit 42 is controlled to reduce the difference. As a result, the progress of the input PCR and the progress of the internal clock of the system can be matched, and the PCR error can be reduced.

  The second PCR progress calculation unit 43 and the second clock control unit 44 have the same configuration as the first PCR progress calculation unit 41 and the second clock control unit 44 described above. However, unlike the above, the same processing is performed on the second input TS6 (CM video bitstream).

  In the embodiment described above, the case where the two stream inputs are switched to each other has been described. However, when one stream input is replaced with a stream of a file format prepared in advance, the present embodiment is also applicable. It goes without saying that the invention is applicable. In this case, a file format stream is read and processed, and used as a bit stream for replacement processing.

  For example, it is assumed that the CM video is a file format stream. In this case, a CM content storage unit may be provided, and this CM content storage unit may store the CM content to be replaced from the input TS by the CM replacement unit. The timing at which this content is read and the CM is replaced by the CM replacement unit may be controlled by the CM replacement control unit.

  Further, the processing sequence of each part constituting this embodiment, such as a code stream thinning unit, DI adding unit, code sequence delay unit, code sequence switch, and PCR processing unit, is not limited to this embodiment. Each can also be applied individually.

  The bitstream replacement device according to the embodiment of the present invention has been described above. In the example of the present embodiment, the first system bit stream is a main video bit stream, and the second system bit stream is a CM video bit stream. According to the present embodiment, when the bit stream of the first system is replaced with the bit stream of the second system, the code string is thinned out from the bit stream of the second system, A process for selectively delaying the transmission timing of a predetermined code string in the stream was performed. Thereby, smooth image switching can be realized as described below.

  That is, when switching between the first system bit stream and the second system bit stream is simply performed in units of GOPs, the rear end frame of the first system bit stream and the second system bit stream Assume that the frames at the front end of the two systems of bit streams overlap in time. Even in such a case, at the front end of the second system bitstream, a code string that is unnecessary for video reproduction of the second system bitstream is discarded on the bitstream by thinning-out processing. The position in the time axis direction on the bit stream of the code string that has not been processed is delayed. As a result, the rear end frame of the first system bit stream and the front end frame of the second system bit stream are prevented from overlapping in time, and resolution degradation in the time axis direction due to thinning is also avoided. Thus, smooth image switching can be realized.

  Further, according to the present embodiment, a frame by bidirectional inter-frame encoding that is unnecessary for video reproduction of the second system bit stream is displayed on the bit stream at the front end frame of the second system bit stream. While discarding, the position in the time axis direction on the bit stream of the frame by intra-frame coding is delayed. In the above example, the frame by intra-frame coding is delayed before the frame by the immediately following inter-frame forward predictive coding. Thereby, it is possible to avoid the temporally overlapping of the rear end frame of the first system bit stream and the front end frame of the second system bit stream, thereby realizing smooth image switching.

  In the present embodiment, as already described repeatedly, the first system bit stream is the main video bit stream, and the second system bit stream is the CM video bit stream. Smooth image switching from video to CM video can be realized.

  Further, in the present embodiment, as described above, the PCR packet is added during the period when the code string thinning unit thins out and becomes blank. This makes it possible to provide a bit stream that complies with the arrival interval of PCR packets in the MPEG standard.

  Further, according to the present embodiment, as shown in FIG. 10, the PCR value of the rear end frame of the second system bit stream and the PCR value of the frame of the first system bit stream are continuous. The PCR value after the front end frame of the first system bit stream is rewritten so as to be the value obtained. With this configuration, when there is a large difference between the PCR value of the rear end frame of the second system bit stream and the PCR value of the front end frame of the first system bit stream that deviates from the MPEG standard, The PCR values after the front end frame of the first system bit stream are rewritten so that the PCR value of the rear end frame of the first system bit stream and the PCR value of the front end frame of the first system bit stream are continuous. Thus, it is possible to provide a bit stream complying with the jitter error of the PCR packet in the MPEG standard.

  Further, according to the present embodiment, rate calculation and rate change are performed as described above. With this configuration, the bit stream can be transmitted within a predetermined period by transmitting the bit stream at a rate higher than the normal setting rate within the bit stream period of the second system, and as a result, on the receiver. And smooth display can be realized.

  Further, according to the present embodiment, as described above, a packet inserter (DI adding unit in the above example) for inserting a TS packet in which the value of discontinuity_indicator is set to “1” is provided. The discontinuity_indicator value existing in the Adaptation Field area in the TS packet is set to “1” at the boundary when switching from the second system bit stream to the first system bit stream after the code string thinning means. By inserting the TS packet and continuing through the next bit stream, the continuity_counter value of both systems can always be synchronized when switching between multiple system bit streams. The continuity_counter value in the stream can always be the same value in both systems. This allows the continuity_counter value to be the same in both systems even when there are multiple system switching systems when considering system redundancy. It is possible to provide a bit stream that can prevent image shock on the receiver side.

  Further, according to the present embodiment, the progress of the PCR value included in the transport stream based on the MPEG2 encoding method is calculated, and the reference clock of the present system is controlled based on the PCR progress. Control is performed on the original oscillator of the system so that the progress of the PCR matches the reference value. As a result, the progress of the PCR included in the input transport stream and the progress of the internal clock of the system can be matched, and the PCR error can be reduced.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and it goes without saying that those skilled in the art can modify the above-described embodiments within the scope of the present invention.

  As described above, the bit stream replacement device according to the present invention has an effect of smoothly switching a plurality of bit streams, and is useful as a bit stream replacement device for digital broadcasting or the like.

The block block diagram which shows the principal part detailed structure of the bit stream replacement apparatus which concerns on embodiment of this invention The block block diagram which shows the whole structure of the bit stream replacement apparatus which concerns on embodiment of this invention The figure which shows the bit stream of the main image image | video and CM image | video used as replacement object in this Embodiment Timing chart showing an example where overlap occurs during CM replacement Timing chart showing CM replacement processing for performing decimation and delay processing in the present embodiment Timing chart showing an example where a blank period occurs during CM replacement Timing chart showing CM replacement processing for performing packet addition and rate change in the present embodiment Timing chart for explaining a two-system synchronization method when replacing the main video and CM video in the present embodiment The figure explaining the jitter of PCR in the replacement control of the main video and CM video The figure explaining the PCR rewriting process for the jitter elimination in the replacement control of the main video and the CM video The block block diagram which shows the bit stream replacement apparatus which concerns on another embodiment of this invention.

Explanation of symbols

1 First input TS
2 1st TS distributor 3 1st input buffer 4 1st CM replacement part 5 1st output buffer 6 2nd input TS
7 Second TS distributor 8 Second input buffer 9 Second CM replacement unit 10 Second output buffer 11 CM replacement timing information 12 TS switcher 13 Output TS
21 Main Video Bitstream 22 First Code String Decimation Unit 23 First DI Addition Unit 24 First Code String Delay Unit 25 CM Video Bitstream 26 Second Code String Decimation Unit 27 Second DI Addition Unit 28 Second Code String Delay Unit 29 CM replacement control unit 30 VBV buffer comparison unit 31 Rate calculation unit 32 Rate conversion unit 33 Code string switch 34 PCR processing unit 35 Empty frame addition unit 36 Replaced bit stream

Claims (9)

A bit stream replacement device that replaces a first system bit stream with a second system bit stream by inputting at least two systems of bit streams and selectively outputting one of them. ,
Code string decimation means for performing code string decimation on the bit stream of the second system according to decimation control information;
And a bit stream delay means for selectively delaying transmission timing of a predetermined code string in the bit stream according to delay control information with respect to the output of the code string thinning means Replacement device.   A replacement control unit that generates the decimation control information and the delay control information according to the replacement timing information of the bitstream and supplies the decimation control information and the delay control information to the code string decimation means and the code string delay means, respectively, The replacement control unit supplies, as the decimation control information, control information for decimation of a code string of a frame by inter-frame bi-directional predictive coding at the front end portion of the second system bit stream, and as the delay control information 2. The bit stream replacement device according to claim 1, wherein control information for delaying a code string of a frame by intra-frame coding at a front end portion of the bit stream of the second system is supplied.   3. The bit stream replacement according to claim 1, wherein the first system bit stream is a main video bit stream, and the second system bit stream is a CM video bit stream. apparatus.   A bit stream switching means provided at a subsequent stage of the code string delay means, and a PCR processing section provided at a subsequent stage of the bit stream switching means, wherein the PCR processing section 4. The bit stream replacement device according to claim 1, wherein a PCR packet is added during a period when the space is drawn and left blank.   A bit stream switching unit provided at a subsequent stage of the code string delay unit; and a PCR processing unit provided at a subsequent stage of the bit stream switching unit, wherein the PCR processing unit includes the bit stream of the second system And the subsequent frame of the first stream of the first stream so that the PCR value of the frame of the first stream and the PCR of the frame of the first stream of the first stream of the first stream that follows are consecutive values. 4. The bit stream replacement device according to claim 1, wherein the PCR value is rewritten.   A VBV buffer comparison unit that measures and compares the VBV buffer amount, which is a buffer fullness of both the first system bit stream and the second system bit stream, and a rate calculation that is controlled by the output of the VBV buffer comparison unit 6. The bit according to claim 1, further comprising a rate changing unit that is controlled by the output of the rate calculating unit and changes the rate of the bit stream of the second system. Stream replacement device.   The discontinuity_indicator value provided in the Adaptation Field area in the TS packet at the boundary where the bit stream of the second system is switched to the first system bit stream at the rear end of the second system bit stream. 7. The bit stream replacement device according to claim 1, further comprising a packet inserter that inserts a TS packet in which is set to “1”.   PCR progress calculating means for calculating the progress of the value of PCR included in the input bitstream, and a clock control section for controlling a reference clock prepared separately using the PCR progress obtained by the PCR progress calculating means as an input The PCR progress calculation means calculates the progress of the PCR value from the PCR value included in the input bitstream and the arrival time of the packet of the input bitstream, and the progress of the PCR matches a separately determined reference value. The bit stream replacement device according to claim 1, wherein the clock control unit controls a reference clock. A bitstream replacement method for replacing a first system bitstream with a second system bitstream by inputting at least two systems of bitstreams and selectively outputting one of them. ,
The code stream is thinned out according to the thinning-out control information for the bit stream of the second system, and the predetermined code in the bit stream is turned out according to the delay control information for the bit stream subjected to the thinning-out A bitstream replacement method characterized by selectively delaying the transmission timing of a column.

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