JP2008277602A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively evade the generation of scratches or the like on a wafer back surface caused by the chipping of a wafer or the like while maintaining the service life and grinding characteristics of a rotary grinding stone for finish grinding in a practical range in a manufacturing process of a semiconductor integrated circuit device, in a back grinding process for grinding the back surface of the wafer and turning it to a desired thickness and a stress relief process integrated with it for details. <P>SOLUTION: In the finish grinding in the back grinding process serving also as the stress relief process, the finish grinding is performed while pressing a grinding stone 105 for toothing to a grinding stone 107 for grinding only in a spark-out period in which the wafer back surface is polished in a rotating state from the finish grinding basically. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique that is effective when applied to a back grinding technique in a method for manufacturing a semiconductor integrated circuit device (or semiconductor device).

  In Japanese Patent Laid-Open No. 9-148283 (Patent Document 1), in finish grinding of a back grinding process using a wafer fixing technique using wax, a work surface due to clogging of a grinding blade, peeling, cracks, etc. are reported. In order to avoid this, it is disclosed to grind while sharpening the grindstone of the grinding blade.

JP-A-9-148283

  In general, back grinding of semiconductors consists of two stages: rough grinding and fine grinding. According to the study of the finish grinding by the present inventors, the following has been clarified. In other words, resin grindstones (diamond abrasive grains as resinoid binders) with a fixed abrasive grain size of approximately # 2000 (JIS or standard number in the grinder / wheel industry) are generally used for finish grinding. However, the back surface is too rough to ensure the final bending strength of the integrated circuit chip. On the other hand, if complete mirror finishing is performed by finish grinding and dry polishing to secure the bending strength, the impurity gettering effect on the back surface is lost and contamination from the back surface cannot be avoided. Then, a resinoid grindstone having an abrasive grain size of about 8000 was applied to finish grinding to attempt a mirror finish, but it was found that good grinding characteristics could not be obtained because the abrasive grains were immersed in a soft resinoid binder. This problem seems to be solved by using a hardened vitrified grindstone, but then the contact area between the wafer and the grindstone increases as a result of the fine abrasive grains, resulting in wafer burning. In this regard, it has been found that holes may be introduced into the vitrified grindstone to reduce the contact area between the wafer and the grindstone. However, it has been found that, as a result, scratches are generated as a result of trapping foreign matters or the like in the holes on the grindstone surface. On the other hand, as described in Japanese Patent Application Laid-Open No. 9-148283, it is conceivable to perform finish grinding while pressing a dressing grindstone (dresser) against the grinding grindstone, but the grinding grindstone is severely worn. Not practical.

  An object of the present invention is to provide a manufacturing process of a semiconductor integrated circuit device suitable for mass production.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to the present invention, in the finish grinding in the back-grinding process, the finish grinding is basically performed only while the sharpening wheel is pressed against the grinding wheel only during the sparkout period.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in finish grinding in the back-grinding process, the back-grinding process is suitable for mass production by finishing grinding while pressing the sharpening wheel against the grinding wheel only for a predetermined period that causes scratches. Can be.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A step of attaching a surface protection tape to the first main surface of the wafer on which the device is formed;
(B) a step of vacuum-sucking the first main surface side of the wafer on which the surface protection tape is attached to a first wafer stage of a grinding apparatus;
(C) While being vacuum-sucked to the first wafer stage, rough grinding (rough grinding) the second main surface of the wafer with a first rotating grindstone (grinding wheel), Grinding the thickness of the wafer to a first thickness;
(D) After the step (c), the second main surface of the wafer is moved from the first rotating grindstone while being vacuum-sucked to the first wafer stage or the second wafer stage. A step of grinding the thickness of the wafer to a second thickness smaller than the first thickness by finish grinding with a second rotating grindstone having a small abrasive grain size,
Here, the finish grinding step of step (d) includes the following sub-steps:
(I) a step of landing the second rotating grindstone on the second main surface of the wafer;
(Ii) grinding the second main surface of the wafer under a first pressure in a state where the second rotating grindstone and the second main surface of the wafer are in contact with each other;
(Iii) Subsequent to the step (ii), in a state where the second rotating grindstone and the second main surface of the wafer are in contact with each other, under a second pressure lighter than the first pressure, Grinding the second main surface of the wafer;
(Iv) Following the step (iii), a step of separating the second rotating grindstone from the second main surface of the wafer;
Here, during the partial period of the finish grinding process, while the sub-process (iii) is performed, the setting grindstone is pressed against the second rotating grindstone.

  2. In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the sharpening period in which the sharpening grindstone is pressed includes the entire period in which the sub-process (iii) is performed.

  3. In the method of manufacturing a semiconductor integrated circuit device according to the item 2, the sharpening period in which the sharpening grindstone is pressed includes the entire period in which the lower step (iii) is performed, and beyond that, the lower step (ii) ) Extends to the end of the period.

  4). In the method of manufacturing a semiconductor integrated circuit device according to the item 3, the sharpening period in which the sharpening grindstone is pressed includes the entire period in which the sub-process (iii) is performed, and beyond that, the sub-process (iv) ) Spans the period that begins.

  5. In the manufacturing method of the semiconductor integrated circuit device according to the item 1, the dressing period in which the dressing grindstone is pressed does not include the time of disclosure or the end of the entire period in which the sub-process (iii) is performed.

  6). In the manufacturing method of the semiconductor integrated circuit device according to the item 1, the dressing period in which the sharpening grindstone is pressed does not include the time of disclosure and the end of the entire period in which the substep (iii) is performed.

  7. 7. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 1 to 6, the sharpening grindstone is held in a movable manner.

  8). 8. In the method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 7, the hardness of the binder of the sharpening grindstone is higher than the hardness of the binder of the second rotating grindstone (note that the dressing grindstone is Even if the binder has a softer hardness or the same hardness as that of a rotating grindstone, it can be applied by changing the shape, combination with abrasive grains, etc. It is not limited to a grindstone-like one. Needless to say).

  9. 9. In the method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 8, the abrasive grains of the sharpening grindstone are smaller than the abrasive grains of the second rotating grindstone (the same applies to the dressing). The grindstone can be applied by changing the shape, fixing method, combination with a binder, etc., even if the grindstone has a larger average particle diameter or is equivalent to that of a rotating grindstone. ).

  10. 10. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 1 to 9, a grinding liquid or grinding water is supplied to the sharpening grindstone during the sharpening period.

11. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A step of attaching a surface protection tape to the first main surface of the wafer on which the device is formed;
(B) a step of vacuum-sucking the first main surface side of the wafer on which the surface protection tape is attached to a first wafer stage of a grinding apparatus;
(C) In a state where the first wafer stage is vacuum-sucked, the second main surface of the wafer is roughly ground by a first rotating grindstone, thereby reducing the thickness of the wafer to the first thickness. Grinding to a thickness;
(D) After the step (c), the second main surface of the wafer is moved from the first rotating grindstone while being vacuum-sucked to the first wafer stage or the second wafer stage. A step of grinding the thickness of the wafer to a second thickness smaller than the first thickness by finish grinding with a second rotating grindstone having a small abrasive grain size,
Here, the finish grinding step of step (d) includes the following sub-steps:
(I) a step of landing the second rotating grindstone on the second main surface of the wafer;
(Ii) grinding the second main surface of the wafer under a first pressure in a state where the second rotating grindstone and the second main surface of the wafer are in contact with each other;
(Iii) Subsequent to the step (ii), in a state where the second rotating grindstone and the second main surface of the wafer are in contact with each other, under a second pressure lighter than the first pressure, Grinding the second main surface of the wafer;
(Iv) Following the step (iii), a step of separating the second rotating grindstone from the second main surface of the wafer;
Here, it is a partial period of the finish grinding process, and while the sub-process (iii) is performed, a sharpening grindstone is pressed against the second rotating grindstone, and the partial period In the finish grinding process other than the above, the sharpening grindstone is not pressed.

  12 12. In the manufacturing method of a semiconductor integrated circuit device according to the item 11, the dressing period in which the dressing grindstone is pressed includes the entire period in which the sub-process (iii) is performed.

  13. 12. In the method of manufacturing a semiconductor integrated circuit device according to the item 12, the sharpening period in which the sharpening grindstone is pressed includes the entire period in which the lower step (iii) is performed, and beyond that, the lower step (ii) ) Extends to the end of the period.

  14 14. In the method of manufacturing a semiconductor integrated circuit device according to the item 13, the sharpening period in which the sharpening grindstone is pressed includes the entire period in which the lower step (iii) is performed, and further beyond that, the lower step (iv) ) Spans the period that begins.

  15. 12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the dressing period in which the dressing grindstone is pressed does not include the time of disclosure or the end of the entire period in which the sub-process (iii) is performed.

  16. 12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the dressing period in which the dressing grindstone is pressed does not include the time of disclosure and the end of the entire period in which the substep (iii) is performed.

  17. 17. In the method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 16, the sharpening grindstone is held in a movable manner.

  18. 18. In the method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 17, the hardness of the binder of the sharpening grindstone is higher than the hardness of the binder of the second rotating grindstone.

  19. 19. In the method of manufacturing a semiconductor integrated circuit device according to any one of 11 to 18, the abrasive grain size of the sharpening grindstone is smaller than the grain size of the abrasive grain of the second rotating grindstone.

  20. 20. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 11 to 19, a grinding liquid or grinding water is supplied to the sharpening grindstone during the sharpening period.

  Next, an outline of another embodiment of the invention disclosed in the present application will be described.

  21. The back surface of the wafer is finish-ground with a rotating grindstone so that the thickness of the wafer becomes the target thickness, and then the obtained integrated circuit chip is printed on a wiring board or other substrate without substantially changing the target thickness. A method of manufacturing a semiconductor integrated circuit device to be fixed on a semiconductor chip, wherein only for a certain period during the finish grinding (here, “only” may be temporary, intermittent, etc. in a part other than the certain period) This method does not exclude pressing with a time interval so that the wheel does not wear substantially, or pressing with a weak pressure within a range where wear is substantially acceptable). A semiconductor integrated circuit device manufacturing method that applies a sharpening wheel (not limited to the so-called grindstone, as long as it can be sharpened) (generally a sharpening wheel is used for backside grinding other than finish grinding) Iga, may be applied to uncle you need to. However, the life of the grinding wheel is shortened when dressing). Needless to say, even if it is referred to as finish grinding, all subsequent processes do not exclude similar processing such as grinding (further grinding processing, dry polishing, chemical etching, and other processing). For example, when there is a gettering layer in the wafer, or when a gettering layer is formed on the backside by another method, contamination from the backside can be avoided without forming a crushed layer on the backside of the wafer by finish grinding. Etc.

  22. 22. In the method of manufacturing a semiconductor integrated circuit device according to the item 21, the predetermined period includes a main part of a spark-out step during the finish grinding.

  23. 23. In the method for manufacturing a semiconductor integrated circuit device according to the item 21 or 22, the sharpening grindstone is used during the predetermined period (even if “during the period” does not necessarily supply water during the entire period). Grinding fluid or grinding water is supplied.

  24. 24. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 21 to 23, the wafer is rotated in the same direction as the rotary grindstone during the finish grinding.

  25. 25. In the method for manufacturing a semiconductor integrated circuit device according to any one of 21 to 24, the finish grinding is performed by outer and inner grinding.

  26. The back surface of the wafer is finish-ground with a rotating grindstone so that the thickness of the wafer becomes the target thickness, and then the obtained integrated circuit chip is printed on a wiring board or other substrate without substantially changing the target thickness. A method of manufacturing a semiconductor integrated circuit device fixed on a semiconductor chip, wherein a sharpening grindstone (not limited to a so-called grindstone, anything that can sharpen) is applied to the rotating grindstone for a certain period of time during the finish grinding. In this case, a method of manufacturing a semiconductor integrated circuit device is performed while supplying a grinding liquid or grinding water (or cleaning liquid or cleaning water) to the sharpening grindstone.

  27. 27. In the method of manufacturing a semiconductor integrated circuit device according to the item 26, the predetermined period includes a main part of a spark-out step during the finish grinding.

  28. 28. In the method of manufacturing a semiconductor integrated circuit device according to the item 26 or 27, the wafer is rotated in the same direction as the rotary grindstone during the finish grinding.

  29. 29. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 26 to 28, the finish grinding is performed by outer and inner grinding.

  30. After half-cut dicing from the front surface of the wafer, a surface protection tape is applied to the front surface of the wafer, and the back surface of the wafer is finish ground with a rotating grindstone so that the thickness of the wafer becomes the target thickness in that state. Thereafter, a method of manufacturing a semiconductor integrated circuit device, wherein the obtained integrated circuit chip is fixed on a wiring board or other semiconductor chip without substantially changing the target thickness, and is fixed during the finish grinding. A method for manufacturing a semiconductor integrated circuit device, wherein a sharpening stone (not limited to a so-called grindstone, anything that can be sharpened) is applied to the rotating grindstone for a period of time.

  31. In the method of manufacturing a semiconductor integrated circuit device according to the item 30, the fixed period includes a main part of a spark-out step during the finish grinding.

  32. In the method of manufacturing a semiconductor integrated circuit device according to the item 30 or 31, a grinding liquid or grinding water is supplied to the sharpening stone during the certain period.

  33. 33. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 30 to 32, the wafer is rotated in the same direction as the rotary grindstone during the finish grinding.

  34. 34. In the method for manufacturing a semiconductor integrated circuit device according to any one of 30 to 33, the finish grinding is performed by outer and inner grinding.

35. A method for manufacturing a semiconductor integrated circuit device, comprising: finishing grinding a back surface of a wafer with a rotating grindstone; and thereafter fixing the obtained integrated circuit chip onto a wiring substrate or another semiconductor chip via the back surface of the wafer. Including the following steps:
(A) performing grinding without applying a sharpening wheel to the rotating wheel during a first period during the finish grinding;
(B) A step of performing grinding while applying the sharpening grindstone to the rotating grindstone during a second period after the first period during the finish grinding.

  36. 36. In the method of manufacturing a semiconductor integrated circuit device according to the item 35, the second period is shorter than the first period.

  37. 38. In the method for manufacturing a semiconductor integrated circuit device according to the item 35 or 36, the second period includes a main part of a spark-out step during the finish grinding.

  38. 38. In the method of manufacturing a semiconductor integrated circuit device according to any one of 35 to 37, a grinding liquid or a grinding water is supplied to the sharpening grindstone during the second period.

39. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A step of attaching a surface protection tape to the first main surface of the wafer on which the device is formed;
(B) a step of vacuum-sucking the first main surface side of the wafer on which the surface protection tape is attached to a first wafer stage of a grinding apparatus;
(C) In a state where the first wafer stage is vacuum-sucked, the second main surface of the wafer is roughly ground by a first rotating grindstone, thereby reducing the thickness of the wafer to the first thickness. Grinding to a thickness;
(D) After the step (c), the second main surface of the wafer is moved from the first rotating grindstone while being vacuum-sucked to the first wafer stage or the second wafer stage. A step of grinding the thickness of the wafer to a second thickness smaller than the first thickness by finish grinding with a second rotating grindstone having a small abrasive grain size,
Here, the finish grinding step of step (d) includes the following sub-steps:
(I) executing the finish grinding without applying a sharpening stone to the second rotating grindstone during the first period;
(Ii) A step of executing the finish grinding process in a second period after the first period while applying a sharpening grindstone to the second rotating grindstone.

  40. 40. In the method of manufacturing a semiconductor integrated circuit device according to item 39, the second period is shorter than the first period.

  41. 41. In the method of manufacturing a semiconductor integrated circuit device according to 39 or 40, the second period includes a main part of a spark-out step during the finish grinding.

  42. 42. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 39 to 41, the sharpening grindstone is held in a movable manner.

  43. 43. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 39 to 42, the hardness of the binder of the sharpening grindstone is higher than the hardness of the binder of the second rotating grindstone.

  44. 44. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 39 to 43, a grain size of the abrasive grains of the sharpening grindstone is smaller than a grain size of the abrasive grains of the second rotating grindstone.

  45. 45. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 39 to 44, a grinding fluid or grinding water is supplied to the sharpening grindstone during the second period.

  46. 46. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 39 to 45, the second rotating grindstone is a vitrified grindstone.

  47. In the method for manufacturing a semiconductor integrated circuit device according to the item 46, the second rotating grindstone is a grindstone having innumerable pores.

  48. 48. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 39 to 47, the second rotating grindstone has an abrasive grain size of less than 1 μm.

  49. 48. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 39 to 47, the second rotating grindstone has an abrasive grain size of less than 0.5 μm.

  50. 50. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 39 to 49, a cleaning liquid or cleaning water is supplied to the second rotating grindstone by a jet nozzle or a two-fluid jet nozzle during the second period. Yes.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of parts for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

  3. Similarly, preferred examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to them unless specifically stated otherwise and clearly not from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise apparent from the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device or an electronic device) is formed, but is an epitaxial wafer, an SOI wafer, a composite of an insulating substrate and a semiconductor layer, etc. Needless to say, wafers are also included. In addition, what is already separated into the chip area after dicing or the like is fixed to the dicing tape or the surface protection tape when collectively shown as a “wafer”. In this application, a silicon-based wafer will be mainly described, but the present invention can also be applied to other GaAs-based wafers, insulating wafers such as glass and ceramics, and the like.

  6). The characteristics of the abrasive (Abrasive) mainly depend on the structural features such as abrasive grains, binder, their bonding state, and the presence or absence of pores (porous), but the same binder and structural features. Depends mainly on the grain size of the abrasive grains (number display #N, for example, # 350). The larger the numerical value of the number display, the smaller the average grain size of the abrasive grains (simply referred to as “abrasive grain size”). (The numerical value after # representing the diameter of the abrasive grains corresponds to the size of the sieve eye that separates the abrasive grains when manufacturing a grindstone, etc. In other words, it corresponds to the diameter of the main abrasive grains contained in it. For example, the particle size of # 280 is approximately 100 μm, the particle size of # 360 is approximately 40 to 60 μm, the particle size of # 2000 is approximately 4 to 6 μm, and the particle size of # 4000 is approximately 2 About 4 μm, # 8000 particle size is about 0.2 μm, and in this application, the characteristics of the grindstone related to the diameter of the abrasive grains will be described in accordance with this. For those that do not have this standard, the standard of the following Disco products is used.) Diamond is generally used for the abrasive grains, but other materials may be used. Grinding stones used in the grinding process are generally mixed with diamond abrasive grains and inorganic binders, or coated with ceramics on the surface and fired, and diamond abrasive grains with organic binders (resin Resinoid type (resin has phenol type, polyimide type, etc.) hardened by bond) or intermediate type. Generally, resin-based binders are considered to have less grinding damage. Further, as applicable abrasive grains (fixed abrasive grains), there are silicon carbide, alumina base abrasive grains, CBN (Cubic Boron Nitride), etc. in addition to diamond. Examples of commercially available grinding wheels for finishing grinding (rotary grinding wheels) include DISCO Corporation's grinding wheel IF series, GF01 series, and Polygrind series.

  7. “Sharpening” of a grinding stone is also called dressing or conditioning. In this application, the surface of the grinding stone is mainly rubbed with a hard object to remove surface deposits (chipping debris, old abrasive grains) and old binders. It refers to giving out a new binder surface (resulting in new abrasive grains) in the lower layer.

[Details of the embodiment]
The embodiment will be further described in detail. Note that a composite type grindstone obtained by impregnating a resin with a vitrified grindstone having pores is disclosed in detail in Japanese Patent Application Laid-Open No. 2007-12810 (or corresponding US Publication No. 2007-0004180). Further, the prevention of contamination on the backside of the wafer is disclosed in detail in Japanese Patent Application Laid-Open No. 2005-210038 (or corresponding US Publication No. 2005-0142815) by the inventors of the present application. Further, edge trimming is disclosed in detail in Japanese Patent Application Laid-Open No. 2003-59878 by the present inventors.

  FIG. 1 is a schematic cross-sectional view of a finish grinding portion (corresponding to the BG step 134 in FIG. 8) of the back grinding apparatus used in this embodiment. (A) is sectional drawing in the same figure, (b) is explanatory drawing which looked at the rotary grindstone part of sectional drawing from the bottom. Here, the wafer 1 is fixed to a vacuum suction table 2 made of porous ceramics via a surface protection tape BT1 (adhesive tape) with the back side facing up (other types of wafer stage or wafer chuck may be used). . The spindle motor 103 is substantially the same as the second rotating grindstone 51 (the first rotating grindstone for rough grinding) which is composed of a wheel base 102 and an annular grindstone row 107 (here, the grindstone is referred to as a segment). In the case of a rotating grindstone, such a dressing mechanism is not necessarily required). A dressboard 105 is pressed against the grindstone row 107 by a dressboard vertical mechanism 106 (a sharpening grindstone position / pressure control mechanism). Here, the dressboard 105 (dressing grindstone) can be rotated by the dressboard rotating mechanism 109 even while being pressed, and only the same portion of the dressing grindstone is not worn. . Also, good dress characteristics can be obtained by rotation during dressing.

  FIG. 2 is an enlarged view of a main part of FIG. During the finish grinding, a grinding fluid (usually pure water) is supplied from the wafer grinding fluid nozzle 111 and the dresser grinding fluid nozzle 112 (in addition, the grinding fluid may be used for cooling, cleaning, lubrication, etc.). For example, pure water, pure water-based chemicals, oil-based liquids, etc. can be used.For cleaning purposes, a high-pressure jet or a two-fluid jet containing high-pressure gas is also effective). It is desirable to supply them onto the wafer 1 and the dressing grindstone, respectively (however, it is not excluded to apply directly to the grinding grindstone 107. For example, the grinding liquid or the cleaning liquid is directly applied for a limited time. That may be valid.) Direct contact with the grinding wheel 107 may promote wear of the grinding wheel. The supply of the grinding fluid by the dresser grinding fluid nozzle 112 has an effect of removing undesired grinding waste generated by sharpening before reaching the wafer 1.

  FIG. 3 is a schematic time chart showing details of a finish grinding step and the like which are the main parts of the process of the present embodiment. Taking a 300 mm wafer as an example (hereinafter the same), the wafer 1 is put into rough grinding (roughing original thickness) with a thickness of about 800 μm (thickness of 700 μm or more), for example. For example, if the target final wafer thickness or the wafer finish thickness (chip thickness) is 100 μm (substantially the same as the die thickness in the die bonding process in FIG. 8), it is set to about 135 μm by rough grinding and is put into finish grinding. (Finishing grinding and rough grinding are usually performed on the same wafer chuck or wafer stage, but it may be changed to a different stage in the middle depending on the configuration of the apparatus. This is advantageous when handling wafers). Finish Grinding (Here we explain the industry standard infeed method. That is, with the grinding wheel and wafer rotating together approximately two-dimensionally overlapping, the wheel gradually faces the wafer. Grinding is performed by descending.) Is divided into the following steps. That is, an air cut step in which the finishing grindstone 51 descends toward the back surface of the wafer 1 while rotating, and a main grinding step from the start of grinding until reaching a substantially target thickness after landing (this step is a grinding characteristic) In general, it is often divided into a first cut step having a lowering speed that is substantially the same as the air cutting step, that is, a first cutting step having a relatively lower falling speed, and a second cutting step having a relatively lower lowering speed. After that, the pressure is applied to the surface under a pressure that is substantially weaker than the main grinding step or only the weight of the grindstone 51 or the like. Finally, the wafer rotates while the grindstone rotates. This is an escape step away from 1. This spark-out step is to make the finish close to a mirror surface (quasi-mirror surface). If this is not done, grinding streaks will be noticeable and look slightly cloudy. In addition, stress concentration tends to occur, which is disadvantageous in terms of bending strength. As will be described in detail below, the spark out step is very short compared to the main grinding step.

FIG. 4 is an explanatory diagram showing an example of detailed conditions of the finish grinding process, the setting period as the main part of the present embodiment, and the relationship between the steps. According to the study of the present inventor, scratches are classified into deep scratches (depth 0.5 to 1.5 μm) and shallow scratches (depth less than 0.5 μm). The cause of deep scratches is foreign matter mixed in the grindstone or abrasive grains having a large particle size, and the cause of shallow scratches is silicon pieces or grindstone pieces caught between the wafer back surface and the grindstone during grinding. This embodiment mainly deals with the reduction of shallow scratches. Accordingly, it is considered that the scratch occurs immediately after the end of the main grinding step and immediately after the start of the escape step. In other words, scratches that occurred before the end of the main grinding step disappear with subsequent grinding, and scratches are theoretically generated immediately after the start of the escape step because the back surface of the wafer and the bottom surface of the grindstone are sufficiently separated. It is thought not to. Therefore, it is desirable to include the spark-out step T ₂ , the end or end period T ₁ of the main grinding step before and after the spark-out step T _2, and the start or start period T ₃ of the escape step, as shown in FIG. This is, for example, a spark-out step and about 1 second before and after that (corresponding to a scratch having a depth of 0.2 μm). Also, theoretically, if the chamfering period is extended to 3 seconds before the spark-out step, a completely shallow scratch can be eliminated, but it is generally considered that such a large scratch is a small number of shallow scratches. Therefore, it is considered that both the front and rear margins T ₁ and T ₃ are optimal from less than 3 seconds to about 1 second. However, it goes without saying that a front and rear margin is not always necessary. Here, since the occurrence of scratches is considered to be relatively small at the end of the spark-out step or at the start of the escape step, it can be as shown in FIGS. B, d, e, f, g, h, etc. . In this way, the retreating operation of the rotating grindstone 51 can be performed smoothly. In addition, from the viewpoint of accurately controlling the final target wafer thickness, it is effective to make them as shown in c, d, e, f, g, i, etc. in FIG. In short, it is important that the main part of the spark-out step is a conspicuous period. In the preferred embodiment shown in this figure, the rotational direction of the rotary grindstone 51 for finish grinding and the rotational direction of the wafer 1 are the same (the same applies to rough grinding). However, reverse rotation may be employed. Details will be described later.

  In addition, rough grinding is much faster than finish grinding because of the larger removal amount. In the apparatus described here, it is desirable that roughing and finishing are processed in substantially the same time because of the wafer flow.

  FIG. 5 is a cross-sectional view of the main part of the wafer apparatus during finish grinding (substantially the same during rough grinding) for explaining chipping at the wafer edge, which is one of the causes of scratches. In the figure, the wafer vacuum suction stage 2 is divided into the following three parts. That is, there are a central porous portion 2a made of a relatively coarse porous material in the center, a peripheral porous portion 2b made of a relatively fine porous material in the periphery, and a metal portion 2c serving as a peripheral frame. Here, the central porous portion 2a and the peripheral porous portion 2b are connected to separate vacuum systems, and as a result, air is removed from the peripheral wafer or the portion where the surface protection tape BR1 is not present. Is prevented from being damaged. That is, for this reason, the periphery has a relatively weak adsorption force, and the wafer edge tends to float. Therefore, there is a high possibility that chipping will occur.

  FIG. 6 is a schematic cross-sectional view (at the time of wafer grinding) of a grindstone for finish grinding used in the present embodiment for illustrating a mechanism for generating scratches. In this embodiment, innumerable pores are introduced into a vitrified grindstone having a diamond grain size of about # 8000 (grain size of about 0.2 μm, that is, fine abrasive grains having a particle size of less than 1 μm or less than 0.5 μm). A foam vitrified grinding wheel (that is, a porous vitrified bond diamond wheel) is used. This is because, since the abrasive grains are fine, in a resinoid grindstone generally used for finish grinding, the abrasive grains are buried in a soft resinoid binder. The reason why the pores are introduced is that the contact area with the wafer becomes excessive if it is left as it is, and there is a risk that surface burns may occur. In the figure, diamond abrasive grains 121 are fired together with vitrified bond (vitrified binder) 122 and have innumerable pores 123. However, when the chipping foreign matter 124 or the like is trapped in the pores 123, a scratch 125 is generated as a result.

  FIG. 7 is a top view of the main part for explaining the movement of the wafer 1 in the grinding process chamber R1. In the figure, a wafer 1 is first adsorbed by one of the adsorbing stages 2, and rough grinding is performed by a rough grinding rotary grindstone 102b. Thereafter, the rotary table 25 is rotated as it is, and the wafer 1 comes under the grinding wheel 102a for finish grinding, and finish grinding is performed (some devices are transferred to another suction stage).

  Note that edge trimming reduces the possibility of chipping, but it cannot be completely eliminated. In the DBG process, chipping inside the wafer is an important problem. Therefore, although the number of processes increases, it goes without saying that edge trimming also helps reduce scratches in this embodiment.

  Next, the overall flow of this embodiment will be described with reference to FIG. A surface protection tape is applied to the surface (device surface) of the wafer 1 on which the wafer process 131 has been completed (BG tape attaching process 132). Thereafter, a back grinding process 134 is performed. Next, the wafer 1 is mounted on the frame 6 for dicing via the dicing tape DT1 (wafer mounting step 135). After mounting, the unnecessary BG tape BT1 is peeled off (BG tape peeling step 136). Thereafter, the wafer is diced (dicing step 137), and subsequently sent to the die bonding step 139 through a UV irradiation step 138 for weakening the adhesive strength of the dicing tape DT1.

  Next, each step after forming a crushed layer on the back surface of the semiconductor wafer 1 by back grinding will be described in order.

  After the semiconductor wafer 1 is cleaned and dried, the semiconductor wafer 1 is replaced with a dicing tape DT1 as shown in FIG. First, the semiconductor wafer 1 is vacuum-sucked by the wafer transfer jig and transferred to the wafer mount apparatus as it is. The semiconductor wafer 1 transported to the wafer mount apparatus is sent to the alignment unit to perform notch or orientation flat alignment, and then the semiconductor wafer 1 is sent to the wafer mount unit for wafer mounting. In the wafer mount, an annular frame 6 to which a dicing tape DT1 is attached in advance is prepared, and the semiconductor wafer 1 is attached to the dicing tape DT1 with its circuit forming surface as an upper surface. The dicing tape DT1 is made of, for example, polyolefin as a base material, coated with an acrylic UV curable adhesive, and a release material made of polyester is further bonded thereon. The release material is, for example, a release paper. The release material is peeled off, and the dicing tape DT1 is attached to the semiconductor wafer 1. The thickness of the dicing tape DT1 is, for example, 90 μm, and the adhesive strength is, for example, 200 g / 25 mm before UV irradiation, and 10 to 20 g / 25 mm after UV irradiation. Note that there may be used a dicing tape having no release material and having the back surface of the substrate removed.

  Next, the frame 6 on which the semiconductor wafer 1 is mounted is sent to the adhesive tape peeling portion. Here, the adhesive tape BT1 (surface protective tape or BG tape) is peeled from the semiconductor wafer 1. The reason why the semiconductor wafer 1 is re-attached to the frame 6 in this manner is that dicing is performed with reference to the alignment mark formed on the circuit forming surface of the semiconductor wafer 1 in a later dicing step, and therefore the circuit in which the alignment mark is formed. The formation surface must be the upper surface. Even if the adhesive tape BT1 is peeled off, since the semiconductor wafer 1 is fixed via the dicing tape DT1 attached to the frame 6, the warp of the semiconductor wafer 1 does not surface.

  Next, as shown in FIG. 10, the semiconductor wafer 1 is diced. Although the semiconductor wafer 1 is divided into chips SC1, each chip SC1 is fixed to the frame 6 via the dicing tape DT1 even after being divided into individual pieces, and thus the aligned state is maintained. First, the semiconductor wafer 1 is vacuum-sucked on the circuit forming surface of the semiconductor wafer 1 by a wafer transfer jig, transferred to the dicing apparatus as it is, and placed on the dicing table 7. Subsequently, the semiconductor wafer 1 is cut vertically and horizontally along the scribe line by using an ultrathin circular blade 8 to which diamond fine particles called diamond saw are attached (a method using a laser is used to divide the wafer). In that case, there is an additional merit such as making the cutting width minute).

  Next, as shown in FIG. 11, the semiconductor wafer 1 is irradiated with UV. By irradiating UV from the back side of the dicing tape DT1, the adhesive force of the surface in contact with each chip SC1 of the dicing tape DT1 is reduced to, for example, about 10 to 20 g / 25 mm. Thereby, each chip SC1 is easily peeled off from the dicing tape DT1.

  Next, as shown in FIG. 12, the chip SC1 determined to be non-defective in the wafer test process is picked up. First, the back surface of the chip SC1 is pressed by the push-up pin 9 through the dicing tape DT1, thereby peeling the chip SC1 from the dicing tape DT1. Subsequently, the collet 10 is moved to be positioned at the upper part facing the push-up pin 9, and the chip SC1 is peeled off from the dicing tape DT1 one by one by vacuum-adsorbing the circuit forming surface of the peeled chip SC1 with the collet 10. Pick up. Since the adhesive force between the dicing tape DT1 and the chip SC1 is weakened by UV irradiation, even the chip SC1 that is thin and has a reduced strength can be reliably picked up. The collet 10 has, for example, a substantially cylindrical outer shape, and the adsorbing portion located at the bottom thereof is made of, for example, soft synthetic rubber.

  Next, as shown in FIG. 13, the first stage chip SC <b> 1 is mounted on the substrate 11. First, the picked-up chip SC1 is attracted and held by the collet 10, and is transported to a predetermined position on the substrate 11 (for example, an organic substrate having a single layer or multilayer wiring structure). Subsequently, the paste material 12 is placed on the plated island (chip mounting region) of the substrate 11, the chip SC1 is lightly pressed thereon, and a curing process is performed at a temperature of about 100 to 200 ° C. Thus, the chip SC1 is attached to the substrate 11. The paste material 12 can be exemplified by an epoxy resin, a polyimide resin, an acrylic resin, or a silicone resin. In addition to pasting with the paste material 12, the back surface of the chip SC1 is lightly rubbed against the plated island, or a small piece of gold tape is sandwiched between the plated island and the chip SC1 to form a eutectic of gold and silicon. It may be made and glued. In addition, a film adhesive such as DAF (Die Attach Film) or a double-sided adhesive member film may be attached to the back surface of the wafer 1 in advance before dicing, thereby increasing the mounting efficiency.

  When the die bonding of the non-defective chips attached to the dicing tape DT1 and the removal of the defective chips are completed, the dicing tape DT1 is peeled off from the frame 6, and the frame 6 is recycled.

Next, as shown in FIG. 14, a chip SC2 is prepared in the same manner as the chip SC1, and the second-stage chip SC2 is bonded onto the first-stage chip SC1 using, for example, an insulating paste 13a. Subsequently, the chip SC3 is prepared in the same manner as the chip SC1, and the chips SC1 and SC2 and the chips SC1, SC2 and the second stage SC2 are joined to the second stage SC2 by using the insulating paste 13b, for example. Stack SC3. The first-stage chip SC1 is, for example, a microcomputer, and the second-stage chip SC2 is, for example, an electrical batch erase type EEPROM (Elec
(tric Erasable Programmable Read Only Memory) The third-stage chip SC3 can be exemplified by an SRAM, for example. A plurality of electrode pads 14 are provided on the front surface of the substrate 11, and a plurality of connection pads 15 are provided on the back surface, and both are electrically connected by wiring 16 in the substrate.

Next, as shown in FIG. 15, the bonding pads arranged on the edge of the surface of each chip SC <b> 1, SC <b> 2 or SC <b> 3 and the electrode pad 14 on the surface of the substrate 11 are connected using bonding wires 17. The operation is automated and is performed using a bonding apparatus. In the bonding apparatus, the arrangement information of the bonding pads of the laminated chips SC1, SC2 and SC3 and the electrode pads 14 on the surface of the substrate 11 is inputted in advance, and the laminated chips SC1, SC2 and SC3 mounted on the substrate 11 The relative positional relationship between the bonding pads on the surface and the electrode pads 14 on the surface of the substrate 11 is captured as an image, data processing is performed, and the bonding wires 17 are accurately connected. At this time, the loop shape of the bonding wire 17 is controlled to rise so as not to touch the peripheral portions of the laminated chips SC1, SC2, and SC3.

  Next, as shown in FIG. 16, the substrate 11 to which the bonding wires 17 are connected is set in a mold molding machine, and the liquefied resin 18 is pumped and poured to increase the temperature, and the laminated chips SC1, SC2, and SC3 are inserted. Enclose and mold. Subsequently, unnecessary resin 18 or burrs are removed.

  Next, as shown in FIG. 17, for example, after supplying bumps 19 made of solder to the connection pads 15 on the back surface of the substrate 11, a reflow process is performed to melt the bumps 19 and connect the bumps 19 and the connection pads 15. To do.

  Thereafter, as shown in FIG. 18, a product name or the like is imprinted on the resin 18, and the laminated chips SC1, SC2, and SC3 are separated from the substrate 11 one by one. Thereafter, the finished product made up of each of the laminated chips SC1, SC2 and SC3 is selected according to the product standard, and the product is completed through an inspection process.

  Next, an example of continuous processing from back grinding to wafer mounting will be described with reference to an explanatory diagram of an integrated processing apparatus shown in FIG.

  An integrated processing apparatus BGM1 shown in FIG. 19 includes a back grinder unit, a cleaning unit, and a wafer mount unit. Each part includes a loader 20 for loading the semiconductor wafer 1 and an unloader 21 for unloading the semiconductor wafer 1, and each part can also be used as a stand-alone. Further, a transfer robot 22 for transferring the semiconductor wafer 1 is provided between the back grinder unit and the cleaning unit. Similarly, between the cleaning unit and the wafer mount unit, a semiconductor wafer is provided between the two. 1 is provided.

First, a hoop having a plurality of semiconductor wafers 1 mounted thereon is placed on the loader 20 of the back grinder unit, and then one semiconductor wafer 1 is taken out from the hoop by the transfer robot 24 and loaded into the processing chamber R1 of the back grinder unit. . The hoop is a hermetically sealed container for batch transfer of the semiconductor wafers 1 and normally stores the semiconductor wafers 1 in batch units such as 25 sheets, 12 sheets, and 6 sheets. The outer wall of the container of the hoop has a secret structure except for a fine ventilation filter portion, and dust is almost completely eliminated. Therefore, even if transported in a class 1000 atmosphere, the inside can maintain a class 1 cleanliness. Docking with the device is performed in a state in which the robot on the device side keeps the cleanness by drawing the hoop door into the device.

  Next, after the semiconductor wafer 1 is placed on the suction stage 2 (for example, one of four) on the rotary table 25 and vacuum-sucked, the semiconductor wafer 1 is used by using a first abrasive (first rotary grindstone). 1 is rough ground to reduce the thickness of the semiconductor wafer 1 to a predetermined thickness (first thickness). Subsequently, the back surface of the semiconductor wafer 1 is finish-ground using a second abrasive (second rotating grindstone), and the thickness of the semiconductor wafer 1 is reduced to a predetermined thickness (second thickness). Let

Next, when the back grinder of the semiconductor wafer 1 is finished, the semiconductor wafer 1 is unloaded from the back grinder section by the transfer robot 22 and transferred to the cleaning section, and the semiconductor robot 1 is further transferred to the processing chamber of the cleaning apparatus by the transfer robot 26. The wafer is carried into R2, and the semiconductor wafer 1 is cleaned and dried with pure water. Subsequently, the semiconductor wafer 1 is unloaded from the cleaning unit by the transfer robot 23 and transferred to the wafer mount unit. After the vacuum suction of the back surface of the semiconductor wafer 1 is performed by the transfer robot 27, the vacuum suction surface of the semiconductor wafer 1 is changed. Then, vacuum suction is applied to the circuit forming surface. Subsequently, the semiconductor wafer 1 is carried into the processing chamber R3 of the wafer mount unit. Here, after adhering the semiconductor wafer 1 to the dicing tape fixed and attached to the annular frame with the circuit forming surface as the upper surface, the semiconductor wafer 1 is attached to the dicing tape with the circuit forming surface as the upper surface, The adhesive tape BT1 is peeled off. Thereafter, the semiconductor wafer 1 is transferred to the unloader 21 of the wafer mount unit, and the semiconductor wafer 1 is taken out from the wafer mount unit and returned to the hoop again.

  Thus, by using the integrated processing apparatus BGM1, the semiconductor wafer 1 can be processed from the back grind to the wafer mount in a short time.

Next, the relationship between the crystallographic structure of the back surface of the wafer 1 and the die strength of the device chip will be described with reference to FIGS. As shown in FIG. 20, in the finish grinding, an atomic level strained layer and a fractured layer (amorphous layer 5a / polycrystalline layer 5b / microcrack layer 5c) 5 are formed on the pure crystal layer on the back surface of the semiconductor wafer 1. The thickness of the atomic level strained layer and the fracture layer 5 is formed thinner than the thickness of the atomic level strained layer and the fractured layer after rough grinding, respectively (in the grinding process using the abrasive having fixed abrasive grains, The abrasive grains are fixed, and mechanical force is applied to the surface to be ground of the semiconductor wafer, so that a crushing layer is formed on the surface to be ground of the semiconductor wafer. In addition to removing damage and forming a lower gettering layer such as a crushing layer with an appropriate thickness, the wafer thickness is adjusted to the purpose). When a pure crystal layer (pure silicon crystal structure portion) is exposed on the back surface of the semiconductor wafer 1 (when a finish search is performed with a grindstone having an extremely fine grain size, dry polishing, deep etching, etc.), the semiconductor wafer 1 When contaminants such as heavy metal impurities adhere to the back surface of the semiconductor wafer, the contaminants easily enter the semiconductor wafer 1. Contaminating impurities that have entered the semiconductor wafer 1 diffuse in the semiconductor wafer 1 and reach the circuit formation surface (device surface) of the semiconductor wafer 1, causing a problem in the characteristics of the semiconductor elements formed on the circuit formation surface. Therefore, in this embodiment, the crushed layer 5 is left on the back surface of the semiconductor wafer 1 so that the contaminating impurities are captured by the crushed layer 5. Thereby, infiltration and diffusion of contaminating impurities to the semiconductor wafer 1 can be suppressed. Among the heavy metals, Cu has a diffusion coefficient of 6.8 × 10 ⁻² / sec (at 150 ° C.) and other heavy metals (for example, the diffusion coefficient of Fe is 2.8 × 10 ⁻¹³ / sec (at It is considered to be one of the main contaminating impurities that cause defective characteristics of the semiconductor element. Examples of the Cu intrusion source include an adhesive layer of a dicing tape and an adhesive layer used for die bonding. In these adhesive layers, a small amount of Cu may be mixed together with various impurities and foreign substances (fillers), and since these adhesive layers are in direct contact with the back surface of the semiconductor wafer 1 or the chip, the intrusion of Cu. Is easy.

  By the way, as shown in FIG. 21, for example, the min value of the chip bending strength becomes smaller as the finished roughness of the back surface of the semiconductor wafer 1 becomes smaller, that is, the number of abrasive grains (see, for example, Japanese Industrial Standards JIS R6001). When the back surface of the semiconductor wafer 1 is mirror-finished by, for example, dry polishing, the min value of the chip bending strength becomes the maximum value. As shown in FIG. 22, as the number of abrasive grains of the abrasive increases, the particle size of the grindstone attached to the abrasive decreases, and the roughness of the back surface (finished surface) of the semiconductor wafer 1 decreases. By becoming. Furthermore, as shown in FIG. 23, the roughness of the finished surface is reduced, so that the thickness of the crushing layer is reduced, which leads to an improvement in the bending strength of the chip. However, the gettering effect decreases as the thickness of the crushing layer having the gettering effect decreases. For example, when the back surface of the semiconductor wafer 1 is mirror-finished by dry polishing, the gettering effect is lost. Contaminating impurities enter from the back surface of the semiconductor wafer and diffuse to the circuit forming surface of the semiconductor wafer 1 to cause a characteristic defect of the semiconductor element. For this reason, in the finish grinding using the second grinding material (second rotating grindstone), the thickness and finished roughness of the crushing layer 5 capable of achieving both the die bending strength and the gettering effect to some extent are selected. It is necessary to.

  Based on these facts, the thickness of the crushed layer 5 is, for example, less than 0.5 μm (that is, a relatively thicker layer is advantageous in order to ensure the bending strength of the chip). Conceivable (of course not limited to this range depending on other conditions). Moreover, the range suitable for mass production is considered to be less than 0.3 μm, but is further less than 0.1 μm (because there is no problem if it is not less than the lower limit value that can prevent the entry and diffusion of contaminating impurities). Most suitable. Here, the thickness of the crushed layer 5 is, for example, measured by measuring the thickness of the crushed layer 5 at a plurality of locations (for example, 5 points or 10 points) in the semiconductor wafer 1 using a film thickness meter. For example, the average thickness (for example, d1 shown in FIG. 20) obtained from the average value of 5 points or 10 points).

Further, the finished roughness of the crushed layer 5 (for example, the maximum amplitude of the surface of the crushed layer 5) is considered to be an appropriate range, for example, less than 0.1 μm. Further, a range suitable for mass production is considered to be less than 0.05 μm, but a range less than 0.01 μm is considered most preferable. Here, the finished roughness of the crushed layer 5 is the maximum amplitude (for example, in FIG. 20) of the surface of the crushed layer 5 at a plurality of locations (for example, 5 points or 10 points) in the semiconductor wafer 1 using, for example, a surface roughness meter. This is the average roughness obtained by measuring the indicated r1) and calculating from the average value of a plurality of locations (for example, 5 points or 10 points). The finished roughness by dry polishing is approximately equivalent to 0.0001 μm, for example.

  Thus, the thickness of the semiconductor wafer 1 is ground to, for example, less than 100 μm, less than 80 μm, or less than 60 μm by the back grinding, and a relatively thin crush layer 5 on the back surface of the semiconductor wafer 1, for example, less than 0.5 μm. By forming the crushing layer 5 having a thickness of less than 0.3 μm or less than 0.1 μm, it is possible to prevent contamination impurities from entering from the back surface of the semiconductor wafer 1 at the same time without reducing the bending strength of the chip, It is possible to prevent a semiconductor device from being deteriorated in characteristics due to contamination impurities. Thereby, the fall of the manufacture yield of a semiconductor product can be suppressed. In addition, since a process that greatly differs in the back grinding is not added, the process of the back grinding process can be simplified. That is, in this embodiment, by using a grindstone (for example, about # 8000) finer than usual (for example, about # 8000), stress relief for removing damage due to rough grinding and finish grinding to a target thickness are performed. Can be implemented in a single process. In short, it is important that the chip back surface when mounted on an organic substrate or another chip substantially maintains the crushed layer remaining when finish grinding.

  Next, in FIG. 24, an example of the dressing grindstone 105 of this embodiment will be described. The dressing grindstone 105 is preferably a non-foamed vitrified grindstone as shown in the figure in combination with the foamed vitrified grindstone. This is because a dressing grindstone is relatively required to have hardness as a structure. In this case, it is desirable that the diameter of the diamond abrasive grains 121 is smaller than the diameter of the grinding stone 51 for grinding. The hardness of the vitrified binder 122 is desirably larger than the hardness of the grinding wheel 51 for grinding. For example, if rough grinding is performed using a grindstone having an abrasive grain size of about # 300 to # 400 (generally about # 100 to # 700 is applicable), finish grinding is performed with an abrasive grain size of # 5000 to # 20000. For example, when a # 8000 grindstone is used for finish grinding, the dressing grindstone is slightly increased to a number # 10000 (average of abrasive grains). A smaller particle size is desirable. This is presumably because the action of dressing is significant in that the abrasive on the surface of the grinding wheel is scraped to produce new abrasive grains. However, the relationship between the particle size and the hardness of the binder is merely an example, and the present invention is not limited to this. In short, any dresser may be used as long as it operates as described above. Therefore, it is possible to use not only a dresser similar to a grindstone but also a dresser tool used for sharpening a normal grinder, or a member similar to an object to be ground such as a silicon member.

  Next, the relationship among the rotating grindstone 51, the wafer 1, and the dresser 105 at the time of finish grinding according to the present embodiment will be described with reference to FIG. In the figure, (a) is outer / inner grinding (or inward grinding), which is usually used in this embodiment. Outside / inner grinding is stable in terms of process, and as a result of the grinding wheel being rubbed at the end of the wafer 1, a sharpening effect is expected, but there is a drawback that chipping is likely to occur. On the other hand, (b) is internal / external grinding (or outward grinding), and this method is effective from the viewpoint of preventing entrainment of chipping. In these systems, the axes of the wafer 1 and the rotating grindstone 51 are slightly shifted so that the grinding wheel comes into contact with the main grinding portion 141 (in general, the wafer suction table 2 is exaggerated in FIG. Since the center has a high fine inclination, the entire rotating grindstone 51 on the wafer is not in contact with the wafer 51). In these, the position of the dresser 105 (105a, 105b, 105c) can be any position from a to c, but the position of a is optimal from the viewpoint of the space margin. The position b has an advantage that sharpening and cleaning can be performed immediately after grinding. Further, at the position c, there is an advantage that sharpening and cleaning can be performed immediately before grinding. If a jet nozzle or a two-fluid jet nozzle directed to the grinding wheel is arranged at the same position that does not overlap with the dresser, and cleaning water or cleaning liquid is supplied during the dressing process, there is a foreign matter removing effect. At this time, it is effective to arrange such that the sharpened grindstone segments grind the wafer after passing through the position of the nozzle. The rotation direction of the wafer 1 at the time of grinding is generally the same as the rotation of the rotating grindstone 51 in the in-feed backside grinding (In-Feed Grinding) in this embodiment from the viewpoint of process stability. Note that reverse rotation is also possible.

  The reverse rotation method has the effect of canceling the grinding stripes (Saw Mark) or grinding marks (Saw Mark) formed during rough grinding, and also has the effect of preventing chipping in the inner region of the wafer 1. Therefore, it is effective when applied to a so-called DBG (Dicing Before Grinding) process (the difference from the above example is shown in FIGS. 27 to 30. The steps before the pre-process 131 and the UV irradiation 138 and after in FIG. 8 are almost the same). . That is, the wafer is first diced from the surface by a half-cut method (FIG. 27), and then the surface protection tape BT1 is stretched on the surface of the wafer 1 (the start point of rough grinding is shown in FIG. 28). In accordance with the present embodiment, the back grinding process is executed, and the wafer is separated into each chip area in the process (the time just before finish grinding is shown in FIG. 29). In that state, each chip area separated by the surface protection tape BT1 is held. Thereafter, with the surface protection tape BT1 attached, the frame 6 shown in FIG. 9 is mounted in the same manner as in the present embodiment (FIG. 30). In this state, since each chip region has already been separated, after the surface protection tape BT1 is peeled off, the process may proceed to the UV irradiation step 138 in FIG. By doing so, chips can be cut out from a large-diameter wafer while minimizing chipping on the back surface and wafer damage during dicing. In this case, the rotational directions of the rotating grindstone 51 and the wafer 1 are generally the same from the viewpoint of process stability, but reverse rotation is also possible. In addition, outer / inner grinding is applied to the grinding position on the wafer from the viewpoint of process stability, but inner / outer grinding is also advantageous from the viewpoint of chipping and the like.

  In this embodiment, in rough grinding, the rotation direction of the wafer 1 during grinding is generally the same direction as the rotation of the rotating grindstone 51 in terms of process stability and the like. However, it goes without saying that reverse rotation is also possible.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the above-described specific example, a vitrified bond-based finish grinding wheel has been described as an example, but the present invention has been described in detail. Needless to say, the present invention can be applied to a process using a medium (including an intermediate one) (because a scratch caused by entrainment of chipping occurs regardless of the presence or absence of pores). Further, the vitrified bond-based grindstone having pores may be one obtained by sintering (including one formed at a low temperature) one obtained by coating a binder around the abrasive grains, or by using a foaming agent. What formed the void | hole or the hole (pore by a bubble) may be used.

1 is a side cross-sectional view of a finished back grinding portion of a back grinding apparatus used in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. It is a principal part enlarged view of the cross section of FIG. It is detailed explanatory drawing of the finish back grinding process of the back grinding process in the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is grinding condition detailed explanatory drawing of the finish back grinding process of the back grinding process in the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is a schematic cross section for demonstrating the cross section in the grinding | polishing of the back surface grinding process of the back grinding process in the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. FIG. 5 is a schematic cross-sectional view for explaining the generation of scratches by enlarging a cross section during grinding in a back grinding process of the back grinding process in the method for manufacturing a semiconductor integrated circuit device of one embodiment of the present invention. It is a top view which shows the grinding part of the back grinding process in the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is a whole flowchart which shows the whole flow of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is sectional drawing which shows the mounting process of the wafer to the dicing frame of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is sectional drawing which shows the dicing process of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is sectional drawing which shows the UV irradiation process of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is sectional drawing which shows the chip pick-up process of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is sectional drawing which shows the die-bonding process of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is sectional drawing which shows the mounting process to the board | substrate of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is sectional drawing which shows the wire bonding process between the electrode on a board | substrate and the pad on a chip | tip of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is sectional drawing which shows the sealing process of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is sectional drawing which shows the bump formation process of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is sectional drawing which shows the device isolation | separation process of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. 1 is a top view of an integrated backgrinding / cleaning / wafer mount apparatus used in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG. It is sectional drawing for demonstrating the crystal state of the wafer back surface vicinity at the time of completion | finish of the finishing back surface grinding process of the back grinding process in the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is a test result plot figure which shows the relationship between the roughness of the final finish of a chip | tip back surface, and the bending strength of a chip | tip. It is a test result plot figure which shows the relationship between the particle size of the abrasive grain of the grindstone for finishing back grinding of a back grinding process, and the roughness of a finished surface. It is a test result plot figure which shows the relationship between the particle size of the grindstone of the grindstone for finishing back grinding of a back grinding process, and the thickness of the crushing layer of a finishing surface. FIG. 3 is an enlarged cross-sectional view of a fine structure of a dresser grindstone used in a finishing back grinding step of a back grinding step in the method for manufacturing a semiconductor integrated circuit device of one embodiment of the present invention. It is a model top view for demonstrating the detail of the grinding | polishing of the back grinding process of the back grinding process in the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is a side pseudo sectional view for explaining the details of grinding in the finish back grinding process of the back grinding process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present invention. It is a schematic cross section of the dicing process of the partial process modification of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is a schematic cross section of the rough grinding process of the partial process modification of the manufacturing method of the semiconductor integrated circuit device of one Embodiment of this invention. It is a schematic cross section of the finish grinding process of the partial process modification of the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present invention. It is a schematic cross section of the wafer mounting process for chip pickup of the partial process modification of the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer 2 Wafer chuck 51 Rotary grindstone 102 Wheel base 103 Spindle motor 105 Grinding wheel for sharpening 106 Grinding wheel vertical mechanism for sharpening 107 Grinding stone segment

Claims (20)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A step of attaching a surface protection tape to the first main surface of the wafer on which the device is formed;
(B) a step of vacuum-sucking the first main surface side of the wafer on which the surface protection tape is attached to a first wafer stage of a grinding apparatus;
(C) In a state where the first wafer stage is vacuum-sucked, the second main surface of the wafer is roughly ground by a first rotating grindstone, thereby reducing the thickness of the wafer to the first thickness. Grinding to a thickness;
(D) After the step (c), the second main surface of the wafer is moved from the first rotating grindstone while being vacuum-sucked to the first wafer stage or the second wafer stage. A step of grinding the thickness of the wafer to a second thickness smaller than the first thickness by finish grinding with a second rotating grindstone having a small abrasive grain size,
Here, the finish grinding step of step (d) includes the following sub-steps:
(I) a step of landing the second rotating grindstone on the second main surface of the wafer;
(Ii) grinding the second main surface of the wafer under a first pressure in a state where the second rotating grindstone and the second main surface of the wafer are in contact with each other;
(Iii) Subsequent to the step (ii), in a state where the second rotating grindstone and the second main surface of the wafer are in contact with each other, under a second pressure lighter than the first pressure, Grinding the second main surface of the wafer;
(Iv) Following the step (iii), a step of separating the second rotating grindstone from the second main surface of the wafer;
Here, during the partial period of the finish grinding process, while the sub-process (iii) is performed, the setting grindstone is pressed against the second rotating grindstone.   In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the sharpening period in which the sharpening grindstone is pressed includes the entire period in which the sub-process (iii) is performed.   In the method of manufacturing a semiconductor integrated circuit device according to the item 2, the sharpening period in which the sharpening grindstone is pressed includes the entire period in which the lower step (iii) is performed, and beyond that, the lower step (ii) ) Extends to the end of the period.   In the method of manufacturing a semiconductor integrated circuit device according to the item 3, the sharpening period in which the sharpening grindstone is pressed includes the entire period in which the sub-process (iii) is performed, and beyond that, the sub-process (iv) ) Spans the period that begins.   In the manufacturing method of the semiconductor integrated circuit device according to the item 1, the dressing period in which the dressing grindstone is pressed does not include the time of disclosure or the end of the entire period in which the sub-process (iii) is performed.   In the manufacturing method of the semiconductor integrated circuit device according to the item 1, the dressing period in which the sharpening grindstone is pressed does not include the time of disclosure and the end of the entire period in which the substep (iii) is performed.   In the method for manufacturing a semiconductor integrated circuit device according to the item 2, the sharpening grindstone is held in a movable manner.   8. The manufacturing method of a semiconductor integrated circuit device according to the item 7, wherein the hardness of the binder of the sharpening grindstone is higher than the hardness of the binder of the second rotating grindstone.   In the method for manufacturing a semiconductor integrated circuit device according to the item 8, the abrasive grain size of the sharpening grindstone is smaller than the grain size of the abrasive grain of the second rotating grindstone.   In the method for manufacturing a semiconductor integrated circuit device according to the item 1, grinding fluid or grinding water is supplied to the sharpening grindstone during the sharpening period. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A step of attaching a surface protection tape to the first main surface of the wafer on which the device is formed;
(B) a step of vacuum-sucking the first main surface side of the wafer on which the surface protection tape is attached to a first wafer stage of a grinding apparatus;
(C) In a state where the first wafer stage is vacuum-sucked, the second main surface of the wafer is roughly ground by a first rotating grindstone, thereby reducing the thickness of the wafer to the first thickness. Grinding to a thickness;
(D) After the step (c), the second main surface of the wafer is moved from the first rotating grindstone while being vacuum-sucked to the first wafer stage or the second wafer stage. A step of grinding the thickness of the wafer to a second thickness smaller than the first thickness by finish grinding with a second rotating grindstone having a small abrasive grain size,
Here, the finish grinding step of step (d) includes the following sub-steps:
(I) a step of landing the second rotating grindstone on the second main surface of the wafer;
(Ii) grinding the second main surface of the wafer under a first pressure in a state where the second rotating grindstone and the second main surface of the wafer are in contact with each other;
(Iii) Subsequent to the step (ii), in a state where the second rotating grindstone and the second main surface of the wafer are in contact with each other, under a second pressure lighter than the first pressure, Grinding the second main surface of the wafer;
(Iv) Following the step (iii), a step of separating the second rotating grindstone from the second main surface of the wafer;
Here, it is a partial period of the finish grinding process, and while the sub-process (iii) is performed, a sharpening grindstone is pressed against the second rotating grindstone, and the partial period In the finish grinding process other than the above, the sharpening grindstone is not pressed.   12. In the manufacturing method of a semiconductor integrated circuit device according to the item 11, the dressing period in which the dressing grindstone is pressed includes the entire period in which the sub-process (iii) is performed.   12. In the method of manufacturing a semiconductor integrated circuit device according to the item 12, the sharpening period in which the sharpening grindstone is pressed includes the entire period in which the lower step (iii) is performed, and beyond that, the lower step (ii) ) Extends to the end of the period.   14. In the method of manufacturing a semiconductor integrated circuit device according to the item 13, the sharpening period in which the sharpening grindstone is pressed includes the entire period in which the lower step (iii) is performed, and further beyond that, the lower step (iv) ) Spans the period that begins.   12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the dressing period in which the dressing grindstone is pressed does not include the time of disclosure or the end of the entire period in which the sub-process (iii) is performed.   12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the dressing period in which the dressing grindstone is pressed does not include the time of disclosure and the end of the entire period in which the substep (iii) is performed.   In the method of manufacturing a semiconductor integrated circuit device according to the item 12, the sharpening grindstone is held in a movable manner.   In the method of manufacturing a semiconductor integrated circuit device according to the item 17, the hardness of the binder of the sharpening grindstone is higher than the hardness of the binder of the second rotating grindstone.   In the method of manufacturing a semiconductor integrated circuit device according to the item 18, the grain size of the sharpening grindstone is smaller than the grain size of the abrasive grain of the second rotating grindstone.   12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, grinding fluid or grinding water is supplied to the sharpening grindstone during the sharpening period.

Images