JP2008277595A - Semiconductor device, and manufacturing method thereof - Google Patents

Semiconductor device, and manufacturing method thereof Download PDF

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Publication number
JP2008277595A
JP2008277595A JP2007120434A JP2007120434A JP2008277595A JP 2008277595 A JP2008277595 A JP 2008277595A JP 2007120434 A JP2007120434 A JP 2007120434A JP 2007120434 A JP2007120434 A JP 2007120434A JP 2008277595 A JP2008277595 A JP 2008277595A
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Japan
Prior art keywords
circuit board
semiconductor device
electrode
semiconductor element
substrate
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JP2007120434A
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Japanese (ja)
Inventor
Shigeru Nonoyama
茂 野々山
Toshitaka Akaboshi
年隆 赤星
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2007120434A priority Critical patent/JP2008277595A/en
Publication of JP2008277595A publication Critical patent/JP2008277595A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing the contact of bonding wires with each other even when the number of surface electrodes on a semiconductor element substantially increases in association with the microfabrication of a diffusion process and the function advancement of the semiconductor element. <P>SOLUTION: The semiconductor device is provided with a circuit board 1, the semiconductor element loaded on the element loading surface of the circuit board, an electrode disposed on the semiconductor element, an electrode disposed on the circuit board corresponding to the electrode of the semiconductor element, and a metal wire electrically connecting the electrode of the semiconductor element and the electrode of the circuit board. On the circuit board 1, an insulating projection part 12 for supporting the bonding wire 9 is formed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置およびその半導体装置の製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

従来より、半導体素子上の表面電極と回路基板上の表面電極とをボンディングワイヤにより電気的に接続したＢＧＡ（ボール・グリッド・アレイ）型半導体装置が知られている（例えば、特許文献１参照。）。従来のＢＧＡ型半導体装置について、図５を用いて説明する。   Conventionally, a BGA (ball grid array) type semiconductor device in which a surface electrode on a semiconductor element and a surface electrode on a circuit board are electrically connected by a bonding wire is known (for example, see Patent Document 1). ). A conventional BGA type semiconductor device will be described with reference to FIG.

図５は従来のＢＧＡ型半導体装置の構造を示す模式図であり、図５（ａ）は平面図、図５（ｂ）は図５（ａ）のＡ−Ａ’間の断面図である。図５において、回路基板１は、ポリイミド樹脂等からなる有機基板、或いは窒化アルミニウム（ＡｌＮ）等からなるセラミック基板などから形成されている。   5A and 5B are schematic views showing the structure of a conventional BGA type semiconductor device. FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along line A-A 'in FIG. In FIG. 5, the circuit board 1 is formed of an organic substrate made of polyimide resin or the like, or a ceramic substrate made of aluminum nitride (AlN) or the like.

また、回路基板１の上側面には、四辺からなる回路基板１の各辺に沿って表面電極２が複数列（ここでは２列）配置されている。また、回路基板１の上側面には、半導体素子を搭載する素子搭載面（回路基板１の中央部）を囲むリング状の電源リング３が、表面電極２よりも内側に配置されている。電源リング３は、半導体素子へ電源あるいは接地電源を供給するための電極である。また、回路基板１の下側面には、格子状に裏面電極４が配置されている。これらの表面電極２、電源リング３、裏面電極４は、回路基板１の両面に形成されている銅（Ｃｕ）等からなる導体パターン（図示せず）の一部にめっきを施すことで形成される。また、回路基板１の両面は、導体パターンを外部環境から保護するために、半導体素子が搭載される領域（素子搭載面）、表面電極２、電源リング３、裏面電極４が形成されている領域を除く領域がソルダレジスト５で被覆されている。   On the upper side of the circuit board 1, a plurality of rows (here, two rows) of surface electrodes 2 are arranged along each side of the circuit board 1 having four sides. Further, on the upper side surface of the circuit board 1, a ring-shaped power supply ring 3 surrounding an element mounting surface (a central portion of the circuit board 1) on which a semiconductor element is mounted is disposed inside the surface electrode 2. The power ring 3 is an electrode for supplying power or ground power to the semiconductor element. Further, on the lower surface of the circuit board 1, back electrodes 4 are arranged in a lattice pattern. The front surface electrode 2, the power supply ring 3, and the back surface electrode 4 are formed by plating a part of a conductor pattern (not shown) made of copper (Cu) or the like formed on both surfaces of the circuit board 1. The In addition, on both sides of the circuit board 1, a region where a semiconductor element is mounted (element mounting surface), a surface electrode 2, a power supply ring 3, and a back electrode 4 are formed in order to protect the conductor pattern from the external environment. The area except for is covered with the solder resist 5.

また、図示しないが、回路基板１の内部には銅（Ｃｕ）等からなる導体パターン、およびビアが形成されており、その導体パターンとビアにより、上側面に形成されている表面電極２および電源リング３と下側面に形成されている裏面電極４とが電気的に接続されている。   Although not shown, a conductor pattern made of copper (Cu) or the like and a via are formed inside the circuit board 1, and the surface electrode 2 and the power source formed on the upper surface by the conductor pattern and the via. The ring 3 and the back electrode 4 formed on the lower surface are electrically connected.

半導体素子６は、回路基板１の上側面の中央部（素子搭載面）に接着剤７により接着されている。また、半導体素子６の上側面には、四辺からなる半導体素子６の各辺に沿って表面電極８が複数列（ここでは２列）配置されている。また、半導体素子６上の表面電極８と回路基板１上の表面電極２および電源リング３とが金（Ａｕ）などの金属性のボンディングワイヤ９により電気的に接続されている。また、上下間で隣接するボンディングワイヤ同士の接触を避けるために、基板中央部側に接続するボンディングワイヤ９よりも基板外周部側に接続するボンディングワイヤ９のループ高さを高く設定している。   The semiconductor element 6 is bonded to the central portion (element mounting surface) of the upper side surface of the circuit board 1 with an adhesive 7. In addition, on the upper surface of the semiconductor element 6, a plurality of rows (here, two rows) of surface electrodes 8 are arranged along each side of the semiconductor element 6 having four sides. Further, the surface electrode 8 on the semiconductor element 6, the surface electrode 2 on the circuit board 1, and the power supply ring 3 are electrically connected by a metallic bonding wire 9 such as gold (Au). Further, in order to avoid contact between adjacent bonding wires between the upper and lower sides, the loop height of the bonding wire 9 connected to the substrate outer peripheral portion side is set higher than the bonding wire 9 connected to the substrate central portion side.

また、回路基板１の上側面は、半導体素子６およびボンディングワイヤ９を外部環境から保護するために、エポキシ樹脂等からなる封止樹脂体１０により被覆されている。また、回路基板１の下側面に形成されている裏面電極４上には、半田ボール等の外部電極端子１１が形成されている。外部電極端子１１は外部基板との接続に用いる。
特開平５−１２９３５７号公報 The upper side surface of the circuit board 1 is covered with a sealing resin body 10 made of epoxy resin or the like in order to protect the semiconductor element 6 and the bonding wire 9 from the external environment. An external electrode terminal 11 such as a solder ball is formed on the back electrode 4 formed on the lower surface of the circuit board 1. The external electrode terminal 11 is used for connection with an external substrate.
JP-A-5-129357

近年、拡散プロセスの微細化並びに半導体素子の高機能化にともない、半導体素子上の表面電極数が飛躍的に増加してきており、これに対応して回路基板上の表面電極数、およびボンディングワイヤ本数を増加させるために、電極幅の縮小化およびボンディングワイヤの細線化等による対策が検討されている。しかしながら、電極幅の縮小化およびボンディングワイヤの細線化により、隣接するボンディングワイヤ間の間隔が縮小するとともに、ボンディングワイヤの強度が低下するため、回路基板の上側面をエポキシ樹脂等で樹脂封止する際の樹脂注入工程時のワイヤ流れによる、隣接するボンディングワイヤ同士の接触や、ループ中央部分でワイヤが垂れることによる、上下間で隣接するボンディングワイヤ同士の接触が発生する確率が高くなるという問題があった。   In recent years, the number of surface electrodes on semiconductor elements has increased dramatically with the miniaturization of the diffusion process and the higher functionality of semiconductor elements. Correspondingly, the number of surface electrodes on the circuit board and the number of bonding wires In order to increase the resistance, measures are being taken by reducing the electrode width and thinning the bonding wires. However, since the electrode width is reduced and the bonding wire is thinned, the distance between adjacent bonding wires is reduced and the strength of the bonding wire is reduced. Therefore, the upper surface of the circuit board is sealed with epoxy resin or the like. There is a problem that the probability of occurrence of contact between adjacent bonding wires between the upper and lower sides due to contact between adjacent bonding wires due to the flow of the wire during the resin injection process and dripping at the center of the loop increases. there were.

本発明は、上記従来の問題点に鑑み、拡散プロセスの微細化並びに半導体素子の高機能化にともない、半導体素子上の表面電極数が飛躍的に増加しても、ボンディングワイヤ同士の接触を防止することが可能となり、半導体装置の安定的な生産を実現することができる半導体装置およびその製造方法を提供することを目的とする。   In view of the above-mentioned conventional problems, the present invention prevents bonding wires from contacting each other even if the number of surface electrodes on the semiconductor element increases dramatically as the diffusion process becomes finer and the function of the semiconductor element increases. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can achieve stable production of the semiconductor device.

本発明の請求項１記載の半導体装置は、回路基板と、前記回路基板の素子搭載面に搭載された半導体素子と、前記半導体素子上に配置された電極と、前記半導体素子の電極に対応して前記回路基板上に配置された電極と、前記半導体素子の電極と前記回路基板の電極とを電気的に接続する金属細線と、前記回路基板上に形成された、前記金属細線を支持する絶縁性の突起部と、を備えたことを特徴とする。   A semiconductor device according to claim 1 of the present invention corresponds to a circuit board, a semiconductor element mounted on an element mounting surface of the circuit board, an electrode disposed on the semiconductor element, and an electrode of the semiconductor element. An electrode disposed on the circuit board, a fine metal wire that electrically connects the electrode of the semiconductor element and the electrode of the circuit board, and an insulation that supports the fine metal wire formed on the circuit board. And a protruding portion having a sex.

また、本発明の請求項２記載の半導体装置は、請求項１記載の半導体装置であって、前記突起部は溝を有し、その溝に前記金属細線が嵌め込まれていることを特徴とする。   The semiconductor device according to claim 2 of the present invention is the semiconductor device according to claim 1, wherein the protrusion has a groove, and the metal thin wire is fitted into the groove. .

また、本発明の請求項３記載の半導体装置は、請求項１もしくは２のいずれかに記載の半導体装置であって、前記回路基板の電極が配置されている面が、前記素子搭載面に対して高いことを特徴とする。   A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein a surface on which the electrode of the circuit board is disposed is relative to the element mounting surface. It is characterized by being expensive.

また、本発明の請求項４記載の半導体装置は、請求項１ないし３のいずれかに記載の半導体装置であって、前記回路基板の電極は複数列配置されており、その各列を構成する電極が配置されている各電極配置面が、前記回路基板の中央部側に隣接する電極配置面に対して高いか、少なくとも同一の高さであることを特徴とする。   A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the electrodes of the circuit board are arranged in a plurality of rows and constitute each row. Each electrode arrangement surface on which electrodes are arranged is higher than at least the same height as the electrode arrangement surface adjacent to the central portion of the circuit board.

また、本発明の請求項５記載の半導体装置の製造方法は、両面に導体パターンが形成されている基材に、その両面の導体パターン間を電気的に接続するビアを形成する工程と、ビアを形成した基材に、片面に導体パターンが形成されている基材を積層し、その積層した基材に、隣接する基材の導体パターン間を電気的に接続するビアを形成する工程と、積層した基材からなる回路基板の表面の一部を、導体パターンの一部を露出して絶縁樹脂で被覆する工程と、前記絶縁樹脂から露出する導体パターンの一部にめっきを形成する工程と、を有する回路基板を形成する工程を具備する半導体装置の製造方法であって、半導体素子を搭載する素子搭載面を有する基材の前記素子搭載面側に積層する基材には、積層する前に、半導体素子を格納可能な開口部を形成しておくことを特徴とする。   According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: forming a via on a base material having a conductor pattern formed on both sides thereof to electrically connect the conductor patterns on both sides; Laminating a base material having a conductor pattern formed on one side thereof on the base material formed, and forming a via in the laminated base material for electrically connecting the conductor patterns of adjacent base materials; A step of exposing a part of the conductor pattern to cover a part of the surface of the circuit board made of the laminated base material with an insulating resin, and a step of forming plating on a part of the conductor pattern exposed from the insulating resin; A method of manufacturing a semiconductor device comprising a step of forming a circuit board having a semiconductor substrate, wherein a substrate having an element mounting surface on which a semiconductor element is mounted is stacked on the substrate mounting surface side of the substrate. Can store semiconductor elements Wherein the previously formed opening.

また、本発明の請求項６記載の半導体装置の製造方法は、請求項５記載の半導体装置の製造方法であって、前記素子搭載面を有する基材の前記素子搭載面側に複数の基材を積層して回路基板を形成する場合、前記開口部が、前記素子搭載面を有する基材に近い順に小さくなるように積層することを特徴とする。   A semiconductor device manufacturing method according to claim 6 of the present invention is the semiconductor device manufacturing method according to claim 5, wherein a plurality of substrates are provided on the element mounting surface side of the substrate having the element mounting surface. When the circuit board is formed by laminating the layers, the openings are laminated so as to become smaller in the order closer to the base material having the element mounting surface.

また、本発明の請求項７記載の半導体装置の製造方法は、請求項５もしくは６のいずれかに記載の半導体装置の製造方法であって、回路基板の表面の一部を、導体パターンの一部を露出して絶縁樹脂で被覆するに際し、部分的に前記絶縁樹脂を厚くして突起部を形成することを特徴とする。   A method for manufacturing a semiconductor device according to claim 7 of the present invention is the method for manufacturing a semiconductor device according to any one of claims 5 and 6, wherein a part of the surface of the circuit board is formed on one of the conductor patterns. When the portion is exposed and covered with an insulating resin, the insulating resin is partially thickened to form a protrusion.

本発明によれば、拡散プロセスの微細化並びに半導体素子の高機能化にともない、半導体素子上の電極（表面電極）数が飛躍的に増加しても、突起部により金属細線（ボンディングワイヤ）を支持することで、金属細線の長ループ化および細線化よるループ中央部分での垂れを抑制し、上下間で隣接する金属細線同士の接触を防止することが可能となる。さらに、突起部の溝に金属細線を嵌め込むことで、金属細線が溝内で固定され、安定的な半導体装置の生産を図ることができる。   According to the present invention, even if the number of electrodes (surface electrodes) on a semiconductor element increases dramatically with the miniaturization of the diffusion process and the higher functionality of the semiconductor element, the metal thin wire (bonding wire) is formed by the protrusion. By supporting, it becomes possible to suppress the drooping in the center portion of the loop due to the lengthening and thinning of the fine metal wires, and to prevent contact between adjacent metal wires between the upper and lower sides. Further, by fitting the fine metal wire into the groove of the protrusion, the fine metal wire is fixed in the groove, and stable production of the semiconductor device can be achieved.

また、半導体素子を搭載する素子搭載面に対して、回路基板の電極（表面電極）が配置されている面を高くすることで、金属細線の長さを縮小することが可能となり、回路基板の上側面をエポキシ樹脂等で樹脂封止する際の樹脂注入工程時のワイヤ流れを抑制し、隣接する金属細線同士の接触を防止することが可能となる。   Further, by increasing the surface on which the electrode (surface electrode) of the circuit board is disposed with respect to the element mounting surface on which the semiconductor element is mounted, it becomes possible to reduce the length of the fine metal wire. It is possible to suppress the wire flow during the resin injection process when the upper side is resin-sealed with an epoxy resin or the like, and to prevent contact between adjacent fine metal wires.

以下、本発明の実施の形態における半導体装置、および半導体装置の製造方法について、ＢＧＡ型半導体装置を例に説明を行うが、本発明はＢＧＡ型半導体装置に限定されるものではない。   Hereinafter, the semiconductor device and the manufacturing method of the semiconductor device according to the embodiment of the present invention will be described by taking a BGA type semiconductor device as an example, but the present invention is not limited to the BGA type semiconductor device.

（実施の形態１）
図１は本発明の実施の形態１におけるＢＧＡ型半導体装置の構造を示す模式図であり、図１（ａ）は平面図、図１（ｂ）は図１（ａ）のＡ−Ａ’間の断面図、図１（ｃ）は図１（ａ）のＢ部の拡大図、図１（ｄ）は突起部の断面図である。 (Embodiment 1)
1A and 1B are schematic views showing the structure of a BGA type semiconductor device according to the first embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line AA ′ in FIG. FIG. 1C is an enlarged view of a portion B in FIG. 1A, and FIG. 1D is a sectional view of a protrusion.

図１（ａ）、図１（ｂ）において、回路基板１は、ポリイミド樹脂等からなる有機基板、或いは窒化アルミニウム（ＡｌＮ）等からなるセラミック基板などから形成されている。また、回路基板１の上側面には、四辺からなる回路基板１の各辺に沿って表面電極２が複数列（ここでは２列）配置されている。また、回路基板１の上側面には、半導体素子を搭載する素子搭載面（回路基板１の中央部）を囲むリング状の電源リング３が、表面電極２よりも内側に配置されている。電源リング３は、半導体素子へ電源あるいは接地電源を供給するための電極である。また、回路基板１の下側面には、格子状に裏面電極４が配置されている。これらの表面電極２、電源リング３、裏面電極４は、回路基板１の両面に形成されている銅（Ｃｕ）等からなる導体パターン（図示せず）の一部にめっきを施すことで形成される。また、回路基板１の両面は、導体パターンを外部環境から保護するために、半導体素子が搭載される領域（素子搭載面）、表面電極２、電源リング３、裏面電極４が形成されている領域を除く領域がソルダレジスト５で被覆されている。   1A and 1B, the circuit board 1 is formed of an organic substrate made of polyimide resin or the like, or a ceramic substrate made of aluminum nitride (AlN) or the like. On the upper side of the circuit board 1, a plurality of rows (here, two rows) of surface electrodes 2 are arranged along each side of the circuit board 1 having four sides. Further, on the upper side surface of the circuit board 1, a ring-shaped power supply ring 3 surrounding an element mounting surface (a central portion of the circuit board 1) on which a semiconductor element is mounted is disposed inside the surface electrode 2. The power ring 3 is an electrode for supplying power or ground power to the semiconductor element. Further, on the lower surface of the circuit board 1, back electrodes 4 are arranged in a lattice pattern. The front surface electrode 2, the power supply ring 3, and the back surface electrode 4 are formed by plating a part of a conductor pattern (not shown) made of copper (Cu) or the like formed on both surfaces of the circuit board 1. The In addition, on both sides of the circuit board 1, a region where a semiconductor element is mounted (element mounting surface), a surface electrode 2, a power supply ring 3, and a back electrode 4 are formed in order to protect the conductor pattern from the external environment. The area except for is covered with the solder resist 5.

また、図示しないが、回路基板１の内部には銅（Ｃｕ）等からなる導体パターン、およびビアが形成されており、その導体パターンとビアにより、上側面に形成されている表面電極２および電源リング３と下側面に形成されている裏面電極４とが電気的に接続されている。   Although not shown, a conductor pattern made of copper (Cu) or the like and a via are formed inside the circuit board 1, and the surface electrode 2 and the power source formed on the upper surface by the conductor pattern and the via. The ring 3 and the back electrode 4 formed on the lower surface are electrically connected.

半導体素子６は、回路基板１の上側面の中央部（素子搭載面）に接着剤７により接着されている。また、半導体素子６の上側面には、四辺からなる半導体素子６の各辺に沿って表面電極８が複数列（ここでは２列）配置されている。また、半導体素子６上の表面電極８と回路基板１上の表面電極２および電源リング３とが金（Ａｕ）などの金属性のボンディングワイヤ（金属細線）９により電気的に接続されている。   The semiconductor element 6 is bonded to the central portion (element mounting surface) of the upper side surface of the circuit board 1 with an adhesive 7. In addition, on the upper surface of the semiconductor element 6, a plurality of rows (here, two rows) of surface electrodes 8 are arranged along each side of the semiconductor element 6 having four sides. Further, the surface electrode 8 on the semiconductor element 6, the surface electrode 2 on the circuit board 1, and the power supply ring 3 are electrically connected by a metallic bonding wire (metal thin wire) 9 such as gold (Au).

また、回路基板１の上側面は、半導体素子６およびボンディングワイヤ９を外部環境から保護するために、エポキシ樹脂等からなる封止樹脂体１０により被覆されている。また、回路基板１の下側面に形成されている裏面電極４上には、半田ボール等の外部電極端子１１が形成されている。外部電極端子１１は外部基板との接続に用いる。   The upper side surface of the circuit board 1 is covered with a sealing resin body 10 made of epoxy resin or the like in order to protect the semiconductor element 6 and the bonding wire 9 from the external environment. An external electrode terminal 11 such as a solder ball is formed on the back electrode 4 formed on the lower surface of the circuit board 1. The external electrode terminal 11 is used for connection with an external substrate.

また、上下間で隣接するボンディングワイヤ同士の接触を避けるために、基板中央部側に接続するボンディングワイヤ９よりも基板外周部側に接続するボンディングワイヤ９のループ高さを高く設定している。その上、本実施の形態１では、回路基板１上に、ボンディングワイヤ９を支持する絶縁性の突起部１２が形成されており、この突起部１２でボンディングワイヤ９を支持することで、ボンディングワイヤ９の長ループ化および細線化によるループ中央部分での垂れを抑制し、上下間で隣接するボンディングワイヤ同士の接触を防止している。   Further, in order to avoid contact between adjacent bonding wires between the upper and lower sides, the loop height of the bonding wire 9 connected to the substrate outer peripheral portion side is set higher than the bonding wire 9 connected to the substrate central portion side. In addition, in the first embodiment, an insulating protrusion 12 that supports the bonding wire 9 is formed on the circuit board 1, and the bonding wire 9 is supported by the protrusion 12 so that the bonding wire 9 is supported. 9 is prevented from sagging at the center portion of the loop due to the long loop and thinning, thereby preventing contact between adjacent bonding wires between the upper and lower sides.

さらに、突起部１２は、図１（ｃ）、（ｄ）に示すように溝１３を有し、その溝１３にボンディングワイヤ９が嵌め込まれている。この構成により、ボンディングワイヤ９が溝１３内で固定され、安定的な半導体装置の生産を図ることができる。   Furthermore, the protrusion 12 has a groove 13 as shown in FIGS. 1C and 1D, and the bonding wire 9 is fitted into the groove 13. With this configuration, the bonding wire 9 is fixed in the groove 13, and a stable semiconductor device can be produced.

（実施の形態２）
図２は本発明の実施の形態２におけるＢＧＡ型半導体装置の構造を示す模式図であり、図２（ａ）は平面図、図２（ｂ）は図２（ａ）のＡ−Ａ’間の断面図である。但し、前述した実施の形態１において説明した部材と同一の部材には同一符号を付して、説明を省略する。 (Embodiment 2)
2A and 2B are schematic views showing the structure of the BGA type semiconductor device according to the second embodiment of the present invention. FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along the line AA 'in FIG. FIG. However, the same members as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

本実施の形態２における半導体装置は、各列を構成する表面電極２が配置されている各電極配置面が、回路基板１の中央部側に隣接する電極配置面に対して高くなっている点に特徴がある。すなわち、図２に示すように、基板外周部側（２列目）の電極配置面が、基板中央部側に隣接する１列目の電極配置面に対して高くなっている。また、ここでは、１列目の電極配置面が素子搭載面と同じ高さとなっており、２列目の電極配置面は、素子搭載面に対しても高くなっている。   In the semiconductor device according to the second embodiment, each electrode arrangement surface on which the surface electrodes 2 constituting each column are arranged is higher than the electrode arrangement surface adjacent to the center side of the circuit board 1. There is a feature. That is, as shown in FIG. 2, the electrode arrangement surface on the substrate outer peripheral side (second row) is higher than the electrode arrangement surface on the first row adjacent to the substrate center side. Here, the electrode arrangement surface in the first row is the same height as the device mounting surface, and the electrode arrangement surface in the second row is also higher than the device mounting surface.

この構成により、ボンディングワイヤの長さを縮小することが可能となり、回路基板の上側面をエポキシ樹脂等で樹脂封止する際の樹脂注入工程時のワイヤ流れを抑制し、隣接するボンディングワイヤ同士の接触を防止することが可能となる。   With this configuration, it is possible to reduce the length of the bonding wire, suppress the wire flow during the resin injection process when the upper surface of the circuit board is resin-sealed with epoxy resin or the like, and It becomes possible to prevent contact.

なお、本実施の形態２では、表面電極２が２列配置されている場合について説明したが、３列以上配置されている構成にも適用することができ、その場合、各列を構成する表面電極２が配置されている各電極配置面を、回路基板１の中央部側に隣接する電極配置面に対して高くするか、あるいは少なくとも同一の高さにする。   In the second embodiment, the case where the surface electrodes 2 are arranged in two rows has been described. However, the present invention can also be applied to a configuration in which three or more rows are arranged. Each electrode arrangement surface on which the electrode 2 is arranged is made higher than at least the same electrode arrangement surface adjacent to the central portion side of the circuit board 1 or at the same height.

（実施の形態３）
図３は本発明の実施の形態３におけるＢＧＡ型半導体装置の構造を示す模式図であり、図３（ａ）は平面図、図３（ｂ）は図３（ａ）のＡ−Ａ’間の断面図である。但し、前述した実施の形態１、２において説明した部材と同一の部材には同一符号を付して、説明を省略する。 (Embodiment 3)
3A and 3B are schematic views showing the structure of the BGA type semiconductor device according to the third embodiment of the present invention. FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line AA ′ in FIG. FIG. However, the same members as those described in the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted.

本実施の形態３における半導体装置は、図３に示すように、１列目の電極配置面も素子搭載面に対して高くなっている点が、前述の実施の形態２と異なる。また、電源リング３と１列目を構成する表面電極２との間にも突起部１２が形成されており、その突起部１２により、１列目を構成する表面電極２に接続するボンディングワイヤ９が支持されている。このように、各列ごとに突起部１２を設けてもよい。   As shown in FIG. 3, the semiconductor device according to the third embodiment is different from the second embodiment described above in that the electrode arrangement surface in the first column is also higher than the element mounting surface. Further, a protrusion 12 is also formed between the power ring 3 and the surface electrode 2 constituting the first row, and the bonding wire 9 connected to the surface electrode 2 constituting the first row by the protrusion 12. Is supported. Thus, you may provide the projection part 12 for every row | line | column.

この構成により、ボンディングワイヤの長さを縮小することが可能となり、回路基板の上側面をエポキシ樹脂等で樹脂封止する際の樹脂注入工程時のワイヤ流れを抑制し、隣接するボンディングワイヤ同士の接触を防止することが可能となる。   With this configuration, it is possible to reduce the length of the bonding wire, suppress the wire flow during the resin injection process when the upper surface of the circuit board is resin-sealed with epoxy resin or the like, and It becomes possible to prevent contact.

続いて、本実施の形態３における半導体装置の製造方法について説明する。図４は本発明の実施の形態３における半導体装置の製造方法を示す工程断面図であり、図３（ａ）のＡ−Ａ’間に相当する部分の断面を示している。   Next, a method for manufacturing a semiconductor device according to the third embodiment will be described. FIG. 4 is a process cross-sectional view illustrating the method of manufacturing the semiconductor device according to the third embodiment of the present invention, and shows a cross section of a portion corresponding to A-A ′ in FIG.

まず、図４（ａ）に示すように、例えば両面に銅等の金属箔が予め形成されたガラスエポキシ樹脂からなる基材１４ａの中央部に、半導体素子を格納可能な開口部を形成する。次に、両面にフォトレジスト等からなる樹脂皮膜を所望の配線パターンが残るように形成し、ドライエッチングもしくはウエットエッチングし、樹脂皮膜を除去することで配線パターン（導体パターン）１５を形成する。   First, as shown in FIG. 4A, for example, an opening capable of storing a semiconductor element is formed in a central portion of a base material 14a made of glass epoxy resin in which a metal foil such as copper is previously formed on both surfaces. Next, a resin film made of photoresist or the like is formed on both surfaces so that a desired wiring pattern remains, dry etching or wet etching is performed, and the resin film is removed to form a wiring pattern (conductor pattern) 15.

次に、図４（ｂ）に示すように、配線パターン１５を形成した基材１４ａにドリルやレーザー加工等により穴を形成し、その穴の壁面に導体めっき等により導体を形成することで、ビア１６を形成し、両面に形成された配線パターン１５間を電気的に接続する。   Next, as shown in FIG. 4B, by forming a hole in the base material 14a on which the wiring pattern 15 is formed by drilling or laser processing, and forming a conductor on the wall surface of the hole by conductor plating or the like, Vias 16 are formed, and the wiring patterns 15 formed on both surfaces are electrically connected.

次に、図４（ｃ）に示すように、予め片面に配線パターン１５を形成した基材１４ｂ、１４ｃを、ビアを形成した基材１４ａの両面に積層する。その際、基材１４ｂ、１４ｃは、配線パターン１５が形成された面とは反対側の面を基材１４ａに対向させて積層する。なお、基材１４ａの上部に積層する基材１４ｂの中央部には、積層前に、基材１４ａよりも大きな開口部を形成しておく。このように、ここでは、基材１４ｃが半導体素子を搭載する素子搭載面を有し、基材１４ｃの上部側（素子搭載面側）に積層する基材１４ａ、１４ｂに、積層前に開口部を形成しておき、基材１４ｃに近い順に開口部が小さくなるように積層する。こうすることで、半導体素子を搭載する素子搭載面に対して、回路基板の表面電極が配置される面を高くすることができる。   Next, as shown in FIG. 4C, the base materials 14b and 14c in which the wiring pattern 15 is formed in advance on one surface are laminated on both surfaces of the base material 14a in which vias are formed. At that time, the base materials 14b and 14c are laminated with the surface opposite to the surface on which the wiring pattern 15 is formed facing the base material 14a. In addition, the opening part larger than the base material 14a is formed in the center part of the base material 14b laminated | stacked on the upper part of the base material 14a before lamination | stacking. Thus, here, the base material 14c has an element mounting surface on which a semiconductor element is mounted, and the base material 14a, 14b stacked on the upper side (element mounting surface side) of the base material 14c has an opening before stacking. Are laminated so that the openings become smaller in the order closer to the base material 14c. By doing so, the surface on which the surface electrode of the circuit board is disposed can be made higher than the element mounting surface on which the semiconductor element is mounted.

次に、図４（ｄ）に示すように、基材１４ｂ、１４ｃにドリルやレーザー加工等により穴を形成し、その穴の壁面に導体めっき等により導体を形成し、ビア１６を形成することで、隣接する基材の配線パターン１５間を電気的に接続する。すなわち、中央の基材１４ａの配線パターン１５と積層された基材１４ｂ、１４ｃの配線パターン１５との間を電気的に接続する。   Next, as shown in FIG. 4 (d), holes are formed in the base materials 14b and 14c by drilling, laser processing or the like, conductors are formed on the wall surfaces of the holes by conductor plating or the like, and vias 16 are formed. Thus, the wiring patterns 15 of the adjacent base materials are electrically connected. That is, the wiring pattern 15 of the central base material 14a and the wiring patterns 15 of the laminated base materials 14b and 14c are electrically connected.

次に、外部環境から配線パターン１５を保護するために、図４（ｅ）に示すように、積層した基材１４ａ〜１４ｃからなる回路基板の両面のうち、半導体素子を搭載する領域、前記した表面電極２、電源リング３、裏面電極４を形成する領域を除く領域上に印刷工法等によりソルダレジスト（絶縁樹脂）５を塗布して、配線パターン１５をソルダレジスト５で被覆する。   Next, in order to protect the wiring pattern 15 from the external environment, as shown in FIG. 4 (e), the area on which the semiconductor element is mounted on both sides of the circuit board composed of the laminated base materials 14a to 14c, as described above A solder resist (insulating resin) 5 is applied to a region excluding the region where the front electrode 2, the power supply ring 3, and the back electrode 4 are formed by a printing method or the like, and the wiring pattern 15 is covered with the solder resist 5.

また、その際、一度ソルダレジストを塗布した後、再度、部分的にソルダレジストを塗布することで、部分的にソルダレジストを厚くして、絶縁性の突起部１２を形成する。また、突起部１２上にフォトレジスト等からなる樹脂皮膜を形成し、ドライエッチングもしくはウエットエッチングし、ソルダレジストを局部的に除去することで、突起部１２上に溝１３を形成する。なお、突起部に関しては、絶縁テープなどの絶縁材料をソルダレジスト面に貼り付けることで形成することも可能である。   At that time, after applying the solder resist once, the solder resist is partially applied again, so that the solder resist is partially thickened to form the insulating protrusions 12. Also, a groove 13 is formed on the protrusion 12 by forming a resin film made of a photoresist or the like on the protrusion 12, performing dry etching or wet etching, and locally removing the solder resist. The protrusions can also be formed by attaching an insulating material such as an insulating tape to the solder resist surface.

次に、図４（ｆ）に示すように、配線パターン１５のソルダレジスト５から露出する部分に、ウエットめっき等によりニッケルや金等の導体めっき１７を形成することで、前記した表面電極２、電源リング３、裏面電極４を形成する。   Next, as shown in FIG. 4 (f), the surface electrode 2 described above is formed by forming a conductor plating 17 such as nickel or gold by wet plating or the like on a portion exposed from the solder resist 5 of the wiring pattern 15. A power ring 3 and a back electrode 4 are formed.

本発明にかかる半導体装置およびその製造方法は、拡散プロセスの微細化並びに半導体素子の高機能化にともない、半導体素子上の表面電極数が飛躍的に増加しても、ボンディングワイヤ同士の接触を防止することが可能となり、半導体装置の安定的な生産を実現することに有用である。   The semiconductor device and the manufacturing method thereof according to the present invention prevent bonding wires from contacting each other even when the number of surface electrodes on the semiconductor element increases dramatically as the diffusion process becomes finer and the function of the semiconductor element increases. This is useful for realizing stable production of semiconductor devices.

本発明の実施の形態１における半導体装置の構造を示す模式図Schematic diagram showing the structure of the semiconductor device according to the first embodiment of the present invention. 本発明の実施の形態２における半導体装置の構造を示す模式図Schematic diagram showing the structure of the semiconductor device according to the second embodiment of the present invention. 本発明の実施の形態３における半導体装置の構造を示す模式図Schematic diagram showing the structure of the semiconductor device according to the third embodiment of the present invention. 本発明の実施の形態３における半導体装置の製造方法を示す工程断面図Sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 3 of this invention 従来の半導体装置の構造を示す模式図Schematic diagram showing the structure of a conventional semiconductor device

符号の説明Explanation of symbols

１ 回路基板
２ 回路基板の表面電極
３ 電源リング
４ 回路基板の裏面電極
５ ソルダレジスト（絶縁樹脂）
６ 半導体素子
７ 接着剤
８ 半導体素子の表面電極
９ ボンディングワイヤ（金属細線）
１０ 封止樹脂体
１１ 外部電極端子
１２ 突起部
１３ 突起部の溝
１４ａ〜１４ｃ 基材
１５ 配線パターン（導体パターン）
１６ ビア
１７ 導体めっき DESCRIPTION OF SYMBOLS 1 Circuit board 2 Circuit board surface electrode 3 Power supply ring 4 Circuit board back surface electrode 5 Solder resist (insulating resin)
6 Semiconductor element 7 Adhesive 8 Surface electrode of semiconductor element 9 Bonding wire (fine metal wire)
DESCRIPTION OF SYMBOLS 10 Sealing resin body 11 External electrode terminal 12 Protrusion part 13 Groove of protrusion part 14a-14c Base material 15 Wiring pattern (conductor pattern)
16 Via 17 Conductor plating

Claims (7)

回路基板と、前記回路基板の素子搭載面に搭載された半導体素子と、前記半導体素子上に配置された電極と、前記半導体素子の電極に対応して前記回路基板上に配置された電極と、前記半導体素子の電極と前記回路基板の電極とを電気的に接続する金属細線と、前記回路基板上に形成された、前記金属細線を支持する絶縁性の突起部と、を備えたことを特徴とする半導体装置。   A circuit board; a semiconductor element mounted on an element mounting surface of the circuit board; an electrode disposed on the semiconductor element; an electrode disposed on the circuit board corresponding to the electrode of the semiconductor element; A thin metal wire that electrically connects the electrode of the semiconductor element and the electrode of the circuit board; and an insulating protrusion that is formed on the circuit board and supports the thin metal wire. A semiconductor device. 請求項１記載の半導体装置であって、前記突起部は溝を有し、その溝に前記金属細線が嵌め込まれていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the protrusion has a groove, and the fine metal wire is fitted into the groove. 請求項１もしくは２のいずれかに記載の半導体装置であって、前記回路基板の電極が配置されている面が、前記素子搭載面に対して高いことを特徴とする半導体装置。   3. The semiconductor device according to claim 1, wherein a surface of the circuit board on which the electrode is disposed is higher than the element mounting surface. 請求項１ないし３のいずれかに記載の半導体装置であって、前記回路基板の電極は複数列配置されており、その各列を構成する電極が配置されている各電極配置面が、前記回路基板の中央部側に隣接する電極配置面に対して高いか、少なくとも同一の高さであることを特徴とする半導体装置。   4. The semiconductor device according to claim 1, wherein the electrodes of the circuit board are arranged in a plurality of rows, and each electrode placement surface on which electrodes constituting each row are arranged is the circuit. A semiconductor device having a height that is at least equal to or higher than an electrode arrangement surface adjacent to the central portion of the substrate. 両面に導体パターンが形成されている基材に、その両面の導体パターン間を電気的に接続するビアを形成する工程と、
ビアを形成した基材に、片面に導体パターンが形成されている基材を積層し、その積層した基材に、隣接する基材の導体パターン間を電気的に接続するビアを形成する工程と、
積層した基材からなる回路基板の表面の一部を、導体パターンの一部を露出して絶縁樹脂で被覆する工程と、
前記絶縁樹脂から露出する導体パターンの一部にめっきを形成する工程と、
を有する回路基板を形成する工程を具備する半導体装置の製造方法であって、半導体素子を搭載する素子搭載面を有する基材の前記素子搭載面側に積層する基材には、積層する前に、半導体素子を格納可能な開口部を形成しておくことを特徴とする半導体装置の製造方法。 Forming a via electrically connecting between the conductor patterns on both sides of the substrate on which the conductor patterns are formed on both sides;
A step of laminating a substrate having a conductor pattern formed on one side thereof on a substrate on which vias are formed, and forming vias electrically connecting between the conductor patterns of adjacent substrates on the laminated substrate; and ,
A part of the surface of the circuit board made of the laminated base material, a part of the conductor pattern is exposed and covered with an insulating resin;
Forming a plating on a part of the conductor pattern exposed from the insulating resin;
A method of manufacturing a semiconductor device comprising a step of forming a circuit board having a semiconductor substrate, wherein a substrate having an element mounting surface on which a semiconductor element is mounted is laminated on the substrate mounting surface side before being stacked A method of manufacturing a semiconductor device, wherein an opening capable of storing a semiconductor element is formed. 請求項５記載の半導体装置の製造方法であって、前記素子搭載面を有する基材の前記素子搭載面側に複数の基材を積層して回路基板を形成する場合、前記開口部が、前記素子搭載面を有する基材に近い順に小さくなるように積層することを特徴とする半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 5, wherein when the circuit board is formed by laminating a plurality of base materials on the element mounting surface side of the base material having the element mounting surface, the opening is A method of manufacturing a semiconductor device, wherein the layers are stacked so as to become smaller in order from the base material having the element mounting surface. 請求項５もしくは６のいずれかに記載の半導体装置の製造方法であって、回路基板の表面の一部を、導体パターンの一部を露出して絶縁樹脂で被覆するに際し、部分的に前記絶縁樹脂を厚くして突起部を形成することを特徴とする半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 5, wherein a part of the surface of the circuit board is partially covered with an insulating resin when a part of the conductor pattern is exposed and covered with an insulating resin. A method of manufacturing a semiconductor device, wherein a protrusion is formed by thickening a resin.
JP2007120434A 2007-05-01 2007-05-01 Semiconductor device, and manufacturing method thereof Pending JP2008277595A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013004984A (en) * 2011-06-17 2013-01-07 Biotronik Se & Co Kg Semiconductor package
CN108807337A (en) * 2018-06-27 2018-11-13 山东傲天环保科技有限公司 A kind of COB encapsulating structures
JP2020013833A (en) * 2018-07-13 2020-01-23 トヨタ自動車株式会社 Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013004984A (en) * 2011-06-17 2013-01-07 Biotronik Se & Co Kg Semiconductor package
CN108807337A (en) * 2018-06-27 2018-11-13 山东傲天环保科技有限公司 A kind of COB encapsulating structures
CN108807337B (en) * 2018-06-27 2020-10-20 上海纬而视科技股份有限公司 COB packaging structure
JP2020013833A (en) * 2018-07-13 2020-01-23 トヨタ自動車株式会社 Semiconductor device
JP7035868B2 (en) 2018-07-13 2022-03-15 株式会社デンソー Semiconductor device

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