JP2008244211A - Manufacturing method for thin-film chip resistor - Google Patents

Manufacturing method for thin-film chip resistor Download PDF

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JP2008244211A
JP2008244211A JP2007083728A JP2007083728A JP2008244211A JP 2008244211 A JP2008244211 A JP 2008244211A JP 2007083728 A JP2007083728 A JP 2007083728A JP 2007083728 A JP2007083728 A JP 2007083728A JP 2008244211 A JP2008244211 A JP 2008244211A
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thin film
resistor
insulating substrate
forming
sheet
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Kazuhiro Kanda
一宏 神田
Mitsuaki Nakao
光明 中尾
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a thin-film chip resistor that can be manufactured at low cost and is excellent in reliability. <P>SOLUTION: A manufacturing method for a thin-film chip resistor includes a step to form many top electrodes 12 by printing and baking organic metal paste on the top surface of a sheet-like insulating substrate, a step to cover at least a part of many top electrodes 12 and to form many thin-film resistors 13 to be electrically connected with many top electrodes 12, and a step to form many inorganic protection films 14 to cover many thin-film resistors 13. A metal mask consisting of 42 alloy is mounted on the top surface of the sheet-like insulating substrate to form the thin-film resistors 13 with mask sputter. Subsequently, the inorganic protection films 14 are formed with the mask sputter continuously without removing the metal mask. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、各種電子機器に用いられる薄膜チップ抵抗器の製造方法に関するものである。   The present invention relates to a method of manufacturing a thin film chip resistor used in various electronic devices.

近年、電子機器の小形化およびコストダウンに伴い、搭載される電子部品に対しても小形化およびコストダウンへの要求が高まっている。チップ抵抗器においても小形化が進められるとともに、高精度でかつ電流雑音特性に優れた薄膜チップ抵抗器を安価に提供する要求が高まっている。   In recent years, with the downsizing and cost reduction of electronic devices, there is an increasing demand for downsizing and cost reduction of mounted electronic components. As chip resistors are also being miniaturized, there is an increasing demand for providing thin film chip resistors with high accuracy and excellent current noise characteristics at low cost.

従来の薄膜チップ抵抗器は、図7に示すように、純度約96%のアルミナからなる絶縁基板1の裏面の両端部に形成した一対の裏面電極2と、前記絶縁基板1の上面の両端部に形成した一対の上面電極3と、この一対の上面電極3と電気的に接続されるようにスパッタリングにより形成した抵抗体4と、この抵抗体4の一部を覆う保護膜5(第1の保護膜5a、第2の保護膜5b、第3の保護膜5c)と前記上面電極3および前記抵抗体4と電気的に接続され、かつ前記保護膜5と接するように前記絶縁基板1の上面の両端部に形成した銀系の樹脂からなる一対の再上面電極6と、この再上面電極6と前記裏面電極2を電気的に接続するように前記絶縁基板1の両端部に形成した一対の端面電極7と、この端面電極7と前記再上面電極6と前記裏面電極2の露出部分に形成されたニッケルめっき層8と、このニッケルめっき層8を覆う錫めっき層9とを備えた構成としていた。   As shown in FIG. 7, the conventional thin film chip resistor includes a pair of back electrodes 2 formed on both ends of the back surface of the insulating substrate 1 made of alumina having a purity of about 96%, and both end portions of the top surface of the insulating substrate 1. A pair of upper surface electrodes 3, a resistor 4 formed by sputtering so as to be electrically connected to the pair of upper surface electrodes 3, and a protective film 5 (a first film covering the part of the resistor 4) A protective film 5a, a second protective film 5b, a third protective film 5c) and the upper surface of the insulating substrate 1 so as to be in electrical contact with the upper surface electrode 3 and the resistor 4 and in contact with the protective film 5. A pair of resurfaced electrodes 6 made of silver-based resin formed on both ends of the insulating substrate 1 and a pair of resurfaced electrodes 6 formed on both ends of the insulating substrate 1 so as to electrically connect the resurfaced electrode 6 and the backside electrode 2 The end face electrode 7, the end face electrode 7, the re-upper face electrode 6, and the front A nickel plating layer 8 formed on the exposed portion of the back electrode 2 had a structure in which a tin plating layer 9 covering the nickel plating layer 8.

なお、この出願の発明に関する先行技術文献情報としては、例えば、特許文献1、2が知られている。特許文献1に記載の従来の薄膜チップ抵抗器においては、抵抗体4のみを薄膜で形成し、かつそれ以外の主要な構成要素、すなわち裏面電極2、上面電極3、再上面電極6および端面電極7はすべて導電性ペーストを用いた厚膜プロセスによって形成しているため、すべての構成要素を薄膜で形成する場合に比べて安価に製造することができるという特徴を有していた。
特開2002−64002号公報 特開2005−223272号公報
For example, Patent Documents 1 and 2 are known as prior art document information relating to the invention of this application. In the conventional thin film chip resistor described in Patent Document 1, only the resistor 4 is formed of a thin film, and other main components, that is, the back surface electrode 2, the top surface electrode 3, the retop surface electrode 6, and the end surface electrode Since No. 7 is formed by a thick film process using a conductive paste, it has a feature that it can be manufactured at a lower cost than a case where all the constituent elements are formed of a thin film.
JP 2002-640002 A JP 2005-223272 A

しかしながら、上記特許文献1に記載の従来の薄膜チップ抵抗器は、抵抗体4をフォトリソプロセスを用いて薄膜で形成し、そしてこの抵抗体4の表面に薄膜によりアルミナ等の絶縁性物質を成膜することによって第1の保護膜5aを形成するようにしているため、抵抗体4の形成工程と第1の保護膜5aの形成工程でそれぞれ別個にマスクパターンを設置する必要があり、製造工程が煩雑になるものであった。また、上記特許文献2には、シート状の絶縁基板の上面にメタルマスクを設置して抵抗体4をマスクスパッタで形成する技術が開示されているもので、この特許文献2に開示された技術と前記した特許文献1の技術を組み合わせれば、シート状の絶縁基板の上面にメタルマスクを設置して抵抗体4をマスクスパッタで形成し、その後、このメタルマスクを取り外さずにこのメタルマスクを利用して第1の保護膜5aをマスクスパッタで形成することができるもので、これによれば、製造工程を簡略化することができるものである。しかしながら、この場合、前記マスクスパッタ工程で用いられるメタルマスクは、特許文献2に記載されているように一般にはステンレスが用いられているもので、このステンレスはシート状の絶縁基板を構成する耐熱絶縁材料であるアルミナ等のセラミックと比較して熱膨張係数が大きいものであるため、抵抗体4の形成工程と第1の保護膜5aの形成工程においてこのメタルマスクを繰り返し使用した場合は、このメタルマスクが熱履歴を受けて変形することになり、その結果、メタルマスクの位置ずれが発生しやすくなって、抵抗体4のパターンを形成する位置もずれやすくなり、これにより、上面電極3との電気的接続が十分保証されずに製品の歩留り悪化につながるという課題を有していた。   However, in the conventional thin film chip resistor described in Patent Document 1, the resistor 4 is formed as a thin film using a photolithography process, and an insulating material such as alumina is formed on the surface of the resistor 4 by a thin film. Thus, since the first protective film 5a is formed, it is necessary to install a mask pattern separately in each of the resistor 4 forming process and the first protective film 5a forming process. It was complicated. Further, Patent Document 2 discloses a technique in which a metal mask is provided on the upper surface of a sheet-like insulating substrate and the resistor 4 is formed by mask sputtering. The technique disclosed in Patent Document 2 is disclosed. And the technique of Patent Document 1 described above, a metal mask is formed on the upper surface of the sheet-like insulating substrate, and the resistor 4 is formed by mask sputtering. Thereafter, the metal mask is removed without removing the metal mask. By utilizing this, the first protective film 5a can be formed by mask sputtering, and according to this, the manufacturing process can be simplified. However, in this case, the metal mask used in the mask sputtering process is generally made of stainless steel as described in Patent Document 2, and this stainless steel is a heat-resistant insulation that forms a sheet-like insulating substrate. Since the thermal expansion coefficient is larger than that of ceramic such as alumina, which is a material, when this metal mask is repeatedly used in the process of forming the resistor 4 and the process of forming the first protective film 5a, the metal The mask is deformed in response to the thermal history, and as a result, the displacement of the metal mask is likely to occur, and the position where the pattern of the resistor 4 is formed is also likely to be displaced. There is a problem that the electrical connection is not sufficiently guaranteed and the yield of the product is deteriorated.

本発明は上記従来の課題を解決するもので、コスト的にも安価に製造でき、かつ信頼性において優れている薄膜チップ抵抗器の製造方法を提供することを目的とするものである。   SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a thin film chip resistor that can be manufactured at low cost and is excellent in reliability.

上記目的を達成するために、本発明は以下の構成を有するものである。   In order to achieve the above object, the present invention has the following configuration.

本発明の請求項1に記載の発明は、シート状の絶縁基板の上面に有機金属ペーストを印刷して焼成することにより複数の上面電極を形成する工程と、前記複数の上面電極の少なくとも一部を覆い、かつこの複数の上面電極と電気的に接続されるように複数の薄膜抵抗体を形成する工程と、前記複数の薄膜抵抗体を覆うように複数の無機保護膜を形成する工程と、前記複数の上面電極を覆うように導電性樹脂ペーストを印刷して硬化させることにより複数の再上面電極を形成する工程と、前記複数の無機保護膜を覆うように熱硬化性樹脂ペーストを印刷して硬化させることにより複数の有機保護膜を形成する工程と、前記シート状の絶縁基板の裏面に導電性樹脂ペーストを印刷して硬化させることにより複数の裏面電極を形成する工程と、前記シート状の絶縁基板を分割して短冊状の基板を得る工程と、前記短冊状の基板の端面に前記上面電極、前記再上面電極、前記裏面電極と電気的に接続されるように導電性樹脂ペーストを塗布して硬化させることにより端面電極を形成する工程とを備え、前記シート状の絶縁基板の上面に42アロイで構成したメタルマスクを設置して前記薄膜抵抗体をマスクスパッタで形成し、その後、前記メタルマスクを取り外さずに続けて無機保護膜をマスクスパッタで形成したもので、この製造方法によれば、メタルマスクをステンレスよりも熱膨張係数の小さい42アロイで構成しているため、前記メタルマスクを薄膜抵抗体の形成と無機保護膜の形成に繰り返し使用しても、メタルマスクが熱履歴を受けて変形するということはなくなり、その結果、メタルマスクの位置ずれも発生しにくくなるため、薄膜抵抗体の形成位置がずれるということはなくなり、これにより、上面電極と薄膜抵抗体との電気的接続が確実に保証されるため、信頼性において優れている薄膜チップ抵抗器がコスト的にも安価に得られるという作用効果を有するものである。   According to a first aspect of the present invention, there is provided a step of forming a plurality of upper surface electrodes by printing and baking an organic metal paste on an upper surface of a sheet-like insulating substrate, and at least a part of the plurality of upper surface electrodes. And forming a plurality of thin film resistors so as to be electrically connected to the plurality of upper surface electrodes, and forming a plurality of inorganic protective films so as to cover the plurality of thin film resistors, Printing a conductive resin paste so as to cover the plurality of upper surface electrodes and curing the conductive resin paste; and printing a thermosetting resin paste so as to cover the plurality of inorganic protective films. Forming a plurality of organic protective films by curing, and forming a plurality of back electrodes by printing and curing a conductive resin paste on the back surface of the sheet-like insulating substrate; and A step of obtaining a strip-shaped substrate by dividing a strip-shaped insulating substrate, and conductive so as to be electrically connected to the end surface of the strip-shaped substrate with the upper surface electrode, the upper surface electrode, and the rear surface electrode. Forming an end face electrode by applying and curing a resin paste, placing a metal mask composed of 42 alloy on the upper surface of the sheet-like insulating substrate, and forming the thin film resistor by mask sputtering. Subsequently, the inorganic protective film was formed by mask sputtering without removing the metal mask, and according to this manufacturing method, the metal mask was composed of 42 alloy having a smaller thermal expansion coefficient than stainless steel. Even if the metal mask is repeatedly used for the formation of the thin film resistor and the inorganic protective film, the metal mask will not be deformed due to the thermal history. Since the displacement of the metal mask is less likely to occur, the formation position of the thin film resistor is no longer shifted. This ensures reliable electrical connection between the upper surface electrode and the thin film resistor. This has the effect that an excellent thin film chip resistor can be obtained at low cost.

以上のように本発明の薄膜チップ抵抗器の製造方法は、シート状の絶縁基板の上面に42アロイで構成したメタルマスクを設置して薄膜抵抗体をマスクスパッタで形成し、その後、前記メタルマスクを取り外さずに続けて無機保護膜をマスクスパッタで形成したもので、前記メタルマスクをステンレスよりも熱膨張係数の小さい42アロイで構成しているため、前記メタルマスクを薄膜抵抗体の形成と無機保護膜の形成に繰り返し使用しても、メタルマスクが熱履歴を受けて変形するということはなくなり、その結果、これにより、メタルマスクの位置ずれも発生しにくくなるため、薄膜抵抗体の形成位置がずれるということはなくなり、これにより、上面電極と薄膜抵抗体との電気的接続が確実に保証されるため、信頼性において優れている薄膜チップ抵抗器がコスト的にも安価に得られるという優れた効果を奏するものである。   As described above, in the method of manufacturing a thin film chip resistor according to the present invention, a metal mask composed of 42 alloy is placed on the upper surface of a sheet-like insulating substrate to form a thin film resistor by mask sputtering, and then the metal mask. An inorganic protective film is formed by mask sputtering without removing the metal mask, and the metal mask is composed of 42 alloy having a thermal expansion coefficient smaller than that of stainless steel. Even if it is repeatedly used for forming the protective film, the metal mask will not be deformed due to the thermal history, and as a result, the metal mask is less likely to be displaced. This ensures that the electrical connection between the upper surface electrode and the thin film resistor is ensured, so that it is excellent in reliability. Thin film chip resistor in which an excellent effect of obtaining inexpensive in cost.

以下、本発明の一実施の形態における薄膜チップ抵抗器の製造方法について、図面を参照しながら説明する。   Hereinafter, a method of manufacturing a thin film chip resistor according to an embodiment of the present invention will be described with reference to the drawings.

図1は本発明の一実施の形態における薄膜チップ抵抗器の断面図、図2は同薄膜チップ抵抗器の製造方法を示すフローチャートである。   FIG. 1 is a cross-sectional view of a thin film chip resistor according to an embodiment of the present invention, and FIG. 2 is a flowchart showing a method for manufacturing the thin film chip resistor.

図1において、11は純度96%のアルミナからなる絶縁基板、12は絶縁基板11の上面の両端部に形成された一対の上面電極、13は上面電極12の少なくとも一部を覆い、かつこの上面電極12と電気的に接続された薄膜抵抗体、14は薄膜抵抗体13を覆うように形成された無機保護膜、15は上面電極12と無機保護膜14を覆うように形成された一対の再上面電極、17は無機保護膜14と再上面電極15の一部を覆うように形成された有機保護膜、18は絶縁基板11の裏面の両端部に形成された一対の裏面電極、20は上面電極12、再上面電極15および裏面電極18と電気的に接続される一対の端面電極、21は再上面電極15、裏面電極18および端面電極20の表面を覆うニッケルめっき層、22はニッケルめっき層21の表面を覆う錫めっき層である。   In FIG. 1, 11 is an insulating substrate made of alumina of 96% purity, 12 is a pair of upper surface electrodes formed at both ends of the upper surface of the insulating substrate 11, and 13 covers at least a part of the upper surface electrode 12, and this upper surface. A thin film resistor electrically connected to the electrode 12, 14 is an inorganic protective film formed so as to cover the thin film resistor 13, and 15 is a pair of re-covers formed so as to cover the upper surface electrode 12 and the inorganic protective film 14. An upper surface electrode, 17 is an organic protective film formed so as to cover a part of the inorganic protective film 14 and the re-upper surface electrode 15, 18 is a pair of back surface electrodes formed at both ends of the back surface of the insulating substrate 11, and 20 is an upper surface. A pair of end face electrodes electrically connected to the electrode 12, the resurface upper electrode 15 and the back face electrode 18, 21 is a nickel plating layer covering the surfaces of the retop face electrode 15, the back face electrode 18 and the end face electrode 20, 22 is nickel plating 21 is a tin-plated layer covering the surface of the.

次に、本発明の一実施の形態における薄膜チップ抵抗器の製造方法を図2のフローチャート、図3(a)〜(c)、図4(a)〜(c)、図5(a)〜(d)および図6(a)〜(d)の製造工程図にもとづいて説明する。   Next, the manufacturing method of the thin film chip resistor in one embodiment of the present invention is shown in the flowchart of FIG. 2, FIGS. 3 (a) to 3 (c), FIGS. 4 (a) to (c), and FIG. A description will be given based on (d) and the manufacturing process diagrams of FIGS.

まず、図3(a)に示すように、1次分割溝11aと2次分割溝11bを有する純度96%のアルミナからなるシート状の絶縁基板11cの上面に、金を主成分とする金属有機物ペーストを1次分割溝11aを跨ぐようにスクリーン印刷して乾燥させ、その後、金属有機物ペーストの有機成分だけを飛ばし、そして金属成分だけを絶縁基板11c上に焼き付けるために、ベルト式連続焼成炉によって600℃〜900℃で焼成し、複数の上面電極12を形成する(図2の上面電極形成工程)。   First, as shown in FIG. 3A, a metal organic material mainly composed of gold is formed on the upper surface of a sheet-like insulating substrate 11c made of alumina having a purity of 96% and having primary division grooves 11a and secondary division grooves 11b. The paste is screen-printed so as to straddle the primary dividing grooves 11a and dried. Thereafter, in order to remove only the organic component of the metal organic paste and burn only the metal component on the insulating substrate 11c, a belt-type continuous firing furnace is used. Baking is performed at 600 ° C. to 900 ° C. to form a plurality of upper surface electrodes 12 (upper surface electrode forming step in FIG. 2).

次に、図3(b)に示すように、シート状の絶縁基板11cの上面に、42アロイからなるメタルマスク(図示せず)を設置し、マスクスパッタ工法を用いてニッケルクロム系合金等からなる複数の薄膜抵抗体13を、複数の上面電極12の少なくとも一部を覆い、かつこの複数の上面電極12と電気的に接続されるように形成する。なお、この薄膜抵抗体13を構成する材料はニッケルクロム系合金に限定されるものではなく、要求される特性に応じて他の材料、例えば窒化タンタル系、クロムシリコン系、酸化タンタル系等の抵抗体として使用できる金属合金やその複合体を用いてもよいものである(図2の薄膜抵抗体形成工程)。   Next, as shown in FIG. 3 (b), a metal mask (not shown) made of 42 alloy is placed on the upper surface of the sheet-like insulating substrate 11c, and a nickel-chromium alloy or the like is used using a mask sputtering method. The plurality of thin film resistors 13 are formed so as to cover at least a part of the plurality of upper surface electrodes 12 and to be electrically connected to the plurality of upper surface electrodes 12. The material constituting the thin film resistor 13 is not limited to a nickel-chromium alloy, and other materials such as tantalum nitride, chromium silicon, and tantalum oxide can be used depending on required characteristics. A metal alloy that can be used as a body or a composite thereof may be used (thin film resistor forming step in FIG. 2).

次に、図3(c)に示すように、薄膜抵抗体13の形成に用いたメタルマスク(図示せず)を取り外さずに続けてマスクスパッタ工法を用いて、酸化ケイ素やアルミナ等の高絶縁性材料からなる無機保護膜14を、薄膜抵抗体13を覆うように50nm〜10μmの厚みで形成する。この場合、シート状の絶縁基板11cの上面にメタルマスクを設置して薄膜抵抗体13をマスクスパッタで形成した後、前記メタルマスクを取り外さずに続けて無機保護膜14をマスクスパッタで形成しているため、薄膜抵抗体13の形成と無機保護膜14の形成をマスクスパッタで連続して実施することができ、これにより、薄膜チップ抵抗器の製造工程が簡略化されて製造コストの低減が図れるものである。また、前記メタルマスクはステンレスよりも熱膨張係数の小さい42アロイで構成しているため、前記メタルマスクを薄膜抵抗体13の形成と無機保護膜14の形成に繰り返し使用しても、メタルマスクが熱履歴を受けて変形するということはなくなり、その結果、メタルマスクの位置ずれも発生しにくくなるため、薄膜抵抗体13の形成位置がずれるということはなくなり、これにより、上面電極12と薄膜抵抗体13との電気的接続も確実に保証されるため、信頼性において優れている薄膜チップ抵抗器がコスト的にも安価に得られるものである。また、このメタルマスクは前述したように42アロイ(ニッケルを42%含む鉄ニッケル系合金)で構成しているもので、この42アロイの熱膨張係数は4.5〜6.5×10-6/℃で、メタルマスクの材料として従来から用いられているステンレス(SUS430)の熱膨張係数10.4×10-6/℃よりも小さいため、上記した効果が顕著に現れるものである。また、無機保護膜14は厚みが50nmよりも薄いと保護膜としての役割を果たさず、一方、厚みが10μmよりも厚いと無機保護膜14の材料の内部応力が上がることになり、これにより、無機保護膜14に剥がれや割れ、そして欠けが発生しやすくなって保護膜としての役割を果たさなくなるものである。したがって、無機保護膜14の厚みは50nm以上10μm以下とするのが好ましい(図2の無機保護膜形成工程)。 Next, as shown in FIG. 3 (c), without removing the metal mask (not shown) used to form the thin film resistor 13, the mask sputtering method is used to perform high insulation such as silicon oxide or alumina. An inorganic protective film 14 made of a conductive material is formed to a thickness of 50 nm to 10 μm so as to cover the thin film resistor 13. In this case, a metal mask is placed on the upper surface of the sheet-like insulating substrate 11c and the thin film resistor 13 is formed by mask sputtering, and then the inorganic protective film 14 is formed by mask sputtering without removing the metal mask. Therefore, the formation of the thin film resistor 13 and the formation of the inorganic protective film 14 can be continuously performed by mask sputtering, thereby simplifying the manufacturing process of the thin film chip resistor and reducing the manufacturing cost. Is. Further, since the metal mask is composed of 42 alloy having a smaller thermal expansion coefficient than stainless steel, the metal mask can be used even when the metal mask is repeatedly used for forming the thin film resistor 13 and the inorganic protective film 14. As a result, the metal mask is not deformed due to heat history, and the metal mask is not easily displaced. Therefore, the formation position of the thin film resistor 13 is not shifted. Since the electrical connection with the body 13 is also reliably ensured, a thin film chip resistor excellent in reliability can be obtained at low cost. Further, as described above, this metal mask is made of 42 alloy (iron nickel-based alloy containing 42% nickel), and the thermal expansion coefficient of this 42 alloy is 4.5 to 6.5 × 10 −6. Since the thermal expansion coefficient is less than 10.4 × 10 −6 / ° C. of stainless steel (SUS430) conventionally used as a metal mask material at / ° C., the above-described effects are remarkably exhibited. Further, if the thickness of the inorganic protective film 14 is less than 50 nm, the inorganic protective film 14 does not play a role as a protective film. On the other hand, if the thickness is thicker than 10 μm, the internal stress of the material of the inorganic protective film 14 increases. The inorganic protective film 14 is easily peeled off, cracked and chipped, and can no longer serve as a protective film. Therefore, the thickness of the inorganic protective film 14 is preferably 50 nm or more and 10 μm or less (inorganic protective film forming step in FIG. 2).

次に、図4(a)に示すように、上面電極12および無機保護膜14の一部を覆うように再上面電極15をその厚みが3μm以上20μm以下となるように形成する。この再上面電極15は、例えばエポキシ系等の樹脂と銀等の導電性粒子の混合体からなる導電性樹脂ペーストを印刷して硬化させることにより形成するものであり、ガラスフリットと導電性粒子を混合焼成した電極材料と比較した場合、鉛を含まないため、環境保護の観点から優れているものである。また、600℃〜900℃で焼成する金レジネート等の金属有機物ペーストと比較した場合、150℃〜300℃という比較的低温で硬化させることができるため、生産時の熱処理炉の使用電力量が少なくて済み、さらには金を含まない安価な材料が利用できるため、製造コストも削減できるものである(図2の再上面電極形成工程)。   Next, as shown in FIG. 4A, the upper surface electrode 15 is formed so as to have a thickness of 3 μm or more and 20 μm or less so as to cover a part of the upper surface electrode 12 and the inorganic protective film 14. The resurface electrode 15 is formed by printing and curing a conductive resin paste made of a mixture of epoxy-based resin and conductive particles such as silver, and the glass frit and the conductive particles are formed. Compared to a mixed and fired electrode material, it does not contain lead and is therefore excellent from the viewpoint of environmental protection. In addition, when compared with metal organic pastes such as gold resinates that are fired at 600 ° C. to 900 ° C., it can be cured at a relatively low temperature of 150 ° C. to 300 ° C., so the power consumption of the heat treatment furnace during production is small. In addition, since an inexpensive material that does not contain gold can be used, the manufacturing cost can also be reduced (re-top electrode formation process in FIG. 2).

次に、図4(b)に示すように、無機保護膜14と薄膜抵抗体13(図示せず)をレーザーを用いて切削することによりトリミング溝16を形成し、抵抗値を所望の値に調整する。この抵抗値調整用のトリミング溝16は、再上面電極15を形成した後に無機保護膜14と薄膜抵抗体13(図示せず)をレーザーを用いて切削することにより形成しているため、薄膜チップ抵抗器の完成抵抗値が導電性樹脂からなる再上面電極15の抵抗値の影響を受けて変動することはなくなり、これにより、抵抗値精度が±0.1%以下という具合に極めて優れている薄膜チップ抵抗器が得られるものである。ここでは、レーザートリミング時に抵抗値を計測するプローブが接触する再上面電極15の厚みは、3μm以上20μm以下となるようにすることが必要である。なぜならば、再上面電極15の厚みが3μmより薄い場合は、プローブと再上面電極15の接触抵抗が大きく抵抗値の測定が安定しないものであり、一方、再上面電極15の厚みが20μmより厚い場合は、再上面電極15の厚み方向の抵抗値が大きくなるため、それに伴う抵抗値の変動により薄膜チップ抵抗器の最終完成品の抵抗値精度が安定しなくなるものである。なお、トリミング溝16を形成するレーザートリミング工程の終了後に、必要に応じてシート状の絶縁基板11cを水系またはアルコール系の洗浄液を用いて洗浄することにより、レーザートリミング工程において発生した滓を除去する洗浄工程を設けてもよいものである(図2のトリミング溝形成工程)。   Next, as shown in FIG. 4B, the inorganic protective film 14 and the thin film resistor 13 (not shown) are cut using a laser to form a trimming groove 16, and the resistance value is set to a desired value. adjust. Since the trimming groove 16 for adjusting the resistance value is formed by cutting the inorganic protective film 14 and the thin film resistor 13 (not shown) using a laser after forming the upper surface electrode 15 again, the thin film chip is formed. The completed resistance value of the resistor does not fluctuate due to the effect of the resistance value of the re-upper surface electrode 15 made of a conductive resin, and the resistance value accuracy is extremely excellent within ± 0.1%. A thin film chip resistor is obtained. Here, it is necessary that the thickness of the re-upper surface electrode 15 that contacts the probe for measuring the resistance value during laser trimming be 3 μm or more and 20 μm or less. This is because, when the thickness of the upper surface electrode 15 is less than 3 μm, the contact resistance between the probe and the upper surface electrode 15 is large and the measurement of the resistance value is not stable, whereas the thickness of the upper surface electrode 15 is larger than 20 μm. In this case, since the resistance value in the thickness direction of the upper surface electrode 15 is increased, the resistance value accuracy of the final product of the thin film chip resistor is not stabilized due to the fluctuation of the resistance value. After the laser trimming process for forming the trimming groove 16, the sheet-like insulating substrate 11c is washed with a water-based or alcohol-based cleaning liquid as necessary to remove wrinkles generated in the laser trimming process. A cleaning step may be provided (trimming groove forming step in FIG. 2).

次に、図4(c)に示すように、無機保護膜14を覆うように熱硬化性樹脂ペーストを印刷して硬化させることにより複数の有機保護膜17を形成する。この有機保護膜17には、必要に応じて抵抗値等の特性を表示する捺印や薄膜チップ抵抗器の方向性判別に用いる認識マークを印刷する。ここでは、図4(c)に示す有機保護膜17は1次分割溝11aとほぼ平行となるように帯状に形成しているが、この有機保護膜17は無機保護膜14の再上面電極15に挟まれた領域を少なくとも覆うように、1次分割溝11aと2次分割溝11bに囲まれた個片領域ごとに独立に形成してもよいものである。なお、この有機保護膜17は後述する裏面電極と同時に硬化させることにより、製造コストを低減させることができる。また、この有機保護膜17は再上面電極15と重なる寸法を200μm以下とするのが好ましい。なぜならば、有機保護膜17における再上面電極15と重なる寸法が200μmを越える場合は、有機保護膜17と再上面電極15の重なっている部分に後述するニッケルめっき層が付かないため、有機保護膜17と再上面電極15の重なっている部分において再上面電極15の抵抗値が薄膜チップ抵抗器の完成抵抗値に直列に加わることになって、薄膜チップ抵抗器の完成抵抗値の精度を保証することが困難になるからである(図2の有機保護膜形成工程)。   Next, as shown in FIG.4 (c), the several organic protective film 17 is formed by printing and hardening a thermosetting resin paste so that the inorganic protective film 14 may be covered. The organic protective film 17 is printed with a mark for displaying characteristics such as a resistance value and a recognition mark used for determining the direction of the thin film chip resistor as necessary. Here, the organic protective film 17 shown in FIG. 4C is formed in a strip shape so as to be substantially parallel to the primary dividing groove 11 a, but the organic protective film 17 is the upper surface electrode 15 of the inorganic protective film 14. Each of the individual regions surrounded by the primary dividing groove 11a and the secondary dividing groove 11b may be formed independently so as to cover at least the region sandwiched between the two. In addition, this organic protective film 17 can reduce manufacturing cost by hardening simultaneously with the back surface electrode mentioned later. Further, it is preferable that the organic protective film 17 has a dimension that overlaps with the upper surface electrode 15 of 200 μm or less. This is because when the dimension of the organic protective film 17 that overlaps with the upper surface electrode 15 exceeds 200 μm, the portion of the organic protective film 17 and the upper surface electrode 15 that overlaps does not have a nickel plating layer that will be described later. In the portion where 17 and the upper surface electrode 15 overlap, the resistance value of the upper surface electrode 15 is added in series with the completed resistance value of the thin film chip resistor, thereby guaranteeing the accuracy of the completed resistance value of the thin film chip resistor. This is because it becomes difficult (the organic protective film forming step in FIG. 2).

ここまで説明したシート状の絶縁基板11cの上面に上面電極12、薄膜抵抗体13、無機保護膜14、再上面電極15、トリミング溝16および有機保護膜17を形成する工程は、いずれもシート状の絶縁基板11cの裏面に何も形成していない状態、すなわちシート状の絶縁基板11cの裏面がフラットな状態で形成しているもので、例えば、上面電極12や再上面電極15を形成する印刷工程においては、シート状の絶縁基板11cを固定するステージへの吸着がより安定した状態で行われるため、基板割れが生じにくくなって、基板割れ等の不良を低減させることができ、これにより、製品の歩留りが向上するものである。また、薄膜抵抗体13と無機保護膜14を形成するマスクスパッタ工程においては、シート状の絶縁基板11cを固定するステージへの吸着がより安定したものとなるため、基板の平行度が向上し、これにより、薄膜抵抗体13と無機保護膜14のパターンの寸法精度も良くなって製品の歩留りが向上するものである。   The steps of forming the upper surface electrode 12, the thin film resistor 13, the inorganic protective film 14, the re-upper surface electrode 15, the trimming groove 16, and the organic protective film 17 on the upper surface of the sheet-like insulating substrate 11c described so far are all sheet-like. In the state where nothing is formed on the back surface of the insulating substrate 11c, that is, the back surface of the sheet-like insulating substrate 11c is formed flat, for example, printing for forming the upper surface electrode 12 and the re-upper surface electrode 15 In the process, since the adsorption to the stage for fixing the sheet-like insulating substrate 11c is performed in a more stable state, the substrate is less likely to be cracked, and defects such as a substrate crack can be reduced. Product yield is improved. Further, in the mask sputtering process for forming the thin film resistor 13 and the inorganic protective film 14, the adsorption to the stage for fixing the sheet-like insulating substrate 11c becomes more stable, so that the parallelism of the substrate is improved. Thereby, the dimensional accuracy of the pattern of the thin film resistor 13 and the inorganic protective film 14 is improved, and the yield of the product is improved.

次に、図5(a)に示すように、シート状の絶縁基板11cの上面に上面電極12、薄膜抵抗体13、無機保護膜14、再上面電極15、トリミング溝16および有機保護膜17を形成した後、シート状の絶縁基板11cの裏面に裏面電極18を形成する。この裏面電極18は、例えばエポキシ系の樹脂と銀等の導電性粒子の混合体からなる導電性樹脂ペーストを印刷して硬化させることにより形成するものであり、鉛を含まないため、環境保護の観点から優れており、また、150℃〜300℃という比較的低温で硬化させることができるため、製造コストも削減できるものである。なお、図5(b)に示すように、裏面電極18を形成する際に、シート状の絶縁基板11cの1次分割溝11a(図示せず)に対応する箇所に裏面電極18を印刷しない箇所、すなわち窓部19を設けてもよいものである。この窓部19の存在によって、後述する分割工程、すなわち1次分割溝11a(図示せず)に沿ってシート状の絶縁基板11cを短冊状に分割する工程においても、裏面電極18にはバリが発生しにくくなり、これにより、形状不良を低減させることができるものである。また、図5(c)に示すように、シート状の絶縁基板11cの裏面に、裏面電極18を2次分割溝11bを跨がないように独立したパターンで形成することにより、2次分割性を向上させるようにしてもよいものである(図2の裏面電極形成工程)。   Next, as shown in FIG. 5A, the upper surface electrode 12, the thin film resistor 13, the inorganic protective film 14, the re-upper surface electrode 15, the trimming groove 16, and the organic protective film 17 are formed on the upper surface of the sheet-like insulating substrate 11c. After the formation, the back electrode 18 is formed on the back surface of the sheet-like insulating substrate 11c. The back electrode 18 is formed, for example, by printing and curing a conductive resin paste made of a mixture of epoxy resin and conductive particles such as silver and does not contain lead. It is excellent from the viewpoint and can be cured at a relatively low temperature of 150 ° C. to 300 ° C., so that the manufacturing cost can be reduced. As shown in FIG. 5B, when the back electrode 18 is formed, a portion where the back electrode 18 is not printed at a location corresponding to the primary division groove 11a (not shown) of the sheet-like insulating substrate 11c. That is, the window portion 19 may be provided. Due to the presence of the window portion 19, the back electrode 18 has burrs even in the dividing step described later, that is, in the step of dividing the sheet-like insulating substrate 11 c into strips along the primary dividing groove 11 a (not shown). It becomes difficult to generate | occur | produce and a shape defect can be reduced by this. Further, as shown in FIG. 5C, by forming the back electrode 18 in an independent pattern on the back surface of the sheet-like insulating substrate 11c so as not to straddle the secondary division grooves 11b, the secondary division property is obtained. May be improved (rear electrode forming step in FIG. 2).

次に、図5(d)に示すように、シート状の絶縁基板11cを1次分割溝11aに沿って分割することにより、図6(a)に示すような短冊状の基板11dを得る(図2の短冊状に分割する工程)。   Next, as shown in FIG. 5D, a sheet-like insulating substrate 11c is divided along the primary dividing groove 11a, thereby obtaining a strip-like substrate 11d as shown in FIG. Step of dividing into strips of FIG. 2).

次に、図6(b)に示すように、上面電極12(図示せず)、再上面電極15および裏面電極18(図示せず)とそれぞれ電気的に接続されるように短冊状の基板11dの両端面に端面電極20を形成する。この端面電極20は、例えばエポキシ系等の樹脂と銀等の導電性粒子の混合体からなる導電性樹脂ペーストを塗布して硬化させることにより形成するものであり、鉛を含まないため、環境保護の観点から優れており、また、端面電極20をスパッタ等の薄膜で形成する場合と比べて安価に製造できるものである(図2の端面電極形成工程)。   Next, as shown in FIG. 6B, the strip-shaped substrate 11d is electrically connected to the upper surface electrode 12 (not shown), the re-upper surface electrode 15 and the back surface electrode 18 (not shown). The end face electrodes 20 are formed on the both end faces. The end face electrode 20 is formed by applying and curing a conductive resin paste made of a mixture of epoxy resin or the like and conductive particles such as silver, and does not contain lead. In view of the above, it can be manufactured at a lower cost compared with the case where the end face electrode 20 is formed of a thin film such as a sputter (end face electrode forming step in FIG. 2).

次に、図6(c)に示すように、短冊状の基板11dを2次分割ライン11bに沿って分割し、個片状の基板11eを得る(図2の個片状に分割する工程)。   Next, as shown in FIG. 6C, the strip-shaped substrate 11d is divided along the secondary dividing line 11b to obtain a piece-like substrate 11e (step of dividing into pieces shown in FIG. 2). .

最後に、図6(d)に示すように、はんだ付け時の信頼性を確保するために、個片状の基板11eの上面、裏面および端面の露出した電極部分にニッケルめっき層21(図示せず)を形成し、さらにこのニッケルめっき層(図示せず)を覆うように錫めっき層22を形成することにより、本発明の一実施の形態における薄膜チップ抵抗器は製造されるものである。なお、上記したニッケルめっき層21を形成する前に銅あるいは銅系合金等の低抵抗率の材料をめっきするようにすれば、めっき部分の抵抗値を下げることができるため、薄膜チップ抵抗器の完成抵抗値精度をさらに上げることが可能となるものである(図2のめっき層形成工程)。   Finally, as shown in FIG. 6 (d), in order to ensure reliability during soldering, a nickel plating layer 21 (not shown) is formed on the exposed electrode portions of the upper surface, the back surface, and the end surface of the individual substrate 11e. The thin film chip resistor in one embodiment of the present invention is manufactured by forming a tin plating layer 22 so as to cover this nickel plating layer (not shown). If a low resistivity material such as copper or a copper-based alloy is plated before the nickel plating layer 21 is formed, the resistance value of the plated portion can be lowered. It is possible to further improve the accuracy of the completed resistance value (plating layer forming step in FIG. 2).

ここで、従来の薄膜チップ抵抗器の製造方法と本発明の一実施の形態における薄膜チップ抵抗器の製造方法において、1608サイズと1005サイズの薄膜チップ抵抗器を製造した結果を(表1)に示す。   Here, the results of manufacturing 1608 size and 1005 size thin film chip resistors in the conventional thin film chip resistor manufacturing method and the thin film chip resistor manufacturing method in one embodiment of the present invention are shown in Table 1. Show.

Figure 2008244211
Figure 2008244211

(表1)から明らかなように、従来の薄膜チップ抵抗器の製造方法においては、薄膜抵抗体13の形成と無機保護膜14の形成に用いるメタルマスクの材質としてステンレスであるSUS430を用いているもので、このSUS430の熱膨張係数は10.4×10-6/℃と大きいため、このSUS430からなるメタルマスクを薄膜抵抗体13の形成と無機保護膜14の形成に繰り返し使用した場合は、メタルマスクが熱履歴を受けて変形することになり、その結果、メタルマスクの位置ずれが発生しやすくなって、薄膜抵抗体13の形成位置もずれやすくなり、これにより、上面電極12と薄膜抵抗体13との電気的接続が保証されない場合があり、特に微小サイズの薄膜チップ抵抗器においては製品歩留りが悪化する傾向が顕著に見られた。 As apparent from Table 1, in the conventional method of manufacturing a thin film chip resistor, SUS430, which is stainless steel, is used as the material of the metal mask used for forming the thin film resistor 13 and the inorganic protective film 14. However, since the thermal expansion coefficient of SUS430 is as large as 10.4 × 10 −6 / ° C., when the metal mask made of SUS430 is repeatedly used for forming the thin film resistor 13 and the inorganic protective film 14, The metal mask is deformed in response to the thermal history, and as a result, the displacement of the metal mask is likely to occur, and the formation position of the thin film resistor 13 is also likely to be displaced. In some cases, the electrical connection with the body 13 may not be guaranteed, and particularly in the case of a small-sized thin film chip resistor, the product yield tends to deteriorate significantly. It was.

一方、本発明の一実施の形態における薄膜チップ抵抗器の製造方法においては、薄膜抵抗体13の形成と無機保護膜14の形成に用いるメタルマスクの材質として42アロイを用いているもので、この42アロイの熱膨張係数は4.5〜6.5×10-6/℃と小さいため、この42アロイからなるメタルマスクを薄膜抵抗体13の形成と無機保護膜14の形成に繰り返し使用しても、メタルマスクが熱履歴を受けて変形するということはなくなり、その結果、メタルマスクの位置ずれも発生しにくくなるため、薄膜抵抗体13の形成位置がずれるということはなくなり、これにより、上面電極12と薄膜抵抗体13との電気的接続が確実に保証され、特に微小サイズの薄膜チップ抵抗器においては製品歩留りが良くなる傾向が顕著に現れるため、信頼性において優れた薄膜チップ抵抗器がコスト的にも安価に得られるという効果を有するものである。 On the other hand, in the method of manufacturing a thin film chip resistor in one embodiment of the present invention, 42 alloy is used as the material of the metal mask used for forming the thin film resistor 13 and the inorganic protective film 14. Since the thermal expansion coefficient of 42 alloy is as small as 4.5 to 6.5 × 10 −6 / ° C., a metal mask composed of 42 alloy is repeatedly used for forming the thin film resistor 13 and the inorganic protective film 14. However, the metal mask is not deformed in response to the thermal history, and as a result, the displacement of the metal mask is less likely to occur, so that the formation position of the thin film resistor 13 is not shifted. The electrical connection between the electrode 12 and the thin film resistor 13 is reliably ensured, and in particular, the tendency to improve the product yield is prominent in a small-sized thin film chip resistor. , Thin film chip resistor which is excellent in reliability in which an effect that is obtained inexpensively in cost.

なお、上記本発明の一実施の形態においては、上面にあらかじめ1次分割溝11aと2次分割溝11bを設けたシート状の絶縁基板11cを用いて製造する方法について説明したが、この製造方法に限定されるものではなく、分割溝をあらかじめ有しないノンスリット基板の上面および裏面に機能素子を形成した後にダイシング工法を用いて基板を切断し、所望の形状を得るようにしてもよいものである。   In the above-described embodiment of the present invention, the method of manufacturing using the sheet-like insulating substrate 11c in which the primary divided grooves 11a and the secondary divided grooves 11b are provided on the upper surface in advance has been described. It is not limited to the above, and a functional element may be formed on the upper and rear surfaces of a non-slit substrate that does not have division grooves in advance, and then the substrate may be cut using a dicing method to obtain a desired shape. is there.

また、上記本発明の一実施の形態においては、1個の薄膜チップ抵抗器に1個の薄膜抵抗体13を有する構成について説明したが、この構成に限定されるものではなく、1個の薄膜チップ抵抗器に複数個の薄膜抵抗体13を有する多連またはネットワークタイプの構成においても本発明は適用できるものである。   In the above-described embodiment of the present invention, the configuration in which one thin film resistor is provided with one thin film resistor 13 is not limited to this configuration. The present invention can also be applied to a multiple or network type configuration having a plurality of thin film resistors 13 in a chip resistor.

本発明に係る薄膜チップ抵抗器の製造方法は、薄膜抵抗体を形成するメタルマスクを熱膨張係数の小さい42アロイで構成することにより、薄膜抵抗体の形成位置のずれを防止して上面電極と薄膜抵抗体との電気的接続が確実に保証されるようにしたものであり、特に薄膜チップ抵抗器の製造方法において有用なものである。   The method of manufacturing a thin film chip resistor according to the present invention comprises a metal mask for forming a thin film resistor made of 42 alloy having a small coefficient of thermal expansion, thereby preventing the displacement of the formation position of the thin film resistor and the upper surface electrode. The electrical connection with the thin film resistor is surely ensured, and is particularly useful in the method of manufacturing the thin film chip resistor.

本発明の一実施の形態における薄膜チップ抵抗器の断面図Sectional drawing of the thin film chip resistor in one embodiment of this invention 同薄膜チップ抵抗器の製造方法を示すフローチャートFlow chart showing the manufacturing method of the thin film chip resistor (a)〜(c)同薄膜チップ抵抗器の製造方法を示す製造工程図(A)-(c) Manufacturing process figure which shows the manufacturing method of the thin film chip resistor (a)〜(c)同薄膜チップ抵抗器の製造方法を示す製造工程図(A)-(c) Manufacturing process figure which shows the manufacturing method of the thin film chip resistor (a)〜(d)同薄膜チップ抵抗器の製造方法を示す製造工程図(A)-(d) Manufacturing process figure which shows the manufacturing method of the thin film chip resistor (a)〜(d)同薄膜チップ抵抗器の製造方法を示す製造工程図(A)-(d) Manufacturing process figure which shows the manufacturing method of the thin film chip resistor 従来の薄膜チップ抵抗器の断面図Cross-sectional view of a conventional thin film chip resistor 同薄膜チップ抵抗器の製造方法を示すフローチャートFlow chart showing the manufacturing method of the thin film chip resistor

符号の説明Explanation of symbols

11 絶縁基板
11c シート状の絶縁基板
11d 短冊状の基板
11e 個片状の基板
12 上面電極
13 薄膜抵抗体
14 無機保護膜
15 再上面電極
16 トリミング溝
17 有機保護膜
18 裏面電極
20 端面電極
DESCRIPTION OF SYMBOLS 11 Insulation board | substrate 11c Sheet-like insulation board | substrate 11d Strip-shaped board | substrate 11e Single piece board | substrate 12 Upper surface electrode 13 Thin film resistor 14 Inorganic protective film 15 Re-upper surface electrode 16 Trimming groove 17 Organic protective film 18 Back surface electrode 20 End surface electrode

Claims (1)

シート状の絶縁基板の上面に有機金属ペーストを印刷して焼成することにより複数の上面電極を形成する工程と、前記複数の上面電極の少なくとも一部を覆い、かつこの複数の上面電極と電気的に接続されるように複数の薄膜抵抗体を形成する工程と、前記複数の薄膜抵抗体を覆うように複数の無機保護膜を形成する工程と、前記複数の上面電極を覆うように導電性樹脂ペーストを印刷して硬化させることにより複数の再上面電極を形成する工程と、前記複数の無機保護膜を覆うように熱硬化性樹脂ペーストを印刷して硬化させることにより複数の有機保護膜を形成する工程と、前記シート状の絶縁基板の裏面に導電性樹脂ペーストを印刷して硬化させることにより複数の裏面電極を形成する工程と、前記シート状の絶縁基板を分割して短冊状の基板を得る工程と、前記短冊状の基板の端面に前記上面電極、前記再上面電極、前記裏面電極と電気的に接続されるように導電性樹脂ペーストを塗布して硬化させることにより端面電極を形成する工程とを備え、前記シート状の絶縁基板の上面に42アロイで構成したメタルマスクを設置して前記薄膜抵抗体をマスクスパッタで形成し、その後、前記メタルマスクを取り外さずに続けて無機保護膜をマスクスパッタで形成した薄膜チップ抵抗器の製造方法。 Forming a plurality of upper surface electrodes by printing and baking an organic metal paste on the upper surface of the sheet-like insulating substrate; covering at least a part of the plurality of upper surface electrodes; Forming a plurality of thin film resistors so as to be connected to each other, forming a plurality of inorganic protective films so as to cover the plurality of thin film resistors, and a conductive resin so as to cover the plurality of upper surface electrodes A step of forming a plurality of resurface electrodes by printing and curing the paste, and a plurality of organic protective films by printing and curing a thermosetting resin paste so as to cover the plurality of inorganic protective films A step of forming a plurality of backside electrodes by printing and curing a conductive resin paste on the backside of the sheet-like insulating substrate, and dividing the sheet-like insulating substrate into strips And an end face electrode by applying and curing a conductive resin paste on the end face of the strip-like board so as to be electrically connected to the upper face electrode, the upper face electrode, and the rear face electrode. And forming a thin film resistor by mask sputtering on the upper surface of the sheet-like insulating substrate to form the thin film resistor, and then continuing without removing the metal mask. A method of manufacturing a thin film chip resistor in which an inorganic protective film is formed by mask sputtering.
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WO2012114673A1 (en) * 2011-02-24 2012-08-30 パナソニック株式会社 Chip resistor and method of producing same
JP2013070108A (en) * 2013-01-23 2013-04-18 Taiyosha Electric Co Ltd Chip resistor

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JPH0745662A (en) * 1993-07-30 1995-02-14 Hitachi Ltd Adhering structure for metal mask
JPH08213221A (en) * 1994-11-10 1996-08-20 Matsushita Electric Ind Co Ltd Manufacture of rectangular thin film chip resistor
JP2002064002A (en) * 2000-06-05 2002-02-28 Rohm Co Ltd Chip resistor and its manufacturing method
JP2004221437A (en) * 2003-01-17 2004-08-05 Sanyo Electric Co Ltd Photovoltaic device and manufacturing method thereof

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JPH0745662A (en) * 1993-07-30 1995-02-14 Hitachi Ltd Adhering structure for metal mask
JPH08213221A (en) * 1994-11-10 1996-08-20 Matsushita Electric Ind Co Ltd Manufacture of rectangular thin film chip resistor
JP2002064002A (en) * 2000-06-05 2002-02-28 Rohm Co Ltd Chip resistor and its manufacturing method
JP2004221437A (en) * 2003-01-17 2004-08-05 Sanyo Electric Co Ltd Photovoltaic device and manufacturing method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012114673A1 (en) * 2011-02-24 2012-08-30 パナソニック株式会社 Chip resistor and method of producing same
JPWO2012114673A1 (en) * 2011-02-24 2014-07-07 パナソニック株式会社 Chip resistor and manufacturing method thereof
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JP2013070108A (en) * 2013-01-23 2013-04-18 Taiyosha Electric Co Ltd Chip resistor

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