JP2008243220A - Information processing communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor capable of attaining a low electric power consumption, without worsening a response speed in an interruption request. <P>SOLUTION: The information processor for assigning a time up to prescribed event execution to call a system has the first timer circuit 9a set to the first period, the second timer circuit 9b set to the second period shorter than the first period, a time-out monitoring part 71 capable of storing a generation time when the system is called, and a first period monitoring part 72 capable of storing a time up to the interruption request of the first timer circuit 9a when the system is called. The time-out monitoring part stores a time provided by subtracting the time stored in the first period monitoring part from the time stored in the time-out monitoring part by the interruption request of the first timer circuit, and subtracts the time of the second period from the time stored in the time-out monitoring part by the interruption request of the second timer circuit, when the time stored in the time-out monitoring part is shorter than the first period. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an information processing communication device and an operating system.

  FIG. 16 is a block diagram showing a conventional wireless communication apparatus disclosed in Japanese Patent Laid-Open No. 11-355198.

  In FIG. 16 of the present application, a central processing unit CPU (hereinafter referred to as a processor) (1), a frame synchronization circuit SYN (hereinafter referred to as a synchronization circuit) (2), a reception circuit RCV (3), a register (control means) REG ( 4) a switching circuit SWC (5), a high-speed oscillation circuit OSC (6) that oscillates and outputs a high-speed clock CK, and a real-time clock RTC (hereinafter referred to as RTC) having a timer function used as a clock function of a wireless communication device. ) (7), input / output circuit I / O (hereinafter referred to as I / O) (8), timer TIM (9), interrupt circuit INTC (10), bus for transmitting and receiving address, data and control data (11) Is described.

  The switching circuit SWC (5) is based on the control data written and stored in the register REG (4) by the processor CPU (1), or the clock CK1 output from the high-speed oscillation circuit OSC (6) or RTC ( 7) Select one of the clocks CK2 output from 7), and supply the selected clock to the processor CPU (1), the synchronization circuit SYN (2), and the register REG (4).

  The timer TIM (9) always operates based on the clock CK2 output from the RTC (7), and receives the clock CK2 output from the RTC (7) during the intermittent period after receiving the paging channel (sleep mode). The supply time is set by the processor CPU (1). Further, when the timer TIM (9) times out, it outputs an interrupt control signal to the interrupt circuit INTC (10), and sets the interrupt circuit INTC (10) to the interrupt state.

  When the interrupt circuit INTC (10) inputs the interrupt control signal output from the timer TIM (9), or when the user operates the key and the key interrupt is input via the I / O (8) When the interrupt circuit INTC (10) receives the interrupt request, the processor CPU (1) is notified of the occurrence of the interrupt request, that is, the interrupt request from the interrupt circuit INTC (10) is sent to the processor CPU (1). Is output.

  After the timer value is set to the timer TIM (9) by the processor CPU (1), the processor CPU (1) writes the control data to the register REG (4). As a result, the switching circuit SWC (5) causes the clock CK1 output from the high-speed oscillation circuit OSC (6) to be output from the RTC (7) based on the control data stored in the register REG (4). Switching to CK2, the clock CK2 is output to the processor CPU (1), the synchronization circuit SYN (2), the register REG (4) and the like. As described above, the processor CPU (1), the synchronization circuit SYN (2), the register REG (4), and the like operate based on the clock CK2. Further, the operation of the high-speed oscillation circuit OSC (6) is stopped based on the control data written in the register REG (4).

  When the interrupt request output from the interrupt circuit INTC (10) is input, the processor CPU (1) determines from which circuit the interrupt request is output. If the interrupt request is an interrupt request output from a circuit other than the timer TIM (9), processing is performed based on the clock CK1, and the arrival of the next interrupt request is awaited.

  When the received interrupt request is an interrupt request output from the timer TIM (9), the processor CPU (1) writes control data in the register REG (4). Based on the control data written in the register REG (4), the switching circuit SWC (5) uses the clock CK2 output from the RTC (7) and the clock CK1 output from the high-speed oscillation circuit OSC (6). Switch to. The switched clock CK1 is supplied to the processor CPU (1), the synchronization circuit SYN (2), the register REG (4), and the like.

Japanese Patent Laid-Open No. 11-355198

  Prior to the present application, the inventors of the present application examined the above-described conventional technology. In addition, since there are information processing apparatuses equipped with e-mail, browser, video / audio / acoustic recording / playback, and the like, the inventors of the present application use the wireless communication apparatus disclosed in Patent Document 1 as an information processing communication apparatus. The same applies to the case of application. When the conventional wireless communication apparatus is applied to an information processing communication apparatus, a memory MEM (21) is mounted on the wireless communication apparatus of FIG. 16, and the memory MEM (21) has an operating system OS (hereinafter referred to as OS). (Omitted) (22) must be equipped. Then, the OS (22) performs time monitoring and management of the information processing communication device by generating an interrupt request for every arbitrary period from the timer TIM (9).

  Here, it has been found that two problems remain in the periodic interrupt request of the timer TIM (9) mounted on the information processing communication apparatus to which the wireless communication apparatus of FIG. 16 and the conventional wireless communication apparatus are applied.

  The first problem is that the power saving mode is canceled according to the period of the periodic interrupt request of the timer TIM (9) and the clocks CK1 and CK2 are supplied to the processor CPU (1) in spite of being in the power saving mode. It is an event that consumes. Hereinafter, this phenomenon will be described with reference to FIG.

  FIG. 17 shows the current consumption (41) in each operation mode of the processor CPU (1). Here, 42 indicates a timer interrupt request mode, and 43 indicates a power saving mode. When the OS (22) has a multitasking function, a process for applying the power saving mode (43) during an infinite loop of the lowest priority task is set. It is assumed that there is an idle state in which the clock CK1 is supplied to the processor CPU (1), that is, it is not used for a while in a scene that can be used for information processing, or there is a margin time until the deadline. The time in the timer interrupt request mode 42 from the time when a timer interrupt occurs until the next timer interrupt occurs is referred to as a timer interrupt duty.

  Here, in order to prevent wasteful consumption of current, when the lowest priority task is started in the idle state, the power saving mode (43) is canceled by the timer interrupt request mode (42) from the timer TIM (9). The clock CK1 is supplied to the processor CPU (1), the CPU starts operating, and the current consumption (41) increases in the scene where it is originally desired to reduce the current. In the event, it is possible to reduce the number of interrupt requests of the timer (9) by lengthening the timer period (44), lengthen the time of the power saving mode (43), and suppress the current consumption (41). .

  However, the OS (22) performs time monitoring and management while counting with the system clock (24) internally at every periodic interrupt request by the timer TIM (9). Therefore, it was found that if the timer period (44) of the timer TIM (9) is lengthened, the time accuracy is deteriorated in order to release the waiting task by time-out within a time shorter than the timer period (44). In other words, it has been found that if the current consumption (41) is suppressed, the time accuracy deteriorates, and conversely, if the time accuracy is improved, the current consumption (41) increases.

  The second problem is an event in which an interrupt is always generated from the timer TIM (9) every timer cycle (44), and is therefore interrupted by the generation of an interrupt request from the other I / O circuit (8).

  In particular, when priority is given to time management, that is, when the interrupt request level of the timer TIM (9) is increased, the interrupt circuit INTC (10) first receives the periodic interrupt request of the timer TIM (9) and processes the periodic interrupt request. Immediately after ending the process, an interrupt request from I / O (8) is accepted and processing related to I / O is performed. Therefore, it was found that the interrupt response becomes dull.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, an information processing apparatus that makes a system call by designating an occurrence time until execution of a predetermined event, and is set to a first timer circuit set to a first cycle and a second cycle shorter than the first cycle. The second timer circuit, the timeout monitoring unit capable of storing the occurrence time when the system call is made, and the next timer timer interrupt when the system call is made A first cycle monitoring unit capable of storing a time until a request, wherein the timeout monitoring unit monitors the first cycle from the time stored in the timeout monitoring unit by an interrupt request of the first timer When the time stored in the timeout monitoring unit is shorter than the first period, the interrupt request of the second timer circuit is received. Further, the time of the second period is subtracted from the time stored in the timeout monitoring unit.

  More preferably, when the time stored in the timeout monitoring unit is longer than the first period, the second timer circuit disables an interrupt request, and the time stored in the timeout monitoring unit is the first time. It may be configured such that an interrupt request is permitted when it is determined that the period is shorter than the cycle.

  More preferably, the first cycle monitoring unit may be configured to be able to input a cycle time of the first cycle.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, by implementing the present invention, it is possible to achieve a reduction in power consumption of the information processing apparatus and an improvement in the response speed of interrupts.

  First, the idea of the present invention will be described with reference to FIGS. FIG. 1 shows an embodiment of a basic configuration for realizing the present invention. A memory MEM (21), I, and a processor CPU (1), a plurality of timers TIM (9), and an OS (22) are mounted. / O (8), bus (11) are shown. Further, one block composed of the processor CPU (1), a plurality of timers TIM (9), I / O (8), and the bus (11) is regarded as the processor CPU (1), and the processor CPU (1) and the memory MEM It is also possible to regard (21) as a circuit connected by the bus (11).

  The plurality of timers TIM (9) includes a first timer TIM1 (9a) and a second timer TIM2 (9b). The first timer TIM1 (9a) includes a status register SREG1 (81a), a control register CREG1 (82a), a counter CNT1 (83a), and a cycle setting register CYCREG1 (84a). The second timer TIM2 (9b) has the same configuration as the first timer TIM1 (9a). The clock CK (85) is a clock signal from the oscillation circuit. The clock CK2 is always input from the RTC (7) to the timer TIM (9). However, depending on the application, the clock CK1 output from the high-speed oscillation circuit OSC (6) is input without being limited to the RTC (7). It doesn't matter.

  The status registers SREG 1 and 2 (81) inform each timer of the internal state of the timer, such as determining whether an underflow has occurred in the counters TIM 1 and 2 (83), enabling or disabling timer interrupts, etc. Have

  The control register CREG (82) sets the timer interrupt permission prohibition when the counter CNT (83) underflows for each timer, sets the frequency division ratio of the clock CK (85) required for the timer drive, and the timer counts It has information for enabling the period to perform. Note that the status register SREG and the control register CREG can be set from the outside.

  The counter CNT (83) has a function in which each timer counts down (subtracts) the initial set value in synchronization with the frequency division ratio with respect to the clock CK (85) set by the control register (82). The counter (83) may be either a count down system or a count up system. The count-up method has a function of counting up (adding) values.

  The period setting register (84) has information for setting the length of the period for generating an interrupt at the initial time or underflow for each timer. If the counter (83) is a count-up system, it is not an underflow but an overflow.

  FIG. 1 shows the OS time management unit (91) as a part of the function of the OS (22). The OS time management unit (91) includes a task information control table (hereinafter referred to as TCB) management unit (92), a timeout request issue processing unit (93), a first timer interrupt processing unit (94), and a second timer interrupt processing unit. (95), a first cycle monitoring unit (72), a system clock (24), and the like. The TCB management unit (92) includes a timeout monitoring unit (71).

  FIG. 2 is a diagram for explaining the concept of the present invention. Hereinafter, the present invention will be described with reference to FIG. 2 includes a counter axis (61), a time axis (62), a counter value (63), a cycle set value (64), an interrupt generation (65), a timeout request issue time (66), a timeout time (67), A timeout request time (68), a timeout monitoring unit (71), a first cycle monitoring unit (72), and a time monitoring rate storage unit (73) are shown.

  For the first timer TIM1 (9a), the first timer period (44a), counter value (63a), period set value (64a), interrupt generation (65a), second timer TIM2 (9b) for the second timer The period (44b), counter value (63b), period setting value (64b), and interrupt generation (65b) are shown.

  The timeout monitoring unit (71), the first cycle monitoring unit (72), and the time monitoring rate storage unit (73) are provided in the memory (21), although not particularly limited. The values stored in the timeout monitoring unit, the first cycle monitoring unit, and the like are values corresponding to the counter values in the first timer and the second timer. These values are equivalent to the time obtained by multiplying the period of the clock input to the first timer or the second timer by the value of the counter. Accordingly, it can be said that the time-out monitoring unit, the first cycle monitoring unit, and the like store the time corresponding to each.

  First, at initialization, the OS (22) sets the timer TIM (9) so that the first timer period (44a) is an integral multiple of the second timer period (44b), and stores it in the time monitoring rate storage unit (73). A value obtained by dividing the first timer period (44a) by the second timer period (44b) is stored. Furthermore, the status register SREG2 (81b) of the second timer TIM2 (9b) is set so that only the second timer TIM2 (44b) prohibits the generation of an interrupt (65b). Next, the timeout request time (68) is stored in the timeout monitoring unit (71) at the timeout request issuance time (66) when the timeout request is issued by the OS (22).

  Each time a timer interrupt occurs from the first timer TIM1 (9a), the first timer period (44a) is subtracted from the value stored in the timeout monitoring unit (71), and the subtraction value is again sent to the timeout monitoring unit (71). Store.

  When the value stored in the timeout monitoring unit (71) becomes smaller than the first timer period (44a), the timer interruption from the second timer TIM2 (9b) is permitted, and the first period monitoring unit (72 ) Is set to the first timer period (44a).

  Each time a timer interrupt is generated from the second timer TIM2 (9b), the second timer period (44b) is subtracted from the respective values stored in the timeout monitoring part (71) and the first period monitoring part (72), The respective subtraction values are stored again in the timeout monitoring unit (71) and the first cycle monitoring unit (72).

  The time when the value stored in the time-out monitoring unit (71) becomes 0 or less is the time-out time, and the time-out request can be satisfied.

  As described above, the first timer period (44a) having a long period and the second timer period (44b) having a short period are provided, and the time is roughly monitored in the first timer period (44a) and the occurrence of an interrupt (65) is suppressed. By performing fine time monitoring in the second timer cycle (44b), it is possible to suppress current consumption due to timer interruption for the processor (1) in the power saving mode while maintaining time management accuracy. Become. In other words, when measuring a predetermined time from the end of the first event to the occurrence of the second event, the count is started at the first cycle with a long period, and the remaining time until the second event occurs is the first period. The present invention can be achieved by configuring to count in the second period when it becomes shorter than the interval.

  For example, the first cycle of the timer interrupt request is 10 [msec], the second cycle is 1 [msec], the conventional timer interrupt request cycle (44) is 1 [msec] cycle, and the current consumption value at the time of the interrupt request ( Assuming that 46) is 150 [mA] and the current consumption value in the low power consumption mode is 35 [mA], if the TMU interrupt duty is 1%, the current consumption improvement rate will be about 2% and 5%. If the current improvement rate is about 12% or 10%, the current consumption improvement rate is about 18%, and if it is 15%, the current consumption improvement rate can be estimated to be about 25%. This is effective in extending the battery life and suppressing heat generated by the processor.

  Also, as described above, by reducing the occurrence of timer interrupts, the occupancy rate of the OS (22) processing is reduced, and it can be spent on other (interrupt) processing.

  Next, the processing procedure of the present invention will be described in detail with reference to FIGS. FIG. 3 shows the TCB management unit (92). The TCB management unit (92) includes, for example, a processing pointer (101), an insertion pointer (102), a temporary storage unit (103), a ready queue header (104), a wait queue header (105), a timer queue header (106), in order It consists of a direction pointer (107), a backward pointer (108), and one or more TCBs (109). There are as many TCBs (109) as the number of tasks generated and operated by the OS (22). For example, in this embodiment, there are three tasks (TCBs 109a, 109b, and 109c). The timer queue header (106) includes a forward pointer (107), a backward pointer (108), and a first cycle monitoring unit (72). In order to simplify the description here, the first time-out TCB is 109a, and the next time-out TCB is 109b. The TCB 109c is a newly generated task.

  The TCB (109a, b, c) is composed of a plurality of forward pointers (107) and backward pointers (108) according to applications, a timeout monitoring unit (71), and the like. The forward pointer (107) of the timer queue header (106) indicates the memory address of the forward pointer (107a) of the TCB (109a) that has the earliest time-out required for releasing the waiting task. The forward pointer of the TCB (109a) indicates the memory address of the forward pointer (107b) of the TCB (109b) of the task that will time out next. The backward pointer (108b) of the pointed TCB (109b) points to the memory address of the backward pointer (108a) of the TCB (109a) of the task that is released from the wait state by the previous timeout. Therefore, the forward pointer (107) of the timer queue header (106) points to the TCB (109a) of the task that times out earliest, and conversely, the backward pointer (108) points to the TCB (109c) of the task that times out latest. Will point. That is, the TCB management unit (72) forms a bidirectional list of each TCB (109) starting from the timer queue header (106) (sentinel).

  The time-out monitoring unit (71) stores the remaining time of the TCB (109) until the time-out after the TCB (109) of the task previously linked to the bidirectional list times out. That is, the remaining time stored in the timeout monitoring unit (71b) indicates the remaining time until the timeout immediately after the TCB (109a) is released from waiting, and the remaining time stored in the timeout monitoring unit (71c) is , TCB (109b) indicates the remaining time from the time immediately after the wait is released to the time-out. Incidentally, the TCB (109) forms a bidirectional list in order of task priority with the ready queue header (104) at the head, and forms a bidirectional list with the wait queue header (105) in the order of arrival.

  The processing pointer (101) indicates the memory address of the TCB (109) currently being processed. The OS time management unit (91) sets in advance the processing pointer (101) to point to the same memory address as the timer queue header (106) at the time of initialization. Here, for the sake of explanation, it is assumed that the timer queue header (106) already points to the TCB (109a) as shown in FIG. The insertion pointer (102) points to the memory address of the new TCB (109c). The time monitoring rate storage unit (73) stores a value obtained by dividing the value of the first timer period (44a) by the value of the second timer period (44b).

  FIGS. 4 to 8 are flowcharts for explaining the flowchart of the timeout request issue processor (93). FIG. 4 shows the entire process of the timeout request issue processor (93). The time-out request issuance processing unit (93) is processed in the system call when the system call for requesting the time-out of the equipment to the OS (22) is issued. First, in the present invention, the status register SREG2 (81b) of the second timer TIM2 (9b) is referenced to determine whether the interrupt generation status from the second timer TIM2 (9b) is enabled or disabled (discriminating process 124). That is, it is determined here whether or not the counting is performed according to the second timer TIM2 (9b). If it is prohibited (counting according to the first timer TIM1 (9a)), the process proceeds to the process (201). If permitted (counting according to the second timer TIM2 (9b)), the process proceeds to the process (202).

  FIG. 5 is a flowchart for explaining the process (201), that is, the process executed when the interrupt generation state from the second timer TIM (9b) is prohibited. If it is determined in the determination process (124) that the interrupt from the second timer TIM2 (9b) is prohibited, the remaining time from the current time until the next first timer TIM (9b) interrupts is obtained to monitor the first period. Part (72). Specifically, the control register CREG2 (82b) is set so as to allow the interrupt generation from the second timer TIM2 (9b), and then the value of the counter CNT1 (83a) of the first timer TIM1 (9a) is set. The value obtained by dividing 1 by the value obtained by adding 1 to the value of the timer period (44b) set in the period setting register CYCREG2 (84b) of the second timer TIM2 (9b) is sent to the first period monitoring unit (72). Store (process 203).

  Next, it is determined whether the timer queue header (106) of the TCB management unit (92) points to the memory address of the TCB (109), that is, whether there is a task waiting for a timeout (hereinafter referred to as a waiting task). (Determination processing 125). If it points to the memory address of the TCB (109) (if there is a waiting task), the processing proceeds to processing (204), and if not (if there is no waiting task), the processing proceeds to processing (205).

  FIG. 6 is a flowchart for explaining a process (204) for newly setting a timeout when there is a timeout waiting task. In the determination process (125), when it is determined that there is a waiting task, first the first period monitoring unit (72) and the time monitoring rate storage unit ( 73), a subtraction value obtained by subtracting the value stored in the first period monitoring unit (72) from the value stored in the time monitoring rate storage unit (73) is obtained. Then, the subtraction value is subtracted from the value stored in the timeout monitoring unit (71) of the TCB (109) pointed to by the processing pointer (101), and the subtraction value is stored in the timeout monitoring unit (71) ( Process 206).

  Next, in order to compare the remaining time until the timeout between the task for which the timeout is newly set and the task for which the timeout has already been set, the timeout monitoring unit (71c) of the TCB (109c) newly requesting the timeout And the magnitude of the value stored in the timeout monitoring unit (71) of the TCB (109) pointed to by the processing pointer (101) is discriminated (discriminating process 126). The timeout request time (68) is already stored in the timeout monitoring unit (71c) of the TCB (109c) that newly requested the timeout. If the timeout monitoring unit (71c) is larger, the process proceeds to the process (207), and if smaller, the process proceeds to the process (208). At this time, the TCB (109c) is not inserted in the bidirectional list of the TCB management unit (92).

  The value stored in the timeout monitoring unit (71c) of the new TCB (109c) in the discrimination process (126) is stored in the timeout monitoring unit (71) of the TCB (109) pointed to by the processing pointer (101). If it is larger, in order to temporarily update the remaining time-out time of the task newly set as time-out, the processing pointer (101) points to the value stored in the time-out monitoring unit (71c) of the TCB (109c). The subtraction value obtained by subtracting the value stored in the timeout monitoring unit (71) of the TCB (109) is stored in the timeout monitoring unit (71) of the TCB (109c), and the processing pointer (101) is set to the current processing pointer ( 101) is set to the memory address of the TCB (109) pointed to by the forward pointer (107) of the TCB (109) pointed to by (101) (process 207).

  Next, in order to determine whether or not all the remaining timeout times of tasks for which timeouts have already been set have been investigated, whether the processing pointer (101) points to the memory address of the timer queue header (106), that is, connected to the timer queue It is determined whether or not the process 207 has been performed on the TCB (109) (determination process 127). If it indicates the memory address of the timer queue header (106), the process proceeds to the process (208), and if not, the process returns to the discrimination process (126).

  In the determination process (127), when it is determined that the process pointer (101) points to the memory address of the timer queue header (106), the process is performed in order to insert the newly timed-out task into the timer queue. The memory address of the TCB (109) pointed to by the pointer (101) is replaced with the memory address of the TCB (109c), and the memory address of the TCB (109) set before the setting is changed in the order of the TCB (109c). The direction pointer (107c) is set to point (process 208). That is, the TCB (109c) is inserted into the bidirectional list of the TCB management unit (92). The setting is changed so that the backward pointer is also inserted.

  Next, the forward pointer (107c) of the TCB (109c) pointed to by the insertion pointer (102) is updated in order to update the remaining time until the timeout of the task timed out next to the task newly inserted into the timer queue. The processing pointer (101) is set at the TCB (109) memory address pointed by (), and the insertion pointer (71) is determined from the value of the timeout monitoring unit (71) of the TCB (109) pointed to before the setting by the processing pointer (101). 102), the subtraction value obtained by subtracting the value stored in the timeout monitoring unit (71c) of the TCB (109c) pointed to by 102) is stored in the timeout monitoring unit (71) of the TCB (109) pointed to by the processing pointer (101). (Process 209). In this way, a new TCB (109c) is inserted into the processing routine.

  FIG. 7 is a diagram illustrating a flowchart of the process (205) in the case where the newly set timeout is timed out in the shortest time. First, in order to determine whether there is a task waiting for timeout other than the task for which timeout has been newly set, the backward pointer (108) of the TCB (109) pointed to by the insertion pointer (102) is set to the timer queue header (106). ) (Determination process 128). If the backward pointer (108) of the TCB (109) pointed to by the insertion pointer (102) points to the timer queue header (106), the process proceeds to the discrimination process (129). If not, the process (205) is terminated. To do.

  In the determination process (128), when it is determined that the backward pointer (108) of the TCB (109) pointed to by the insertion pointer (102) points to the timer queue header (106), a new timeout is set. In order to determine the remaining time of the task and the value of the first cycle monitoring unit, the value of the timeout monitoring unit (71) of the TCB (109) pointed to by the insertion pointer (102) is set to the first cycle monitoring unit ( 72) is determined (determination process 129). Here, if the value of the timeout monitoring unit (71) of the TCB (109) pointed to by the insertion pointer (102) is equal to or larger than the value of the first cycle monitoring unit (72), the process proceeds to the processing (210). The process (205) is terminated. The process (210) generates an interrupt from the second timer TIM2 (9b) in the control register CREG2 (82b) of the second timer TIM2 (9b) in order to set the interrupt of the first timer TIM1 (9a) to be prohibited. Set to prohibited.

  FIG. 8 is a diagram for explaining a flowchart of the process (202). The process (202) refers to the status register SREG2 (81b) of the second timer TIM2 (9b), and shifts to the process when the interrupt generation status from the second timer TIM2 (9b) is enabled (see FIG. 4). ). Since this process (202) is the same as the process described with reference to FIGS.

  FIG. 9 is a diagram illustrating a flowchart of the first timer interrupt processing unit. When the first timer interrupt processing unit (94) generates the first timer interrupt (65a), the first timer interrupt processing unit (94) performs the following processing to activate the processor (1). First, in order to set the timer cycle of the first timer in the first cycle monitoring unit (72), both the first timer TIM1 (9a) and the second timer TIM2 (9b) are counter CNT ( 83) is set so as not to underflow, the value of the first cycle monitoring unit (72) is stored in the temporary storage unit (103), and the value stored in the time monitoring rate storage unit (73) is stored in the first cycle monitoring unit. (72) (process 221).

  Next, in order to determine whether there is a task waiting for timeout, it is determined whether the timer queue header (106) of the TCB manager (92) points to the memory address of the TCB (109), that is, whether there is a task waiting. Discrimination is performed (discrimination processing 125).

  In the determination process (125), when it is determined that the timer queue header (106) points to the memory address of the TCB, in order to update the remaining time until the timeout of the task that times out earliest, the processing pointer ( 101) is set to the memory address of the TCB (109) pointed to by the forward pointer (107) of the timer queue header (106), and the time-out monitoring unit (71) of the TCB (109) pointed to by the processing pointer (101) is set. A process (222) of subtracting a value obtained by subtracting the value stored in the temporary storage unit (103) from the stored value into the timeout monitoring unit (71) of the TCB (109) pointed to by the process pointer (101).

  Next, the timeout processing (223) of the task that times out earliest is performed. The process (223) will be described with reference to FIG. First, in order to switch from the processing pointer for timeout request issuance processing to the processing pointer for timer interrupt, the processing pointer (101b) should be pointed to the same memory address as the memory address of TCB (109) pointed to by the processing pointer (101a). Setting is made (process 225). Next, in order to determine whether it is the time-out time, it is determined whether the value of the time-out monitoring unit (71) of the TCB (109) pointed to by the processing pointer (101a) is 0 or less (determination process 142). If the value of the timeout monitoring unit (71) of the TCB (109) pointed to by the process pointer (101a) is 0 or less, the process proceeds to the process (226). Otherwise, the process proceeds to the process (227).

  In the discrimination process (142), when the value of the timeout monitoring unit (71) is determined to be 0 or less, the TCB (109) pointed to by the process pointer (101a) is used to release the TCB from the timer queue and time out. Is deleted from the bidirectional list of the TCB management unit (92), and post-processing of the bidirectional list of the TCB management unit (92) is performed (processing 226).

  Thereafter, the processing pointer (101a) points to the memory address of the TCB (109) pointed to by the forward pointer (108) of the TCB (109) pointed to by the processing pointer (101b) to be shifted to the next time-out TCB. Then, timeout processing is performed (processing 227).

  After the process (227) is completed (after the process 223 in FIG. 9 is completed), the process pointer (101b) is set to the memory address of the timer queue header (107) in order to determine whether or not all the waiting task timeout states have been investigated. Is determined (determination process 141). If so, the process proceeds to the process (224), and if not, the process returns to the process (223).

  FIG. 11 is a diagram for explaining the flowchart of the process (224). First, in order to determine whether there is a waiting task, it is determined whether the forward pointer (107) of the timer queue header (106) points to the memory address of the timer queue header (106) (determination process 143). . If so, the process proceeds to processing (228), and if not, the process proceeds to discrimination processing (144).

  In the determination process (143), when it is determined that the forward pointer (107) does not point to the memory address of the timer queue header, the remaining time until the timeout of the task that times out earliest is longer than the first cycle monitoring unit In order to determine whether the value is larger, the value stored in the timeout monitoring unit (71) of the TCB (82) pointed to by the forward pointer (83) of the timer queue header (106) is the first cycle monitoring unit (72). It is determined whether or not the value is greater than or equal to (determination process 144). If the value is equal to or greater than the value of the first cycle monitoring unit (72), the process proceeds to the process (228). Otherwise, the process (224) is terminated.

  When it is determined in the determination process (143) that the forward pointer (107) points to the memory address of the timer queue header, or the value stored in the timeout monitoring unit (71) in the determination process (144) Is determined to be greater than or equal to the value of the first period monitoring unit (72), the control register (82b) sets the interrupt generation from the second timer (9b) to be prohibited (processing 228) and ends the processing (224). To do.

  FIG. 12 is a diagram illustrating a flowchart of the second timer interrupt processing unit. The second timer interrupt processing unit (95) activates the processor (1) when the second timer interrupt occurs (65b). First, in order to update the first cycle monitoring unit, the counter (83b) is set not to underflow in the control register (82b) of the second timer (9b) and stored in the first cycle monitoring unit (72). The second timer period (44b) is subtracted from this value, and the subtraction value is substituted into the first period monitoring unit (75) (process 241).

  Next, in order to update the remaining time of the task that times out earliest, the memory address of TCB (109) pointed to by the forward pointer (107) of the timer queue header (106) is substituted into the processing pointer (101a). . The value obtained by subtracting the second timer period (44b) from the value stored in the timeout monitoring unit (71) of the TCB (109) pointed to by the processing pointer (101a) is the TCB (109) pointed to by the processing pointer (101a). ) In the time-out monitoring unit (71) (step 242).

  Next, discrimination processing (125), processing (223), processing (224), and discrimination processing (141) are performed. Since these have been described with reference to FIG.

  With the processing flow as described above, the present invention can be implemented, and the power consumption and response speed of the information processing phase device can be reduced.

  Although the embodiment of the present invention has been described on the assumption that the timer (9) adopts the countdown method, the operation principle is the same for the timer (9) of the countup method, so that it can be applied. .

  FIG. 13 is a diagram for explaining an embodiment when the present invention is applied to an information processing apparatus to which the present invention is applied, particularly an information portable terminal. The present invention can be easily realized by changing the function of the OS, that is, the software without changing the hardware, if the information processing device has two timers TIM (9) (two channels). . However, it is possible to perform processing at high speed by appropriately realizing functions processed by software (OS) with hardware. Furthermore, as shown in FIG. 14, a timer and a power saving mode may be mounted on the CPU. In this case, the information processing apparatus can be made small.

  FIG. 15 is a diagram for explaining a second embodiment of the information processing apparatus according to the present invention. In a communication device represented by a mobile phone, communication and multimedia processing are performed simultaneously, and the load on the processor is heavy. Therefore, a baseband processor (1b) for communication processing and an application processor (1a) for multimedia processing are installed in the information processing apparatus. Here, the present invention can be applied to both the baseband processor (1b) and the application processor (1a). However, the power consumption of the baseband processor (1b) is smaller than that of the application processor (1a). Accordingly, in FIG. 15, the present invention is applied only to the application processor (1a) and not to the baseband processor (1b). With such a configuration, the capacity of the memory MEM (21b) related to the baseband processor (1b) can be reduced, and the information processing apparatus can be configured smaller.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example,

It is a figure explaining the typical example of this invention. It is a figure explaining the problem which invention is going to solve. It is a figure explaining operation | movement of this invention. It is a figure explaining the timeout request issue processing part flowchart. It is a figure explaining the flowchart of a process (201). It is a figure explaining the flowchart of a process (204). It is a figure explaining the flowchart of a process (205). It is a figure explaining the flowchart of a process (202). It is a figure explaining the flowchart of a 1st timer interruption process part. It is a figure explaining the flowchart of a process (223). It is a figure explaining the flowchart of a process (224). It is a figure explaining the flowchart of a 2nd timer interruption process part. It is a figure explaining the information processing apparatus which gave this invention. It is explanatory drawing of a timer and a power-saving mode built-in CPU information processing apparatus. It is a figure explaining the information processor with a processor to which the present invention is applied. It is a figure explaining the conventional radio | wireless communication apparatus. It is a figure explaining the subject of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Processor 2 ... Synchronous circuit 3 ... Receiving circuit 4 ... Register 5 ... Switching circuit 6 ... High-speed oscillation circuit 7 ... RTC
8 ... I / O
9 ... Timer 10 ... Interrupt circuit 11 ... Bus 21 ... Memory 22 ... OS
23 ... Power saving mode circuit 24 ... System clock 41 ... Current consumption 42 ... Timer interrupt request mode 43 ... Power saving mode 44 ... Timer cycle 45 ... 0 [A]
46 ... Current consumption value when timer interrupt occurs 47 ... Current consumption value during power saving mode 61 ... Counter axis 62 ... Time axis 63 ... Counter value 64 ... Cycle setting value 65 ... Interrupt generation 66 ... Time-out request issue time 67 ... Time-out time 68 ... Time-out request time 71 ... Time-out monitoring unit 72 ... First period monitoring unit 73 ... Time monitoring rate storage unit 81 ... Status register 82 ... Control register 83 ... Counter 84 ... Cycle setting register 85 ... Clock CK
91 ... OS time management unit 92 ... TCB management unit 93 ... Timeout request issue processing unit 94 ... First timer interrupt processing unit 95 ... Second timer interrupt processing unit 101 ... Processing pointer DESCRIPTION OF SYMBOLS 102 ... Insertion pointer 103 ... Temporary storage part 104 ... Ready cue header 105 ... Wait cue header 106 ... Timer cue header 107 ... Forward pointer 108 ... Reverse pointer 109 ..TCB
121 ... start point 122 ... end point 123 ... confluence 124, 125, 126, 127, 128, 129, 141, 142, 143, 144 ... discrimination processing 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 221, 222, 223, 241, 242, ... processing

Claims (3)

An information processing apparatus that makes a system call by designating an occurrence time until execution of a predetermined event,
A first timer circuit set in the first period;
A second timer circuit set to a second period shorter than the first period;
The time-out monitoring unit capable of storing the occurrence time when the system call is made;
A first period monitoring unit capable of storing a time until an interrupt request of the first timer circuit when the system call is made;
A register for setting whether the interrupt generation from the second timer circuit is permitted or prohibited,
The time-out monitoring unit prohibits an interrupt request from the second timer when the time stored in the time-out monitoring unit is longer than the first period, and the time stored in the time-out monitoring unit is the first time If it is shorter than the period, set the register to allow the interrupt request from the second timer,
When the timeout monitoring unit receives an interrupt request from the first timer circuit or the second timer circuit, the timeout monitoring unit refers to the value of the register to determine whether the interrupt request from the first timer circuit or the second timer Determine whether it is an interrupt request from the circuit,
The time-out monitoring unit stores a time obtained by subtracting the time stored in the first period monitoring unit from the time stored in the time-out monitoring unit when it is determined as an interrupt request of the first timer circuit, Subtracting the time of the second period from the time stored in the timeout monitoring unit when it is determined as an interrupt request of the second timer circuit;
The information processing apparatus, wherein the event is executed when the time stored in the timeout monitoring unit becomes 0 or less. An information processing apparatus that measures a predetermined time from a system call to execution of a predetermined event,
A first timer for counting at a time interval of the first period;
A second timer for counting at a time interval of a second period shorter than the first period;
A time-out monitoring unit for measuring the predetermined time;
A register for setting whether the interrupt generation from the second timer is permitted or prohibited,
The time-out monitoring unit prohibits an interrupt request from the second timer when the time stored in the time-out monitoring unit is longer than the first period, and the time stored in the time-out monitoring unit is the first time If it is shorter than the period, set the register to allow the interrupt request from the second timer,
The time-out monitoring unit refers to an interrupt request from the first timer or an interrupt from the second timer by referring to the value of the register when an interrupt request is received from the first timer or the second timer. Determine if it is a request,
When the information processing apparatus measures the predetermined time, when it is determined that the interrupt request is from the first timer, the information processing apparatus counts by the first timer, and when it is determined that the interrupt request is from the second timer Counting by the second timer,
The predetermined time decreases the time stored in the timeout monitoring unit when it is determined as an interrupt request of the first timer, and the interrupt of the second timer when it is determined as an interrupt request of the second timer. Measured by reducing the time stored in the timeout monitor upon receipt of the request,
The information processing apparatus, wherein the event is executed when the time stored in the timeout monitoring unit becomes 0 or less. An information processing apparatus that executes a predetermined event after a predetermined time from a system call,
A central processing unit;
A memory connected to the central processing unit;
A first timer for making an interrupt request according to a pulse of the first period;
A second timer that makes an interrupt request according to a pulse of a second period shorter than the first period;
A timeout monitoring unit for storing the predetermined time at the time of the system call;
A register for setting whether the interrupt generation from the second timer is permitted or prohibited,
The time-out monitoring unit prohibits an interrupt request from the second timer when the time stored in the time-out monitoring unit is longer than the first period, and the time stored in the time-out monitoring unit is the first time If it is shorter than the period, set the register to allow the interrupt request from the second timer,
The time-out monitoring unit refers to an interrupt request from the first timer or an interrupt from the second timer by referring to the value of the register when an interrupt request is received from the first timer or the second timer. Determine if it is a request,
The central processing unit changes the time stored in the time-out monitoring unit when it is determined as an interrupt request for the first timer, and when the interrupt request for the second timer is determined as the interrupt request for the second timer. Change the time stored in the timeout monitoring unit by an interrupt request,
The information processing apparatus, wherein the event is executed when the time stored in the timeout monitoring unit becomes 0 or less.

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