JP2008242884A - I2c bus control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem of a conventional I2C bus control circuit that a STOP condition is outputted in accordance with the slowest STOP condition reception timing among devices connected to the same I2C bus and the unnecessary waiting of a device earlier in the STOP condition reception timing is caused. <P>SOLUTION: A transmission control part 413 is provided with a STOP condition output timing control register 422. A controller 419 for determining a communication counterpart optimizes STOP condition generation timing for each slave address, and thereby a communication time is reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an I2C bus control circuit capable of shortening transmission time by efficiently using an I2C bus used for an interface between internal devices such as electronic devices.

  The I2C bus control needs to comply with the I2C specification proposed by Philips (see Non-Patent Document 1). However, this specification does not specify an implementation method of I2C bus control, and there are various implementation methods.

  Some slave devices connected to the I2C bus do not comply with the stop condition timing specified in the I2C specification. Even if the master device outputs a stop condition as specified in the I2C specification, the slave device may not recognize the stop condition. . For this reason, in a communication circuit in which multiple slave devices are connected on the same I2C bus, the master device outputs a stop condition at the timing that matches the slave device with the slowest timing to recognize the stop condition, thereby realizing I2C communication. ing.

  More specifically, a conventional I2C bus control circuit is connected to a controller that performs control and monitoring, and the controller determines a slave address of a slave device to be communicated and data to be transmitted, and 1 byte is transferred to the I2C bus control circuit. When the slave address is set as the eye data, the I2C bus control circuit transmits the slave address and transmits an interrupt signal to the controller after transmission. The controller sets the second byte data by the interrupt, the I2C bus control circuit transmits the second byte, transmits the interrupt signal to the controller after transmission, and the controller sets the next transmission data by the interrupt Is repeated, and a stop condition is output at the interrupt after the last data transmission, thereby realizing continuous transmission of a plurality of data.

  In the slave device in which the sub address is composed of 1 byte, the second byte of data to be transmitted is a sub address, and in the slave device in which the sub address is composed of 2 bytes, the second byte and the third byte of data to be transmitted are sub addresses. The first byte is a slave address.

  FIG. 1 is a diagram of an I2C bus control circuit configured as a microcontroller with a built-in controller. However, the controller may be configured as a separate device.

  The I2C bus control circuit 110 in FIG. 1 includes a data line control unit 111 connected to the data line (SDA) of the I2C bus 123, a clock line control unit 112 connected to the clock line (SCL) of the I2C bus 123, A transmission control unit 113 that controls transmission according to settings from the controller 119 and a sequence control unit 116 that performs state management, error detection, timing control, and the like are provided.

  The transmission control unit 113 includes a transmission data register 114 and a parallel / serial conversion unit 115, and the sequence control unit 116 includes an arbitration unit 117 and an error detection unit 118. The configuration of the transmission data register 114 of the transmission control unit 113 is shown in FIG.

  The controller 119 sets data in the transmission data register 114 of the transmission control unit 113, so that the data set in the transmission data register 114 of the transmission control unit 113 is parallel / serial in synchronization with the timing generated by the sequence control unit 116. The data is converted by the conversion unit 115 and transmitted to the data line control unit 111. The data line control unit 111 and the clock line control unit 112 are synchronized with the timing generated by the sequence control unit 116, respectively. Data transmission is performed by controlling (SCL).

  The controller 119 includes a ROM 120 and a RAM 121. The ROM 120 is loaded with a program for controlling the I2C bus control circuit 110, and the RAM 121 stores data used during program execution. The controller 119 controls the I2C bus control circuit 110 by executing a program in the ROM 120 and transmits data to a plurality of slave devices. The process flow of the program will be described.

  STEP 1: The controller 119 determines a slave device to be transmitted and data to be transmitted, and stores a plurality of continuous transmission data and the number of transmission data in the RAM 121. When the number of transmission data is 0, the process ends. Here, a slave address is set at the head of a plurality of continuous transmission data.

  STEP 2: The controller 119 sets the first byte (slave address) of a plurality of continuous transmission data and the start condition control bit in accordance with the configuration of the transmission data register 114 of the transmission control unit 113 (stop condition control bit). Is not set) in the transmission data register 114, and the number of transmission data in the RAM 121 is reduced by one.

  STEP 3: The start condition and 1-byte data (slave address) are transmitted by the I2C bus control circuit 110, and the transmission of the RAM 121 by an interrupt transmitted from the sequence control unit 116 of the I2C bus control circuit 110 to the controller 119 after the transmission. If the number of data is 1 or more, the next 1-byte transmission data of a plurality of continuous transmission data (the start condition control bit and stop condition control bit are not set) is set in the transmission data register 114, and the number of transmission data in the RAM 121 Decrease by 1. When the number of transmission data is 0, the I2C bus control circuit 110 outputs a stop condition by setting the transmission data register 114 with data in which the stop condition control bit is set (the start condition control bit and transmission data are not set). To end transmission.

  STEP 4: If 1 byte data is transmitted in the I2C bus control circuit 110, and the number of transmission data in the RAM 121 is 1 or more by an interrupt transmitted from the sequence control unit 116 of the I2C bus control circuit 110 to the controller 119 after the transmission, The next 1-byte transmission data (the start condition control bit and the stop condition control bit are not set) of a plurality of continuous transmission data is set in the transmission data register 114 to reduce the number of transmission data in the RAM 121 by one. When the number of transmission data is 0, the I2C bus control circuit 110 outputs the stop condition by setting the data in which the stop condition control bit is set (the start condition control bit and the transmission data are not set) in the transmission data register 114. To finish transmission.

  STEP5: Repeat STEP4.

  As described above, a series of data transmission is realized by the conventional I2C bus control circuit 110.

  FIG. 3 shows an example of I2C communication when a plurality of slave devices are connected on the same I2C bus in the conventional I2C bus control circuit.

As shown in the upper half of FIG. 3, even when the device B alone can recognize the stop condition quickly, the above STEP 3 and STEP 4 when a plurality of slave devices having different speeds are connected on the same I2C bus. As shown in the lower half of FIG. 3, the output timing of the stop condition is output in accordance with the timing of the slave device having the latest timing for recognizing the stop condition.
Philips: THE I2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000, Internet <URL: http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf>

  As described above, in a conventional communication circuit in which a plurality of slave devices are connected on the same I2C bus, the master device outputs a stop condition at a timing that matches the slave device with the latest timing for recognizing the stop condition. Communication was realized.

  Furthermore, the specifications of the I2C bus have recently been expanded to enable high-speed communication. Even if high-speed communication is possible, a communication circuit in which a plurality of slave devices are connected on the same I2C bus is stopped. Since it is necessary to match the slave device whose timing for recognizing the condition is the slowest, a device having a fast timing for recognizing the stop condition has a waiting time.

  In addition, electronic devices such as AV devices have become highly functional, and the amount of communication on the I2C bus inside the device has increased, which also affects the performance of the electronic devices. For example, when switching channels on a TV, data corresponding to the video processing device, audio processing device, etc. is transmitted all at once according to the video format and audio format of the channel after switching, and during this transmission, video mute and It is customary not to produce distorted video or audio by applying audio mute, but if the transmission time is long, the time to apply the video mute or audio mute becomes long, which makes the viewer uncomfortable.

  The present invention reduces the communication time by adding a function for changing the output timing of the stop condition to the conventional configuration and transmitting the stop condition at an optimum timing for each slave device.

  According to the present invention, in an electronic device using an I2C bus control circuit, if only the I2C bus control circuit and the controller program to which the function for changing the output timing of the stop condition is modified, the communication time can be reduced easily and easily. And the performance of the electronic device can be improved.

  Hereinafter, specific examples of the I2C bus control circuit according to the present invention and application examples thereof will be described with reference to FIGS.

Embodiment 1
FIG. 4 is a diagram of an I2C bus control circuit configured as a microcontroller with a built-in controller. However, the controller may be configured as a separate device.

  The I2C bus control circuit 410 of FIG. 4 includes a data line control unit 411 connected to the data line (SDA) of the I2C bus 423, a clock line control unit 412 connected to the clock line (SCL) of the I2C bus 423, A transmission control unit 413 that controls transmission according to settings from the controller 419 and a sequence control unit 416 that performs state management, error detection, timing control, and the like are provided. A plurality of slave devices (for example, devices A, B, C, and D) 424, 425, 426, and 427 are connected to the I2C bus 423.

  The transmission control unit 413 includes a transmission data register 414, a parallel / serial conversion unit 415, and a stop condition output timing control register 422, and the sequence control unit 416 includes an arbitration unit 417 and an error detection unit 418, respectively.

  FIG. 5 shows a stop condition timing table 428 that the controller 419 has.

  The controller 419 includes a ROM 420 and a RAM 421. The ROM 420 has a program for controlling the I2C bus control circuit 410 and an output timing of stop conditions according to addresses of slave devices 424 to 427 connected on the same I2C bus 423. A stop condition timing table 428 for managing the program is mounted, and the RAM 421 stores data used during program execution. The controller 419 controls the I2C bus control circuit 410 by executing the program of the ROM 420 and transmits data to the plurality of slave devices 424 to 427.

  The stop condition timing table 428 may be configured in the RAM 421. Further, in the present embodiment, the case of using a table has been described, but it may be realized by other means.

  Hereinafter, the flow of processing of the program will be described.

  STEP 101: The controller 419 determines a slave device to be transmitted and data to be transmitted, and stores a plurality of continuous transmission data and the number of transmission data in the RAM 421. When the number of transmission data is 0, the process ends. Here, a slave address is set at the head of a plurality of continuous transmission data.

  STEP 102: The controller 419 determines a slave device to transmit, reads the stop condition output timing corresponding to the slave address to be transmitted from the stop condition timing table 428, and sets it in the stop condition output timing control register 422.

  STEP 103: The controller 419 sets the first byte (slave address) of a plurality of continuous transmission data and a start condition control bit (stop condition control bit) in accordance with the configuration of the transmission data register 414 of the transmission control unit 413. Is not set) in the transmission data register 414, and the number of transmission data in the RAM 421 is reduced by one.

  STEP 104: A start condition and 1-byte data (slave address) are transmitted by the I2C bus control circuit 410, and then transmitted by the RAM 421 by an interrupt transmitted from the sequence control unit 416 of the I2C bus control circuit 410 to the controller 419. If the number of data is 1 or more, the transmission data register 414 is set with the next 1-byte transmission data (the start condition control bit and the stop condition control bit are not set) of a plurality of continuous transmission data, and the number of transmission data in the RAM 421 Decrease by 1. When the number of transmission data is 0, the I2C bus control circuit 410 outputs a stop condition by setting the data in which the stop condition control bit is set (the start condition control bit and transmission data are not set) in the transmission data register 414. To end transmission.

  STEP 105: 1 byte data is transmitted in the I2C bus control circuit 410, and if the number of transmission data in the RAM 421 is 1 or more by an interrupt transmitted from the sequence control unit 416 of the I2C bus control circuit 410 to the controller 419 after the transmission, The next 1-byte transmission data of a plurality of continuous transmission data (the start condition control bit and the stop condition control bit are not set) is set in the transmission data register 414 to reduce the number of transmission data in the RAM 421 by one. When the number of transmission data is 0, the I2C bus control circuit 410 outputs the stop condition by setting the data in which the stop condition control bit is set (the start condition control bit and the transmission data are not set) in the transmission data register 414. To finish transmission.

  STEP 106: STEP 105 is repeated.

  FIG. 6 is a communication diagram in the related art and Embodiment 1 of the present invention, in which the upper stage shows the prior art and the lower stage shows the present embodiment. As shown in FIG. 6, according to the present embodiment, the output timing of the stop condition can be changed for each slave device. Conventionally, the recognition of the stop condition is the best among the plurality of slave devices connected on the same I2C bus. The stop condition that was transmitted at the timing of the slow device can be output at the optimal timing for each slave device, and the wait time wasted when the output timing of the stop condition is transmitted at the timing of the slowest slave device Communication time can be shortened.

<< Embodiment 2 >>
FIG. 7 is a diagram in which a stop condition setting function valid / invalid table 429 for determining whether the stop condition output timing setting is valid or invalid is added to the controller 419 in the I2C bus control circuit 410 according to the first embodiment.

  The stop condition setting function valid / invalid table 429 may be configured not only in the ROM 420 but also in the RAM 421. In the present embodiment, the case of using a table will be described, but it may be realized by other means.

  Hereinafter, the flow of processing of the program will be described. However, STEP 203 to STEP 206 are the same as STEP 103 to STEP 106 of the first embodiment, and thus description thereof is omitted.

  STEP 201: The controller 419 determines a slave device to be transmitted and data to be transmitted, and stores a plurality of continuous transmission data and the number of transmission data in the RAM 421. When the number of transmission data is 0, the process ends. Here, a slave address is set at the head of a plurality of continuous transmission data.

  STEP 202: The controller 419 determines the slave device to be transmitted, reads the valid / invalid corresponding to the slave device to be transmitted from the stop condition setting function valid / invalid table 429, and if it is valid, the stop condition output timing table 428. Is read out from the stop condition output timing and set in the stop condition output timing control register 422. When the validity / invalidity corresponding to the slave device to be transmitted is invalid in the stop condition setting function valid / invalid table 429, a predetermined stop condition output timing is set in the stop condition output timing control register 422.

  Thereby, in the communication circuit in which a plurality of slave devices 424 to 427 are connected on the same I2C bus 423, the size of the stop condition output timing table for each slave device can be reduced.

  In this embodiment, the case where the stop condition setting function valid / invalid is used as a table has been described. However, the transmission data register 414 may be realized by adding a stop condition function valid / invalid bit.

<< Embodiment 3 >>
FIG. 8 is a configuration diagram of the I2C bus control circuit 410 according to the third embodiment of the present invention. In the I2C bus control circuit 410 of FIG. 8, the transmission control unit 413 and the sequence control unit 416 operate based on the drive clock supplied from the controller 419. The frequency of the drive clock varies depending on the operation mode of the controller 419. Here, a case where the controller 419 has two operation modes of a normal mode and a low power consumption mode will be described.

  Note that the low power consumption mode here refers to an operation mode in which the drive clock source used by the controller 419 uses a low-speed clock frequency to suppress power consumption. Since the drive clock used in the low power consumption mode is slower than in the normal operation mode, the output timing of the stop condition is delayed in the first and second embodiments as compared with the normal mode, so it is optimal for each drive clock source. Need to be set up.

  FIG. 9 is a diagram in which a stop condition timing table 428 for determining a stop condition output timing corresponding to each drive clock source in the normal mode and the low power consumption mode is added to the controller 419.

  Hereinafter, the flow of processing of the program will be described. However, STEP 303 to STEP 306 are the same as STEP 103 to STEP 106 of the first embodiment, and thus description thereof is omitted.

  STEP 301: The controller 419 determines a slave device to be transmitted and data to be transmitted, and stores a plurality of continuous transmission data and the number of transmission data in the RAM 421. When the number of transmission data is 0, the process ends. Here, a slave address is set at the head of a plurality of continuous transmission data.

  STEP 302: The controller 419 determines the slave device to be transmitted, reads the stop condition output timing corresponding to the slave device to be transmitted and the operation mode from the stop condition timing table 428 in FIG. 9, and sets it in the stop condition output timing control register 422. .

  Accordingly, since the output timing of the stop condition delayed by the drive clock source can be set for each drive clock source, transmission can be performed at the same stop condition output timing regardless of the drive clock source.

  Note that if the operation mode of the controller 419 is changed during the stop condition output, it is expected that the output timing of the stop condition will shift, but the controller 419 detects the stop condition output and operates immediately after the stop condition is output. This can be dealt with by switching modes.

  Finally, a broadcast receiving apparatus using the I2C bus control circuit according to the present invention will be described.

  FIG. 10 is a functional block diagram showing an outline of the broadcast receiving apparatus of the present invention. This broadcast receiving apparatus is a broadcast receiving apparatus in a terrestrial analog television system, and includes an instruction input unit 1000, an event management unit 1001, an I2C transmission control unit 1002, a terrestrial analog tuner unit 1003, and a video signal processing unit 1004. And an audio signal processing unit 1006. In FIG. 10, reference numeral 1005 denotes a display device, and 1007 denotes a speaker.

  The terrestrial analog tuner unit 1003 receives video / audio signals from the antenna. The video signal processing unit 1004 processes the video signal from the terrestrial analog tuner unit 1003. The audio signal processing unit 1006 processes the audio signal from the terrestrial analog tuner unit 1003. The instruction input unit 1000 decodes the transmission code from the remote controller. The event management unit 1001 determines an event input from the instruction input unit 1000 and issues an instruction to the I2C transmission control unit 1002. The I2C transmission control unit 1002 has any one of the I2C bus control circuits according to the present invention, and responds to an instruction from the event management unit 1001 via the I2C bus via the terrestrial analog tuner unit 1003 and the video signal processing unit 1004. And the stop condition according to the timing which receives the stop condition of data and a device is transmitted to at least 1 of the audio | voice signal processing part 1006.

  As described above, a broadcast receiving apparatus can be realized using the I2C bus control circuit of the present invention.

  Although the instruction input by the remote controller is given as an example of the instruction input, the instruction input is not limited to the remote controller, and can be replaced with any man-machine interface.

  In addition, the tuner has exemplified the broadcast receiving apparatus in the terrestrial analog television system as the terrestrial analog tuner section, but the broadcast receiving apparatus in the digital television system can be realized by replacing the tuner with a digital television tuner.

  Furthermore, although the example which applies this invention regarding an I2C bus control circuit to a broadcast receiver was shown, this invention is not only between broadcast receivers but between internal devices, such as a mobile telephone and a car navigation system, via an I2C bus. It can be applied to any electronic device that communicates.

  According to the I2C bus control circuit of the present invention, the communication time of the I2C bus used in the electronic device can be shortened, and the performance of the electronic device can be improved. Since only the program of the I2C bus control circuit and the controller is modified, it can be applied to a conventional electronic device at a low cost and in a short period of time.

  In particular, in digital TVs that have recently become widespread, with the diversification of corresponding video formats and audio formats, higher image quality, and higher sound quality, the amount of data transmitted on the I2C bus generated at the time of channel switching increases. Switching time is getting longer. The present invention is useful as one technique for solving such problems.

It is a block diagram of the conventional I2C bus control circuit. It is a block diagram of the transmission data register of the conventional I2C bus control circuit. It is a wave form diagram of an I2C bus when a stop condition is transmitted by a conventional I2C bus control circuit. It is a block diagram of the I2C bus control circuit in Embodiment 1 of this invention. It is a block diagram of the stop condition timing table which the controller in FIG. 4 has. FIG. 3 is an I2C bus communication diagram showing a comparison between the conventional example and the first embodiment of the present invention. It is a block diagram of the stop condition timing table and stop condition setting function valid / invalid table which the controller in Embodiment 2 of this invention has. It is a block diagram of the I2C bus control circuit in Embodiment 3 of this invention. It is a block diagram of the stop condition timing table which the controller in FIG. 8 has. 1 is a block diagram of a broadcast receiving apparatus using an I2C bus control circuit according to the present invention.

Explanation of symbols

110, 410 I2C bus control circuit 111, 411 Data line control unit 112, 412 Clock line control unit 113, 413 Transmission control unit 114, 414 Transmission data register 115, 415 Parallel / serial conversion unit 116, 416 Sequence control unit 117, 417 Arbitration unit 118, 418 Error detection unit 119, 419 Controller 120, 420 ROM
121,421 RAM
123, 423 I2C bus 422 Stop condition output timing control register 424 Device A
425 Device B
426 Device C
427 Device D
428 Stop condition timing table 429 Stop condition setting function valid / invalid table 1000 Instruction input unit 1001 Event management unit 1002 I2C transmission control unit 1003 Tuner 1004 Video signal processing unit 1005 Display device 1006 Audio signal processing unit 1007 Speaker

Claims (4)

An I2C bus control circuit to which a plurality of slave devices are connected,
A slave address determination unit for determining a communication partner from the plurality of slave devices;
A data determining unit for determining data to be transmitted to the communication partner;
A stop condition output timing determining unit for determining an output timing of a stop condition indicating the end of the transmission;
A transmission control unit that performs a transmission operation according to the determination of the slave address determination unit, the data determination unit, and the stop condition output timing determination unit,
The I2C bus control circuit, wherein the transmission control unit outputs a stop condition at an optimal timing for each slave device. The I2C bus control circuit according to claim 1,
A stop condition timing valid / invalid determining unit for determining whether to enable or disable the output timing of the stop condition determined by the stop condition output timing determining unit;
The transmission control unit outputs a stop condition at the timing determined by the stop condition output timing determining unit when the stop condition output timing valid / invalid determining unit is determined to be valid, and when determined to be invalid An I2C bus control circuit that outputs a stop condition at a predetermined timing. The I2C bus control circuit according to claim 1 or 2,
The I2C bus control circuit, wherein the stop condition output timing determination unit determines a stop condition output timing for each mode of a drive clock of the transmission control unit. An apparatus that outputs a video and an audio by demodulating a video signal and an audio signal constituting the received television signal after receiving a broadcast television signal,
A television signal receiver that receives the television signal via a broadcast path;
An instruction input unit for receiving an instruction from the operator;
An event management unit for guiding processing to be executed from the input from the instruction input unit and the current state;
A video signal processor for demodulating the video signal;
An audio signal processor that demodulates the audio signal;
The television signal having the I2C bus control circuit according to any one of claims 1 to 3, wherein the television signal is connected to the same I2C bus by controlling the I2C bus control circuit in accordance with an instruction from the event management unit. A broadcast receiving apparatus comprising: an I2C transmission control unit configured to transmit data to at least one of a receiving unit, the video signal processing unit, and the audio signal processing unit.

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