JP2008227890A - Dual-configuration transmission method, transmission system, and receiving apparatus in tdm line emulation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dual-configuration transmission method, transmission system and receiving apparatus in a TDM line emulation that does not include unnecessary means. <P>SOLUTION: A packet in which TDM data and a sequence number are encapsulated is transmitted to both dual communication paths. A TDM signal is taken out from the received packet, and the sequence number transmitted together is referred so as to calculate and write a write address of a memory. Furthermore, a read address is calculated, after an initial-value of the read address has been determined in consideration of maximum transmission delay time difference, and the TDM signal is read from the memory at a predetermined cycle. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention provides communication reliability in TDM circuit emulation for transmitting a TDM signal of a synchronous communication service (ISDN, STM, SONET / SDH, etc.) via an asynchronous communication network (Ethernet (registered trademark), IP, etc.). The present invention relates to a transmission method, a transmission system, and a receiving device having a duplex configuration for improvement.

  As a standard related to the TDM circuit emulation technology, for example, ITU-T Recommendation Y. 1413 “TDM-MPLS network interworking-User plane interworking” defines a function for interconnection between a TDM network and an MPLS network. 1453 "TDM-IP interworking-User plane interworking" defines a function for interconnection between a TDM network and an IP network. Also, MEF8 “Implementation Agreement for the Emulation of PDH Circuits over Metro Ethernet Networks” stipulates the transmission of TDM signals over the Ethernet network.

  In the duplex configuration method, by duplicating the communication path, even if an abnormality occurs in one of the paths, a signal can be transmitted through the other path, so that communication reliability can be improved. It can be done.

  In a system in which a data transmission device transmits data to a data reception device, a communication system having a duplex configuration in which a path between both devices is duplexed is conventionally known. For example, Non-Patent Document 1 describes multiple section switching in which an active and spare multiple section is prepared between two devices in an SDH network, and is automatically switched from active to spare when a failure occurs. In addition, there is a 1: n configuration in which there is one spare and n active, and the active side and the spare are separated on the transmission side, or one spare and one active side, and the active side and the spare on the transmission side. It also describes the configuration of the switching system, such as a 1 + 1 configuration that always flows the same information.

  Non-Patent Document 2 proposes a transmission method that does not cause signal loss at the time of switching.

  In the method described in Non-Patent Document 2, the ATM cell transmitted by the ATM transmitting apparatus is copied and transmitted to a plurality of independent paths, and the receiving apparatus receives ATM cells from the plurality of paths. Two methods have been proposed as a method for transmitting a cell received by a receiving apparatus to the subsequent stage. One method is a method for transmitting a cell to the subsequent stage when the same cell arrives from both paths, and the other method is: This is a method of adjusting the delay time of the first-arriving cell with a delay adjustment buffer and then sending the cell that has arrived first to the subsequent stage. In order to identify the same cell, synchronous cells including sequence numbers are inserted at regular intervals.

  Further, in Patent Document 1, when a packet is transferred from a transmitting device to a receiving device, the transmitting device copies the packet, transfers each copy through two or more independent paths, and identifies each packet on the receiving side. A method has been proposed in which one of the same packets is transferred downstream while maintaining the order. In order to identify the identity and order of the packets, the order information inserted into the packets by the transmitting device or the time stamp is used. In order to transfer only one of the same packets downstream, the identity identification information of the transferred packets is held for the past m, and only untransferred packets are transferred.

  Further, in Patent Document 2, in a non-disruptive transmission apparatus arranged opposite to each other via a plurality of transmission units for transmitting cells in an ATM network, the transmitting side duplicates and transmits the cells having the same information to the plurality of transmission units. Then, a method has been proposed in which a cell having the same information received on the receiving side is identified, one of the cells is transmitted to the subsequent stage, and the other cell is discarded.

JP 2006-174406 A JP 7-46250 A Hiroyuki Kawanishi, Kazumitsu Tsuji, Hisao Tsuji, Hiroshi Ueda, “Intuitive SDH / SONET Transmission Method”, Ohmsha, 2001 Kojiyama Koji, Fujiwara Kazuhiro, Tsuboi Toshinori, “Proposal of ATM Uninterrupted Transmission Method for Real-time Applications”, IEICE General Conference, no. B-8-28, pp. 375, March 1998

  The method described in Non-Patent Document 2 requires a reception ATM cell buffer for delay adjustment and a selection process for the first cell.

  According to the method described in Patent Document 1, the same packet is identified from the received packets using the identity identification information such as order information, and one of the same packets is transferred downstream. However, to transfer only one of the same packets, it is necessary to identify the transferred packet. This document holds m pieces of identity identification information in the past, and judges them by comparing them with the identity identification information of the received packet. In this case, it is necessary to hold and compare the past m pieces of identity identification information.

  The method described in Patent Document 2 requires a means for identifying cells having the same information and selecting only one of them, and for this purpose, reception history of cells having the same information is required. Alternatively, it is necessary to store all received cells during the time when arrival of all cells having the same information transmitted in parallel can be expected. Therefore, depending on the case, a huge storage means for storing the reception history or the reception cell is required.

  However, the above-described prior art is not limited to the TDM signal to be transmitted, but is applied to general information transmission. Therefore, the first cell selection process, the identity identification information holding and comparison process, the reception history Or an enormous storage means for storing received cells is required. On the other hand, in TDM circuit emulation, since the information to be transmitted is a TDM signal, when considering only the dual configuration method of TDM circuit emulation, each method of the prior art has unnecessary means as described above. There was a problem of being included.

  Therefore, in order to solve the above problems, the present invention doubles the paths that make up the TDM circuit emulation, transmits the same data through both paths, and generates information loss even if an abnormality occurs in one of the paths. An object of the present invention is to provide a transmission method, a transmission system, and a receiving apparatus having a duplex configuration that are not allowed to be performed.

  In order to achieve the above object, a transmission method according to the present invention is a transmission method of a duplex configuration of TDM circuit emulation for transmitting a TDM signal of a synchronous communication service via an asynchronous communication network, and includes a TDM data and a sequence number. Is transmitted to both of the duplexed communication paths, a receiving step to receive the packet, a separating step to separate the sequence number from the received packet, and the separated A write address generating step for generating a write address based on the sequence number, a write step for writing the TDM data of the received packet to a common memory at the write address, and maximum transmission of the duplexed communication path Initial value of read address based on delay time difference Et al, and the read address generating step of generating a read address, in the read address, including the steps of: reading the TDM data in a predetermined period from said common memory.

  The transmitting step includes a sub-step of creating a common data unit including the TDM signal and the sequence number, duplicating the common data unit, and a sub-step of creating a packet according to the communication path from the common data unit. Preferably including a step.

  The write address is preferably generated while maintaining a one-to-one relationship and an order relationship with the sequence number.

  Preferably, the method further includes a selection step of ordering the received packets and passing them to the writing step when the packets are received simultaneously from the duplexed communication path.

  Further, the initial value of the read address is a value obtained by subtracting a fixed value from the initial value of the write address and further subtracting 1, and the fixed value is a value obtained by dividing the maximum transmission delay time difference by the period. preferable.

  In the initial state of the memory, idle signals are preferably stored at all addresses.

  In order to achieve the above object, a receiving apparatus according to the present invention is a receiving apparatus having a duplex configuration of TDM line emulation that transmits a TDM signal of a synchronous communication service via an asynchronous communication network, and includes a TDM data and a sequence number. Receiving means for receiving a packet encapsulating the packet from both duplexed communication paths, separating means for separating the sequence number from the received packet, and generating a write address based on the separated sequence number A write address generating means for writing, a write means for writing the TDM data of the received packet to a common memory at the write address, and an initial value of the read address based on a maximum transmission delay time difference of the duplexed communication path Read address generation method for generating a read address from When, in the read address includes a reading means for reading the TDM data from said common memory in a predetermined cycle.

  In order to achieve the above object, a transmission system according to the present invention is a transmission system having a duplex configuration of TDM line emulation that transmits a TDM signal of a synchronous communication service via an asynchronous communication network, and includes a TDM data and a sequence number. The transmission apparatus which transmits the packet which encapsulated to the duplex communication path | route, and the receiving apparatus described above are provided.

  According to the present invention, in TDM circuit emulation performed using a duplex communication path, even if a failure occurs in one of the communication paths, no signal loss appears from the receiving TDM terminal, and the received TDM is received. Provided are a transmission method, a transmission system, and a receiving apparatus in which a signal does not fluctuate in timing.

  The present invention has an effect that the first-arrival cell selection process required in the prior art is unnecessary and a buffer for delay adjustment is also unnecessary. Further, there is an effect that it is not necessary to hold the identity information of the packet transferred in the past and the processing is unnecessary.

  In a packet network that performs TDM line emulation, two lines of the packet network between the transmission device and the reception device are set. The transmitting apparatus transmits a packet encapsulating TDM data and a sequence number to both paths. The receiving apparatus stores the TDM data extracted from the received packet in a memory with a write address calculated by referring to a sequence number sent together with the TDM data. Although the packet transmission delay time may be different for each route, it is stored in the memory regardless of first arrival or later arrival. As a result, even if one path fails, data from the other path is stored in the memory. Furthermore, the receiving apparatus can output the TDM signal at a desired timing by reading data from the memory at a period that matches the data rate of the TDM signal, and can realize an uninterrupted transmission method in TDM line emulation. . In this system, it is not necessary to identify the identity of a packet, and it is not necessary to select a first-arrival packet.

  The entire system including the transmission device and the reception device is shown in FIG. The transmitting-side TDM terminal outputs a TDM signal to the transmitting apparatus, and the transmitting apparatus generates two packets for a group of TDM signals and transmits them to different communication paths. There are two interfaces for the transmitting device to connect to the communication path, and there are two interfaces for the receiving device to connect to the communication path. A unique destination address is set for each interface of the receiving apparatus. In each packet transmitted by the transmission device to each communication path, the destination address is correctly set so as to reach the interface of the reception apparatus corresponding to the path.

  The functional block configuration of the transmission apparatus is shown in FIG. A common data unit of a predetermined format is created from the TDM signal received from the transmitting side TDM terminal, the common data unit is copied and passed to the packet generation unit # 1 and the packet generation unit # 2, and a packet corresponding to the communication path is transmitted. Create and output to communication path # 1 and communication path # 2. In addition to the TDM signal, the common data unit also includes a sequence number indicating the order in which packets are created.

  An example of a common data unit and a packet created by the transmission device is shown in FIG. A data obtained by adding an encapsulation header or the like to a fixed amount of received TDM signal at a certain period and adjusting the format is called a common data unit. The sequence number is included in the encapsulation header. The value of the sequence number is obtained by adding 1 to the value of the sequence number of the common data unit created before that. This addition is performed modulo M (M is a positive integer). The initial value of the sequence number is set by a separately defined method. The range of the sequence number value is 0 or more and M−1 or less. The value of the sequence number increases by 1, but when it increases to M−1, the next sequence number becomes 0. The TDM signal is put in the TDM payload part. In the example of FIG. 3, two packets are created by adding a destination address, a source address, and an FCS (Frame Check Sequence) to the common data unit. The value of the destination address is the value of the destination address assigned to each interface of the receiving device.

  The functional block configuration of the receiving apparatus is shown in FIG. 4A. The packet filter refers to the destination address and the transmission source address of the received packet, and determines that the packet is a packet transmitted from the predetermined transmission source to the own interface. Otherwise, discard the packet. The sequence number separation unit separates the sequence number of the packet received from the packet filter, passes the sequence number to the write address generation unit, and passes the TDM signal to the selection unit. The write address generation unit generates an address of a memory storing the TDM signal based on the sequence number.

  In order for the transmitting TDM terminal and the receiving TDM terminal to correctly transmit and receive signals, the TDM signal output from the transmitting TDM terminal is (of course) maintained in its order and timing, and the receiving side It needs to be received by the TDM terminal. Regarding the timing, since the clock from the same clock source is provided to both the transmitting side and the receiving side, the data read from the memory by the receiving device is the same as the data rate of the TDM signal transmitted by the transmitting TDM terminal. The data rate may be output to the receiving TDM terminal. The order is as follows. The receiving apparatus writes the TDM signal into the memory and the TDM signal from the memory in the order of position so that the positional relationship of the TDM signal in the memory of the receiving apparatus is in the order when the transmitting TDM terminal transmits the TDM signal. Read it out. To read in order of position, the read address may be increased by one. The method of generating the read address in this method is simply simple because it is increased by 1 periodically.

  A method will be described in which the receiving apparatus writes the TDM signal to the memory so that the positional relationship is in the order in which it was transmitted. The data width of the memory is the same as the amount of TDM signal data accommodated in one packet. That is, in order to write the TDM signal of one packet, it is only necessary to use one value as the write address of the memory. As described above, the transmission apparatus sequentially packetizes the TDM signal received from the transmission side TDM terminal by a fixed amount and transmits the packet. This fixed amount of TDM signal is called a block TDM signal. Since the sequence number given to the packet is incremented by 1, the order of the block TDM signals matches the order of the sequence numbers. Therefore, if the order relationship of the write addresses when writing the block TDM signal to the memory matches the order relationship of the sequence numbers, the order of the block TDM signal is retained and written to the memory. FIG. 5 shows a schematic diagram of a TDM signal output from the transmitting TDM terminal, a sequence number corresponding to the TDM signal, a write address, and a position in the memory. It can be seen that the above method places the block TDM signals in the memory in the same order as they were transmitted. There are a number of methods for associating the sequence numbers with the write addresses on a one-to-one basis and maintaining the order. For example, there is a method in which the sequence number itself is used as the write address. As a condition of this method, the memory capacity needs to be “block TDM signal data amount” × M or more. Since the block TDM signals are arranged adjacent to each other by this association method, the address generation at the time of reading may be increased by one. When the area used by the memory is not an area from address 0 but another area, the essential part is the same because the minimum address of the area is used as an offset and the offset is added to the write address.

  Writing the TDM signal to the memory is basically performed every time a packet is received. However, if two packets are received simultaneously from two communication paths, the TDM signal writing signal does not collide. The selection unit adjusts the timing, selects one set from the two sets of write address signal and data signal, and outputs it to the memory. After the writing of one set of data to the memory is completed, the other set of address signal and data signal is output to the memory and written. In FIG. 4B, the selection unit selects one set from two sets of sequence numbers and TDM data, passes the selected sequence number to the write address generation unit, and writes the other sequence number after completion of writing by the selected sequence number. The structure passed to an address generation part is shown. Compared to configuration 1 in FIG. 4A, configuration 2 generates addresses after selection, and therefore requires fewer address generation units.

  The reading from the memory will be described. Set an initial value to the read address. The initial value is a value obtained by subtracting a fixed value from the value of the first write address and further subtracting one. This subtraction is performed modulo M (M is a positive integer). Stored data is periodically read from the memory, and the read address is incremented by 1 for each read. The range of values that the read address can take is the same as the range of values that the write address can take. When the read address is incremented by 1 when the value is the maximum address, the read address is set to the minimum address. The read cycle is the same as the cycle in which the transmitting device encapsulates the TDM signal to create the block TDM signal. The fixed value that is subtracted from the initial value of the write address when determining the initial value of the read address is the difference between the memory addresses corresponding to the maximum transmission delay time difference between the communication paths # 1 and # 2. This value is the maximum transmission delay time difference divided by the data read cycle. Calculate by rounding up after the decimal point. The reason for this is that, as shown in FIG. 6, only the data that arrives first can be read before the data that arrives late after the data that has arrived first is written. Because it becomes. Data that arrives late becomes data that is not read out, and data that arrives later is ignored, so there is no point in duplicating the communication path. If the earlier data does not arrive due to a failure in the communication path, the later data cannot be read out, and the effect is not achieved even though the communication paths are duplicated. Therefore, in consideration of the maximum transmission delay time difference of packets, an address that is spaced by the time for writing data that arrives late is set as the initial value of the read address.

  The read block TDM signal includes a plurality of TDM signals. One block TDM signal is read at a time, and the TDM signals in the block TDM signal are output to the receiving TDM terminal in the order in which the transmitting TDM terminal outputs them and to match the data rate output by the transmitting TDM terminal. .

  FIG. 7 shows a state at the start of data writing in the memory. As an initial state, the memory may store idle signals at all addresses. An idle signal is a signal that is output when there is no data to be transmitted as a TDM signal. In this way, even if a value read from a memory location where TDM data is not yet stored is output to the receiving TDM terminal, it is possible to avoid the possibility of unnecessary malfunction. As a matter of course, it is assumed that both communication paths # 1 and # 2 are operating normally when the operation of this system starts. This is because if there is an abnormality in the communication path, communication is started after removing the abnormal state. The first packet that arrives at the receiving device is a packet that has passed through the communication path with the shorter transmission delay time. If the transition is normal as it is, the packet that has passed through the communication path with the longer transmission delay time arrives after the transmission delay time difference elapses. When this transmission delay time difference is the maximum transmission delay time difference, the value of the read address at that time is a value obtained by adding the value obtained by dividing the maximum transmission delay time difference by the read cycle to the initial value of the read address. That is, it is a place where 1 is subtracted from the initial value of the write address (the place where the block TDM signal of the first packet is stored). The time from writing to reading data that arrives late is minimized. Thereby, the transmission delay resulting from the processing in the receiving apparatus can be minimized.

  When the data width of the memory is larger than the data amount of the block TDM signal, an area where no data is stored in the memory may be ignored.

  When the data width of the memory is smaller than the data amount of the block TDM signal, the following is performed. A memory partition equal to the amount of data of one block TDM signal is defined as one block, the memory is divided into blocks, each memory block is numbered, and the number is referred to as an upper address. When writing the TDM signal to the memory, the upper address is calculated with reference to the sequence number. The block TDM signal is divided into TDM signals of an amount that can be within the data width of the memory, and numbers are assigned to the divided data in ascending order from 0 to the order of the TDM signals, and the numbers are referred to as lower addresses. A write address for writing each divided data is generated by combining the upper address and the lower address. In the case of reading, the amount of data read at one read address is smaller than the amount of data of one block TDM signal, and the read cycle is divided when storing one block TDM signal in the memory. The period is inversely proportional to the number. In this case, however, the read address may be increased by 1 periodically. As described above, the initial value of the read address is a value obtained by subtracting a fixed value from the value of the first write address and subtracting one. This subtraction is performed modulo M (M is a positive integer). This fixed value is obtained by dividing the maximum transmission delay time difference between communication paths # 1 and # 2 by the data reading cycle. An example is shown in FIG. In the example of FIG. 8, one TDM signal is stored with one address. How many TDM signals are stored depends on the data width of the memory. In order to prevent a useless memory area where no data is stored between a certain memory block and a memory block below it, the number m of TDM signals in the block TDM signal is stored by one address. Assume that the number of TDM signals is multiplied by a power of two. B & 0 ... 0 in FIG. 8 represents a value obtained by shifting the value obtained by dividing m by the number of TDM signals stored at one address to the left by a value obtained by subtracting 1 from the number of bits in binary representation. .

  A specific example of the time change of the arrangement of TDM data in the memory of the receiving apparatus will be shown. The transmitting-side TDM terminal outputs a 64 kbit / s TDM signal, and the transmitting device encapsulates the received TDM signal every 4 bytes in a cycle of 0.5 ms, creates two packets, and sends them to communication paths # 1 and # 2. Suppose you send one by one. It is assumed that the transmission delay time of the communication path # 2 is always 1 ms longer than the communication path # 1. The initial value of the sequence number is 7. The data width of the memory of the receiving device is 1 byte. That is, the memory is divided into memory blocks each having 4 bytes. A method of calculating a memory block number with reference to a sequence number uses the sequence number itself as the memory block number. FIG. 9A and FIG. 9B show how the memory contents, the write address, and the read address change from the first packet reception. In the example of FIGS. 9A and 9B, the initial value of the write address is 28, which is a value obtained by shifting the initial value 7 of the sequence number to the left by 2 bits. The initial value of the read address is 19 which is obtained by subtracting a value obtained by dividing the maximum transmission delay time difference (1 ms) by the read cycle (0.125 ms) from the initial value 28 of the write address, and further subtracting one.

  In the present invention, it is possible to provide a function for checking an error, such as adding an error detection code to the packet, so that data in which an error is mixed during transmission is not written to the memory, Can be discarded. For example, when applied to an Ethernet frame, the frame includes a “frame check sequence (FCS)” for detecting a code error in the frame, thereby discarding all data including errors. be able to. In the present invention, by using such a function, it is possible to avoid outputting data including an error as it is.

  In the standard such as ITU-T for TDM line emulation, the sequence number is defined in the frame format, so there is no need to provide a sequence number field again.

  Moreover, all the embodiment described above shows the present invention exemplarily, and does not limit the present invention, and the present invention can be implemented in other various modifications and changes. Therefore, the scope of the present invention is defined only by the claims and their equivalents.

1 shows an overall system including a transmitting device and a receiving device. The function block structure of a transmitter is shown. An example of a common data unit and a packet created by a transmission apparatus from a TDM signal is shown. 1 shows a functional block configuration 1 of a receiving apparatus. The functional block structure 2 of a receiver is shown. The TDM signal, the sequence number, and the write address correspond to the positional relationship in the memory. The problem when the packet arrival timing and reading timing are too early is shown. The example of the state at the time of the start of TDM signal writing in memory is shown. An example of a method for storing a TDM signal in the memory when the data width of the memory is smaller than the block TDM signal will be described. The example of the time change of arrangement | positioning of TDM data in the memory of a receiver is shown. The continuation of the example of the time change of arrangement | positioning of TDM data in the memory of a receiver is shown.

Claims (8)

A TDM circuit emulation duplex transmission method for transmitting a TDM signal of a synchronous communication service via an asynchronous communication network,
A transmission step of transmitting a packet encapsulating TDM data and a sequence number to both of the duplexed communication paths;
A receiving step of receiving the packet;
A separation step of separating the sequence number from the received packet;
A write address generation step of generating a write address based on the separated sequence number;
A writing step of writing TDM data of the received packet to a common memory at the write address;
A read address generation step of generating a read address from an initial value of the read address based on the maximum transmission delay time difference between the duplexed communication paths;
A read step of reading the TDM data from the common memory at a predetermined cycle at the read address;
A transmission method of a duplex configuration of TDM line emulation, characterized in that The transmitting step includes
Creating a common data unit including the TDM signal and the sequence number, and replicating the common data unit;
A sub-step of creating a packet according to the communication path from the common data unit;
The transmission method according to claim 1, further comprising:   The transmission method according to claim 1, wherein the write address is generated while maintaining a one-to-one relationship and an order relationship with the sequence number.   4. The method according to claim 1, further comprising a selection step of ordering the received packets and passing them to the writing step when the packets are simultaneously received from the duplexed communication path. The transmission method according to the item.   The initial value of the read address is a value obtained by subtracting a fixed value from the initial value of the write address and further subtracting 1, and the fixed value is a value obtained by dividing the maximum transmission delay time difference by the period. The transmission method according to any one of claims 1 to 4.   6. The transmission method according to claim 1, wherein an idle signal is stored in all addresses in the initial state of the memory. A TDM line emulation duplex receiving device for transmitting a TDM signal of a synchronous communication service via an asynchronous communication network;
Receiving means for receiving a packet encapsulating TDM data and a sequence number from both of the duplexed communication paths;
Separating means for separating the sequence number from the received packet;
Write address generating means for generating a write address based on the separated sequence number;
Writing means for writing TDM data of the received packet into a common memory at the write address;
Read address generation means for generating a read address from an initial value of the read address based on the maximum transmission delay time difference between the duplexed communication paths;
Read means for reading the TDM data from the common memory at a predetermined cycle at the read address;
A receiver having a duplex configuration of TDM line emulation. A transmission system having a duplex configuration of TDM line emulation for transmitting a TDM signal of a synchronous communication service via an asynchronous communication network,
A transmission device for transmitting a packet encapsulating TDM data and a sequence number to a duplexed communication path;
A receiving device according to claim 7;
A transmission system having a duplex configuration of TDM line emulation.

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