JP2008219813A - Lvds receiver, lvds receiving method, lvds data transmission system, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent reception errors by using an optimum strobe signal in which skew, variations in manufacturing process, and effects of external-cause factors are suppressed, without detecting skew. <P>SOLUTION: An LVDS reception controller 200 is inputted with serial data and a clock signal so as to convert the serial data into parallel data while being synchronized with a strobe signal. The LVDS reception controller is provided with a PLL circuit 203, which generates a plurality of clock signals having different phases on the basis of the clock signal; a characteristic detection control part 210, which detects at least the information on either the variation in manufacturing process or external load so as to specify the optimum conditions for generating the strobe signal by the detected information; and a strobe selection circuit 202 that generates the strobe signal from a plurality of the clock signals generated by the PLL circuit 203, corresponding to the optimum conditions specified by the characteristics detection control part 210. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an LVDS receiver, an LVDS reception method, an LVDS data transmission system, and a semiconductor device.

  Conventionally, as a system for transmitting digital image information from an information processing apparatus to a flat panel display such as a liquid crystal display device or a plasma display panel, a liquid crystal projector, a multi-display system, etc., for example, a data transmission system as shown in FIG. Is known.

  As a means for transmitting digital image information to the display device or the like, an LVDS (Low Voltage Differential Signal) transmission technique using one or more pairs of lines is known. In the data transmission system of FIG. 17, data transfer is performed from one information processing device (transmitter (LVDSTx) 500) side to the other information processing device (receiver (LVDSRx) 600) side using an LVDS cable. Has been done.

  In this case, the transmitter 500 multiplies the input clock signal by a PLL (Phase Locked Loop) circuit 502. Based on the multiplied clock signal, parallel transmission data (hereinafter referred to as parallel data) such as input video information is converted into serial transmission data (hereinafter referred to as serial data) by a parallel / serial converter (Parallel / LVDS) 501. )).

  Then, the transmitter 500 transmits the input clock signal as it is and the converted serial data for each channel (channels CLK and AD in the example shown in FIG. 17) in the order of driver, cable, and receiver. To the receiver 600.

  The receiver 600 multiplies the received clock signal by the PLL circuit 602. Then, based on the multiplied clock signal, serial data is converted into parallel data by a serial / parallel converter (LVDS / Parallel) 601.

  Here, in order to convert serial data into parallel data, it is necessary to determine the break (start position) of each data string of serial data. Therefore, it is the received clock signal that provides information for this determination. In other words, since one cycle of the clock corresponds to the length of the unit data string, a fixed time interval is maintained between the rising (or falling) timing of the clock and the start position of each data string of serial data. I'm leaning.

  Therefore, the leading position of each data string of serial data can be known from the rising edge (or falling edge) of the received clock. As a result, conversion to parallel data can be performed without causing a bit shift.

  However, the clock signal output from the transmitter 500 often has large jitter. Therefore, the receiver 600 is affected by this jitter when extracting the clock signal or multiplying the input clock signal, so that conversion to parallel data and data reproduction are not normally performed. There was a problem.

  In other words, when the clock signal used in the receiver 600 is accompanied by jitter, a phenomenon occurs in which the propagation times of the clock signal and the data signal are different. In the case of this phenomenon, a skew that is a variation in the phase of the signal occurs between the two signals.

  As a result of the occurrence of the skew, there may be a problem that the setup time and hold time of the data signal with respect to the clock signal are not sufficiently satisfied. Further, in the case of high-speed data transmission, there is a tendency that erroneous data reception occurs.

  Therefore, as a solution to the above-described problem of skew, for example, a technique related to skew correction is disclosed in Patent Document 1.

  The skew correction apparatus of Patent Document 1 includes a transition detector that detects a transition of an input data signal and supplies a pulse signal representing the detection, and a delay data signal obtained by delaying the input data signal by a predetermined delay amount. A phase comparator for comparing the transition with the phase of the clock signal. As a result, the phase comparator controls the delay amount so that the transition of the delayed data signal is substantially in phase with the rising edge of the clock signal on condition that the pulse signal is supplied from the transition detector. . Then, the delayed data signal delayed by the controlled delay amount is output together with the clock signal.

  Therefore, since the delay amount control by the phase comparator is enabled only when there is a data signal transition, the skew between the clock signal and the data signal can be corrected not only in the setup mode but also in the normal operation mode. it can. Therefore, skew correction according to environmental changes such as temperature rise during normal operation can be performed.

  However, in the above skew correction device, it can be effective when the clock rate and the data rate are the same, but there is multi-bit serial data for one clock rate, and data that converts these serial data into parallel data. Not suitable for use in transmission systems.

  Further, as a solution to the above-described problem of skew, for example, Patent Document 2 discloses a technique for eliminating a clock phase shift on the receiving side even when jitter occurs on the transmitting side.

  The serial-parallel conversion device disclosed in Patent Document 2 reproduces a clock for performing serial-parallel conversion from a transmission clock, and provides a synchronization detection bit for each unit data string of serial data, and synchronizes with the reproduction clock to stabilize the serial data. It is characterized by serial / parallel conversion.

  As a result, it is possible to improve the display image on the receiving side by eliminating the shift in the conversion timing in the serial / parallel conversion unit and accurately converting the serial data into parallel data.

  However, the serial / parallel conversion device requires that the transmission side code the synchronization detection bit in advance in the data, and is not suitable for converting simple serial data into parallel data.

  Therefore, for example, Patent Document 3 discloses a serial parallel that self-corrects an input data signal with respect to a clock signal even if a skew occurs between the data signal and the clock signal without coding a synchronization detection bit in the data in advance. A conversion device (ie, an LVDS receiver) has been proposed.

  Next, the configuration and operation of the LVDS receiver 700 described in Patent Document 3 will be described with reference to FIGS.

  FIG. 18 is a diagram illustrating a configuration of the LVDS receiver 700.

  As shown in FIG. 18, the LVDS receiver 700 divides a clock signal and outputs a plurality of tap output signals, and generates a plurality of strobe signals having different phases using the plurality of tap output signals. A strobe generation circuit 702 for detecting a skew between serial data and a clock signal, a strobe selection circuit 704 for selecting a strobe signal corresponding to the detected skew, and converting the serial data into parallel data by the selected strobe signal. An S / P conversion unit (serial / parallel conversion circuit) 705, a receiver 706 for inputting an external clock signal, and a receiver 707 for inputting serial data from the outside.

  In LVDS receiver 700, first, a clock signal is divided by an internal VCO (voltage controlled oscillator) in PLL circuit 701, and a plurality of tap output signals are generated and output. The strobe generation circuit 702 generates a plurality of strobe signals having regularity for the generated plurality of tap output signals.

  Subsequently, the skew detection circuit 703 detects the skew of the serial data using the plurality of strobe signals. The skew detection circuit 703 samples serial data using a plurality of strobe signals created from the PLL circuit 701 through the strobe creation circuit 702. Then, the presence / absence and state of skew is detected from the sampling result.

  The plurality of strobe signals are also supplied to the strobe selection circuit 704. In the strobe selection circuit 704, an optimum strobe signal corresponding to the detection result of the skew detection circuit 703 is selected from the plurality of strobe signals generated by the strobe generation circuit 702. Then, the selected strobe signal is output to the S / P conversion unit 705 as an S / P conversion strobe signal.

  Next, the selection process of the strobe signal in the LVDS receiver 700 will be described.

  FIG. 19 is a diagram for explaining a strobe selection method when there is no skew in the LVDS receiving apparatus 700.

  In FIG. 19, CLKIN indicates the input clock signal, and DataIN indicates the input serial data. Here, it is assumed that 7-bit serial data is input within the T period and mapped with data D [6: 0] = [0001000]. In this case, attention is paid to 3 bits of the data D [4: 2].

  Arrows indicate strobe signals that are regularly created by the strobe creation circuit 702. Three strobe signals are created per 1-bit data. That is, the strobe selection circuit 704, based on the result of the skew detection circuit 703, strobe signals indicated by dotted arrows for each bit, strobe signals indicated by solid arrows for each bit, and each One of the strobe signals indicated by the broken arrow is selected for the bit. For example, if the strobe signal indicated by the dotted arrow is selected, the strobe signal indicated by the dotted arrow is selected for all the bits.

  In the skew detection circuit 703, D [4: 2] data is sampled by nine strobes (three per bit) supplied from the strobe generation circuit 702 for skew detection.

  When there is no skew, the sampling result is S [8: 0] = [000 111 000]. As a result, S [8: 0] = [000 111 000] is supplied from the skew detection circuit 703 to the strobe selection circuit 704 as a select signal.

  The strobe selection circuit 704 is supplied with a plurality of regular strobe signals from the strobe generation circuit 702. The strobe selection circuit 704 specifies that there is no skew based on the combination of S [8: 0] based on the select signal, and selects the optimum strobe signal (each strobe signal indicated by the solid line arrow in FIG. 19). Then, the selected strobe signal is output to S / P converter 705.

  Therefore, in the case shown in FIG. 19, the strobe signal regularly generated by the PLL circuit 701 has a three-strobe configuration for one data, and an optimum strobe signal is obtained by performing skew detection for D4, D3, and D2. Selected.

  FIG. 20 is a diagram for explaining a strobe selection method when there is data advance skew in the LVDS receiver 700. Input parameters such as serial data and a clock signal are the same as those in FIG.

  In the skew detection circuit 703, D [4: 2] data is sampled by nine strobes (three per bit) supplied from the strobe generation circuit 702 for skew detection.

  In this case, since the serial data is advanced (advanced) with respect to the clock signal, the sampling result is S [8: 0] = [001 110 000]. Then, this result is supplied from the skew detection circuit 703 to the strobe selection circuit 704 as a select signal.

  The strobe selection circuit 704 identifies that there is an advance skew based on the select signal, and selects an optimum strobe signal (each strobe signal indicated by a dotted arrow in FIG. 20). Then, the selected strobe signal is output to S / P converter 705.

  Therefore, as shown in FIG. 20, even if there is an advance skew of data, an optimal strobe signal is selected and supplied to the S / P converter 705. For this reason, S / P conversion is possible in a state where a stable strobe margin is ensured.

  FIG. 21 is a diagram for explaining a strobe selection method when there is a data delay skew in the LVDS receiver 700. Input parameters such as serial data and a clock signal are the same as those in FIG.

  In the skew detection circuit 703, D [4: 2] data is sampled by nine strobes (three per bit) supplied from the strobe generation circuit 702 for skew detection.

  In this case, since the serial data is delayed (delayed) with respect to the clock signal, the sampling result is S [8: 0] = [000 011 100]. Then, this result is supplied from the skew detection circuit 703 to the strobe selection circuit 704 as a select signal.

  The strobe selection circuit 704 identifies that there is a delay skew based on the select signal, and selects an optimum strobe signal (each strobe signal indicated by a broken arrow in FIG. 21). Then, the selected strobe signal is output to S / P converter 705.

Therefore, as shown in FIG. 21, even when there is a data delay skew, an optimum strobe signal is selected and supplied to the S / P converter 705. For this reason, S / P conversion is possible in a state where a stable strobe margin is ensured.
Japanese Patent Laid-Open No. 11-168365 (released on June 22, 1999) JP 2000-78027 A (published March 14, 2000) JP 2003-133965 A (published on May 9, 2003)

  However, the LVDS receiver 700 described in Patent Document 3 has a problem that it is necessary to include a skew detection circuit 703 because it is necessary to detect skew.

  In the above description, an example in which skew is detected by focusing on 3 bits of data D [4: 2] has been described. For example, when 7 bits of D [6: 0] are focused, serial data is always in 21 locations. Since it is necessary to sample, the number of samples increases. Therefore, the LVDS receiving apparatus 700 has a problem that the processing for converting the serial data is heavy and complicated, and the power consumption increases.

  By the way, in a general receiving device, due to the influence of fluctuations such as heat treatment occurring in the manufacturing process (manufacturing process) of the receiving device, the fluctuations affect the shape of the element and the physical property conditions, and thus in the chip and in the chip. The transistor characteristics may vary between the two. If the characteristics of the transistors vary, the circuit formed in the receiving device may not operate as specified.

  The LVDS receiver is no exception, and the shift of the strobe signal that occurs when the threshold value Vth of the transistor varies due to variations in the manufacturing process is a factor that further reduces the reception margin.

  In addition, this manufacturing process variation is affected by transmission line variations in the board design by the user, internal connection cables and connectors, and the operating environment at severe temperatures, resulting in skew that exceeds the reception margin. To do. Therefore, there is a problem that serial data cannot be converted normally and a reception error occurs.

  Since the LVDS receiver is used in a place where the operating temperature environment due to high-speed operation is severe and accurate impedance matching between the substrate and the transmission line is required, there is a demand for an LVDS receiver that solves the above problems.

  The present invention has been made in view of the above-described conventional problems, and it is optimal to suppress the influence of skew, manufacturing process variations, and external factors (such as transmission line and operating ambient temperature) without detecting skew. An object of the present invention is to provide an LVDS receiver, an LVDS reception method, an LVDS data transmission system, and a semiconductor device that can prevent reception errors by using a simple strobe signal.

  In order to solve the above problems, an LVDS receiver of the present invention is an LVDS receiver that inputs serial data and a clock signal and converts the serial data into parallel data in synchronization with a strobe signal. Based on the signal generation means for generating a plurality of clock signals having different phases, information on at least one of manufacturing process variations and external loads, and generating the strobe signal based on the detected information And a strobe signal for generating the strobe signal from a plurality of clock signals generated by the signal generating means in accordance with the optimum condition specified by the characteristic detection control means. And a creation means.

  The LVDS reception method of the present invention is an LVDS reception method for inputting serial data and a clock signal, and converting the serial data into parallel data in synchronization with a strobe signal, the phase of which is based on the clock signal. A first step of creating a plurality of different clock signals, a second step of detecting information of at least one of manufacturing process variation and external load, and information detected in the second step, According to the third step for specifying the optimum condition for creating the strobe signal, and the plurality of clock signals created in the first step according to the optimum condition identified in the third step, And a fourth step of creating a strobe signal.

  According to the above configuration, information on at least one of a manufacturing process variation and an external load is detected, and a strobe signal used when converting serial data into parallel data is created based on the detected information. The optimal conditions for the are identified. Then, a strobe signal is created from a plurality of clock signals according to the specified optimum condition.

  This makes it possible to create an optimum strobe signal that suppresses the influence of at least one of manufacturing process variations and external factors. In addition, since serial data is converted into parallel data in synchronization with the optimum strobe signal, reception errors can be prevented. Moreover, it is not affected by the skew at the time of conversion, and there is no need to detect the skew.

  Therefore, it is possible to prevent reception errors by using an optimal strobe signal that suppresses the influence of skew, manufacturing process variations, and external factors without detecting skew.

  Further, in the LVDS receiver according to the present invention, the characteristic detection control means includes an LUT in which the optimum conditions defined corresponding to the manufacturing process variation information and the external load information are stored, and the manufacturing process. Manufacturing process characteristic detecting means for detecting variations in the manufacturing process, external load detecting means for detecting the external load, information on manufacturing process variations detected by the manufacturing process characteristic detecting means with reference to the LUT, and external load detection Preferably, an optimum condition specifying means for specifying an optimum condition stored in the LUT from information on the external load detected by the means is provided.

  According to the above configuration, variations in manufacturing processes are detected, external loads are detected, and the optimum conditions are specified from the LUT in which the optimum conditions defined corresponding to these pieces of information are stored. Thereby, it is possible to supply the strobe signal generating means with the optimum condition specified in consideration of the variation in the manufacturing process and the influence of the external load.

  In the LVDS receiver according to the present invention, it is preferable that the manufacturing process characteristic detecting means includes a CMOS inverter circuit and an analog / digital conversion circuit that encodes and outputs the output voltage of the CMOS inverter circuit. .

  When the manufacturing process varies, the threshold values of the P-channel MOS transistor and the N-channel MOS transistor constituting the CMOS inverter circuit vary. Thereby, according to said structure, the voltage level of the output voltage of a CMOS inverter circuit is fluctuate | varied. Therefore, the analog / digital conversion circuit outputs a data signal reflecting the variation in the manufacturing process. Therefore, it is possible to create a data signal that reflects variations in the manufacturing process with a simple configuration.

  In the LVDS receiver according to the present invention, the characteristic detection control means includes temperature detection means for detecting an ambient temperature, and the LUT further stores the optimum condition defined corresponding to the ambient temperature information. The optimum condition specifying means refers to the LUT, the manufacturing process characteristic information detected by the manufacturing process characteristic detecting means, the external load information detected by the external load detecting means, and the temperature detecting means detected. It is preferable to specify the optimum condition stored in the LUT from the ambient temperature information.

  According to the above configuration, by detecting the ambient temperature, the optimum condition that is identified in consideration of the influence of the ambient temperature is identified. As a result, even when the operating temperature environment is severe, it is possible to supply the optimum condition corresponding to the operating temperature environment to the strobe signal generating means.

  The LVDS data transmission system of the present invention includes the LVDS receiver and an LVDS transmitter that outputs the serial data and the clock signal to the LVDS receiver via the LVDS transmission means.

  According to the above configuration, the LVDS receiver converts serial data to parallel data using an optimal strobe signal that suppresses the influence of skew, manufacturing process variations, and external factors, without detecting skew. Prevent receiving errors.

  For this reason, the LVDS transmitter does not need to control the skew of the serial data and the clock signal input to the LVDS receiver so as to be within a margin that can be reliably converted into parallel data. In addition, it is possible to improve the degree of freedom in the mechanism design of the substrate on which the LVDS transmitter is mounted and the transmission line. Therefore, a stable transmission / reception system can be realized.

  In addition, a semiconductor device of the present invention is characterized in that the LVDS receiver is incorporated.

  According to the above configuration, the LVDS receiver, or the LVDS receiver and its peripheral circuit can be easily realized in the form of a semiconductor device.

  As described above, the LVDS receiver according to the present invention provides at least one of information on signal generation means for generating a plurality of clock signals having different phases based on the clock signal, manufacturing process variation, and external load. Based on the detected information, characteristic detection control means for specifying an optimum condition for creating a strobe signal based on the detected information, and the signal generation means prepared according to the optimum condition specified by the characteristic detection control means A strobe signal generating means for generating the strobe signal from a plurality of clock signals is provided.

  The LVDS reception method of the present invention detects at least one of the first step of creating a plurality of clock signals having different phases based on the clock signal, manufacturing process variation, and external load. According to the second step, the third step for identifying the optimum condition for creating the strobe signal based on the information detected in the second step, and the optimum condition identified in the third step And a fourth step of creating the strobe signal from a plurality of clock signals created in the first step.

  Therefore, it is possible to create an optimum strobe signal that suppresses the influence of at least one of manufacturing process variations and external factors. In addition, since serial data is converted into parallel data in synchronization with the optimum strobe signal, reception errors can be prevented. Moreover, it is not affected by the skew at the time of conversion, and there is no need to detect the skew.

  Therefore, it is possible to prevent reception errors by using an optimal strobe signal that suppresses the influence of skew, manufacturing process variations, and external factors without detecting skew.

  The LVDS data transmission system of the present invention includes the LVDS receiver and an LVDS transmitter that outputs the serial data and the clock signal to the LVDS receiver via the LVDS transmission means.

  Therefore, the LVDS transmitter does not need to control the skew of the serial data and the clock signal input to the LVDS receiver so as to be within a margin that can be reliably converted into parallel data. In addition, it is possible to improve the degree of freedom in the mechanism design of the substrate on which the LVDS transmitter is mounted and the transmission line. Therefore, there is an effect that a stable transmission / reception system can be realized.

  The semiconductor device of the present invention incorporates the LVDS receiver.

  Therefore, the LVDS receiver, or the LVDS receiver and its peripheral circuit can be easily realized in the form of a semiconductor device.

  An embodiment of the present invention will be described below with reference to the drawings.

  FIG. 2 is a schematic configuration diagram showing an overview of the LVDS data transmission system of the present invention.

  As shown in FIG. 2, the LVDS data transmission system according to the present invention includes a LVDS (Low Voltage Differential) that uses one or more pairs of wires from the host side, for example, the LVDS transmission device 100, which is a data signal transmission side. Signal: a system that transmits digital image information and the like to the LVDS reception control device 200 (LVDS reception device) using a transmission means.

  In this specification, a receiving apparatus that performs LVDS transmission is referred to as an LVDS reception control apparatus 200. A host-side device that transmits data to the LVDS reception control device 200 is referred to as an LVDS transmission device 100.

  The LVDS transmission apparatus 100 transmits not only digital image information but also various data information corresponding to the LVDS reception control apparatus 200. The LVDS transmitting apparatus 100 converts data information to be transmitted from parallel data to serial data, and transmits the converted serial data together with a clock signal.

  The LVDS reception control device 200 is used for devices that require high-speed signal transmission, such as communication devices and display devices. For example, it is used for an FPD panel interface represented by a large LCD panel in which an operating temperature environment due to high-speed operation is severe and an accurate impedance matching between a substrate and a transmission line is required. It is also used in flat panel displays such as liquid crystal display devices and plasma display panels, liquid crystal projectors, multi-display systems, and the like.

  Next, a detailed configuration of the LVDS reception control apparatus 200 according to the present embodiment will be described.

  FIG. 1 is a block diagram illustrating a configuration example of the LVDS reception control apparatus 200.

  As shown in FIG. 1, an LVDS reception control apparatus 200 according to the present embodiment includes a serial / parallel converter circuit (Serial / Parallel Converter) 201, a strobe selection circuit 202 (strobe signal generating means), and a PLL circuit 203 (signal generating means). ), LUT (Look Up Table) 204, register control unit 205 (optimum condition specifying means, external load detecting means), Vth detecting circuit 206 (manufacturing process characteristic detecting means), temperature sensor 207 (temperature detecting means), and LVDS / CMOS conversion units (LVDS to CMOS) 211 to 215 are provided.

  The serial / parallel conversion circuit 201 is a circuit which converts CMOS level serial data into parallel data. Specifically, the serial / parallel conversion circuit 201 synchronizes the serial data output from the LVDS / CMOS conversion units 211 to 214 with respect to each channel in synchronization with the optimum strobe signal output from the strobe selection circuit 202. Convert to parallel data. Further, the serial / parallel conversion circuit 201 outputs the converted parallel data (outputs A to D) to, for example, a subsequent circuit unit such as a memory unit or a control unit.

  The strobe selection circuit 202 creates an optimum strobe signal from a plurality of sampling clocks created by the PLL circuit 203. Specifically, the strobe selection circuit 202 selects an optimum sampling from a plurality of sampling clocks output from the PLL circuit 203 based on a data signal (LTR) indicating an optimum strobe signal selection condition output from the LUT 204. Select a clock to create an optimal strobe signal. The strobe signal is a signal such as a pulse signal with instantaneous input time and output time.

  The strobe selection circuit 202 is configured by a MUX (multiplexer) circuit or the like. The strobe selection circuit 202 outputs the selected sampling clock to the serial / parallel conversion circuit 201.

  The PLL circuit 203 is a circuit that generates a plurality of sampling clocks having different phases synchronized with the clock signal output from the LVDS / CMOS conversion unit 215. The plurality of sampling clocks are a basis for creating a strobe signal used in the serial / parallel conversion circuit 201. The PLL circuit 203 outputs the created sampling clocks to the strobe selection circuit 202.

  Here, as an example, a detailed configuration of the PLL circuit 203 is shown in FIG.

  As shown in FIG. 3, the PLL circuit 203 includes a phase comparator 221, a charge pump 222, an LPF (low pass filter) 223, a VCO (voltage controlled oscillator) 224, and a frequency divider 225. Circuit.

  The phase comparator 221 detects a phase difference between the reference signal CK and the feedback signal FP from the frequency divider 225. Then, the control signal UP for increasing the oscillation frequency of the VCO 224 or the control signal DN for decreasing it is output to the charge pump 222 according to the detection result.

  Specifically, when the feedback signal FP is delayed with respect to the reference signal CK, the phase comparator 221 outputs a control signal UP that increases the oscillation frequency of the VCO 224 for a period corresponding to the phase difference. Conversely, when the feedback signal FP is advanced with respect to the reference signal CK, the phase comparator 221 outputs a control signal DN for decreasing the oscillation frequency of the VCO 224 for a period corresponding to the phase difference. Therefore, the phase comparator 221 outputs to the charge pump 222 a signal obtained by converting the phase difference between the two input signals into a pulse width.

  The charge pump 222 converts the control signals UP and DN from the phase comparator 221 into analog signals. Then, the output signal CPO is passed through the LPF 223 and given to the VCO 224 as the control voltage Vc.

  The LPF 223 includes a resistor and a capacitor. The LPF 223 is used for the purpose of reducing switching noise included in the output signal CPO from the charge pump 222 and the purpose of stabilizing the feedback loop.

  The VCO 224 creates a plurality of clocks with different phases that are output as the PLL circuit 203 according to the oscillation frequency. The detailed configuration of the VCO 224 will be described later. The output signal of the VCO 224 is output as the output signal Clock of the PLL circuit 203 shown in FIG. 1, and is divided by the frequency divider 225 and input to the phase comparator 221 as the feedback signal FP.

  At that time, the output signal of the VCO 224 is converted into a frequency of 1 / N by the frequency divider 225. Thereby, the relationship between the frequencies of the feedback signal FP and the output signal is expressed by the following equation (1), where the output signal of the VCO 224 is fo. The frequency divider 225 can change the frequency division ratio.

FP = fo / N (1)
The PLL circuit 203 controls the control voltage Vc so that CK = FP. For this reason, the output signal fo is expressed as the following equation (2). That is, an output signal fo having a frequency N times that of the reference signal CK is output from the PLL circuit 203.

fo = N × CK (2)
Next, a detailed configuration of the VCO 224 will be described. FIG. 4 is a circuit diagram showing a schematic configuration of the VCO 224.

  As shown in FIG. 4, the VCO 224 has a configuration including an M-stage ring oscillator 231 (M: odd number) whose oscillation frequency changes according to the input control voltage Vc.

  In the present invention, the output signals phi 1 to phi (M) output from the taps of the M inverter elements constituting the M-stage ring oscillator 231 are used as the output of the PLL circuit 203. Further, the output signal phi1 becomes the output signal fo of the VCO 224.

  With the above configuration, the output signals phi1 to phi (M) that are the outputs of the PLL circuit 203 have a frequency that is a frequency division ratio (N) times that of the reference signal CK. When the period of the reference signal CK is T, each phase is an output signal delayed by T / (N · M). That is, the output signals phi1 to phi (M) are a plurality of sampling clocks output from the PLL circuit 203 and having different phases.

  The LUT 204 is a storage unit that stores a control data table for selecting an optimal strobe signal.

  For example, in the LUT 204, the movement amount (deviation) of a plurality of sampling clocks output from the PLL circuit 203, which is defined corresponding to the variation in the manufacturing process, is first, and the board, the connector, The amount of skew defined corresponding to the external load of the transmission line such as cables, and thirdly, it has an adverse effect on serial parallel conversion such as the effect on the circuit defined corresponding to the ambient temperature of the operating environment. Parameters that are measured in advance by simulation or the like are stored for various factors. In addition, a control data table that defines conditions for creating the optimum strobe signal in accordance with the parameters and combinations of the parameters is stored.

  Further, the parameters stored in the LUT 204 are not limited to the three parameters described above, and it is preferable to additionally store settings for each additional condition as appropriate even when other conditions such as a load condition are added. Therefore, the LVDS reception control apparatus 200 corresponding to all the above-described factors can be realized by storing in the LUT 204 the setting of conditions for each factor regarding various factors that adversely affect the serial / parallel conversion assumed in advance. Is possible.

  The register control unit 205 indicates a data signal (CL) indicating the state of a load such as a transmission line, a data signal (VthS) indicating a result of manufacturing variation by the Vth detection circuit 206, and an ambient temperature measurement result by the temperature sensor 207. A data signal (SC) is input, and these signals are combined to create a register output signal (RG). Then, this register output signal is output to the LUT 204, and the optimum strobe signal selection condition stored in the LUT 204 is specified based on the register output signal. The register control unit 205 gives the specified optimum strobe signal selection condition to the strobe selection circuit 202.

  The Vth detection circuit 206 is a circuit that detects manufacturing variations in the LVDS reception control apparatus 200. The Vth detection circuit 206 outputs the detected manufacturing variation detection result to the register control unit 205. Here, as an example, a detailed configuration of the Vth detection circuit 206 is shown in FIG.

  As shown in FIG. 5, the Vth detection circuit 206 includes a CMOS inverter circuit composed of a P-channel MOS transistor 241 and an N-channel MOS transistor 242, and an A / D converter 243 (analog / digital conversion circuit). ing. According to the above configuration, the output voltage V obtained by short-circuiting the input / output of the CMOS inverter circuit can be encoded by inputting the output voltage V to the A / D converter 243.

  If the manufacturing process varies, the threshold values (Vth) of the P-channel MOS transistor 241 and the N-channel MOS transistor 242 vary. Thereby, the voltage level of the output voltage V of the CMOS inverter circuit changes. Therefore, the Vth detection circuit 206 can detect manufacturing process variations.

  The temperature sensor 207 is a circuit that detects the ambient temperature of the LVDS reception control apparatus 200. The temperature sensor 207 outputs the measurement result of the ambient temperature to the register control unit 205.

  Note that the LUT 204, the register control unit 205, the Vth detection circuit 206, and the temperature sensor 207 constitute a characteristic detection control unit 210 (characteristic detection control means). In other words, the characteristic detection control unit 210 detects, in the LVDS reception control device 200, information that adversely affects serial / parallel conversion such as variations in manufacturing process, external load, and ambient temperature, and the optimum strobe is detected based on the detected information. This is a part for specifying the signal selection condition.

  The LVDS / CMOS converters 211 to 214 are parts that convert LVDS to a CMOS level. Specifically, the LVDS / CMOS converters 211 to 214 input LVDS from the LVDS transmission control device (LA to LD), convert them to the CMOS level, and then output them to the serial / parallel converter circuit 201, respectively. Serial data is input to each channel of the LVDS / CMOS conversion units 211 to 214, respectively.

  The LVDS / CMOS conversion unit 215 is a part that converts LVDS into a CMOS level. Specifically, the LVDS / CMOS conversion unit 215 inputs (LCK) the LVDS from the LVDS transmission control device, converts the LVDS to a CMOS level, and then outputs the LVDS to the PLL circuit 203. Note that a clock signal is input to the LVDS / CMOS conversion unit 215.

  Here, as described with reference to FIG. 2, the LVDS reception control apparatus 200 receives the serial data and the clock signal transmitted from the LVDS transmission apparatus 100 via the LVDS transmission. When the propagation times of the serial data and the clock signal are different at the time of reception, a skew (Skew) that is a variation in the phase of the signal occurs between the two signals.

  Therefore, next, data reception of the LVDS reception control apparatus 200 in a skew occurrence state will be described with reference to FIGS.

  FIG. 6 is a diagram for explaining data capture in the LVDS reception control apparatus 200 when there is no skew in the data.

  FIG. 7 is a diagram for explaining data capture in the LVDS reception control apparatus 200 when the strobe signal is shifted to the delay side.

  FIG. 8 is a diagram for explaining data capture in the LVDS reception control apparatus 200 when the strobe signal is shifted to the advance side.

  FIG. 9 is a diagram for explaining a reception error in the LVDS reception control apparatus 200 when the strobe signal is shifted to the delay side and there is an advance skew.

  6 to 9 show the parameters in the serial / parallel conversion circuit 201 in time series when 7-bit serial data is received in one clock cycle. LA is output data from the LVDS / CMOS converter 211, LB is output data from the LVDS / CMOS converter 212, LC is output data from the LVDS / CMOS converter 213, and LD is output from the LVDS / CMOS converter 214. Data and LCK indicate output clock signals from the LVDS / CMOS conversion unit 215. Strb1 to Strb7 indicate strobe signals generated by the strobe selection circuit 202, and outputs A to D indicate parallel data output from the serial / parallel conversion circuit 201.

  Normally, LVDS serial data (LA to LD, LCK) is transmitted without skew as shown in FIG. At this time, if there is no variation in the manufacturing process of the LVDS reception control device 200 and Vth is the center of the target, the generated strobe signals Strb1 to Strb7 are located at the center with respect to the LVDS serial data.

  The strobe signals Strb1 to Strb7 are located at the center from the time Setup · Time from the beginning of the 1-bit data to the strobe signal located at the center of the 1-bit data and from the strobe signal to the end of the 1-bit data. The time Hold · Time is maximized.

  However, when a manufacturing process variation (Vth variation) occurs in the LVDS reception control apparatus 200, the strobe signals Strb1 to Strb7 shift (shift from the synchronized position).

  When the strobe signals Strb1 to Strb7 are shifted to the delay side (backward), as shown in FIG. 7, the Hold / Time margin of the LVDS serial data LA to LD is reduced with respect to the strobe signals Strb1 to Strb7.

  On the other hand, when the strobe signals Strb1 to Strb7 are shifted to the advance side (front), the setup / time margin of the LVDS serial data LA to LD is reduced with respect to the strobe signals Strb1 to Strb7 as shown in FIG. become.

  As shown in FIGS. 7 and 8, if the Hold · Time margin and the Setup · Time margin remain, data can be captured even if the strobe signal is shifted.

  However, for example, in the case shown in FIG. 7, when the transmission system is such that a skew occurs between the LVDS serial data and the LVDS clock signal due to a problem in designing the transmission line, the transmission system shown in FIG. Thus, a reception error will occur. FIG. 9 shows an example in which a skew has occurred in the LVDS serial data LC.

  Therefore, as shown in FIG. 9, when the strobe signal for sampling the LVDS serial data is shifted due to the variation of Vth, and further, a skew occurs between the LVDS clock signal and the LVDS serial data due to the influence of the transmission line. It cannot be dealt with.

  On the other hand, the LVDS reception control apparatus 200 according to the present embodiment includes a Vth detection circuit 206 and inputs a CL signal indicating the state of the transmission line, thereby causing a physical factor (transmission line) of the LVDS reception control apparatus 200. Information, unequal length wiring) and information obtained by encoding the shift amount due to the variation of Vth, the register control unit 205 refers to the LUT 204 to identify and identify conditions for creating an optimal strobe signal A data signal indicating the condition is output to the strobe selection circuit 202.

  As a result, it is possible to correct the shift of the strobe signals Strb1 to Strb7 of the LVDS serial data due to variations in the manufacturing process of the LVDS reception control device 200, and to maximize the Setup / Hold / Time margin of the LVDS serial data with respect to the strobe signals Strb1 to Strb7. It becomes. At the same time, it is possible to realize a stable LVDS reception control apparatus 200 that is not affected by variations in manufacturing process variations and skew due to transmission line factors.

  That is, in the LVDS reception control apparatus 200 of the present embodiment, as shown in FIG. 10, an optimum strobe signal is created for each channel, and serial / parallel conversion can be performed.

  Next, a series of operations for creating an optimum strobe signal for each channel in LVDS reception control apparatus 200 of the present embodiment will be described. Here, in the following description, in order to make the description easy to understand, the LVDS reception control device 250 (LVDS reception device) having LVDS serial data of 1ch (LA) shown in FIG. 11 is used.

  As shown in FIG. 11, the LVDS reception control apparatus 250 of the present embodiment has the same configuration as that of the LVDS reception control apparatus 200 excluding the LVDS / CMOS conversion units 212 to 214. Further, the LVDS reception control apparatus 250 according to the present embodiment performs LVDS data transmission with the LVDS transmission apparatus (LVDSTx) 150 as shown in FIG.

  FIG. 12 is a configuration diagram illustrating a configuration example of an LVDS data transmission system of the LVDS reception control device 250 and the LVDS transmission device 150.

  The LVDS reception control device 250 includes a connector 251 that is an externally connectable terminal that receives serial data.

  The LVDS transmission device 150 is a transmitter such as an IC chip having a function capable of transmitting serial data and a clock signal. The LVDS transmitter 150 is mounted on the printed circuit board 161, and includes a connector 162 attached to the same printed circuit board 161 and wiring that connects the input / output unit of the LVDS transmitter 150 and the input / output unit of the connector 162. It is configured to allow data transmission with the outside.

  The LVDS transmission device 150 and the LVDS reception control device 250 are connected by a cable 171 that transmits serial data including data information and a cable 172 that transmits a clock signal.

  In the PLL circuit 203, as shown in FIG. 13, the number of oscillator elements of the VCO 224 is set to 14 and the output signals Phi1 to Phi28 are generated. Note that the resolution of the output signal Phi to be created can be set by changing the number of stages (M) of the VCO 224. The higher the resolution, the higher the ability to prevent reception errors.

  First, 7-bit LVDS serial data (LA) and LVDS clock signal (LCK) are transmitted from the LVDS transmission device 150 in one clock cycle to the wiring formed on the printed circuit board 161, the connector 162, the cables 171 and 172, and the connector 251. The data is input to the LVDS / CMOS conversion units 211 and 215 of the LVDS reception control device 250 in order.

  In addition, a 2-bit CL signal is input to the register control unit 205. The CL signal [1: 0] is a signal indicating information (board, cable, etc.) of the transmission line difference (skew) of the LA and LCK lines to the LVDS reception control device 250. At this time, LA and LCK may be input in a timing chart as shown in FIG.

  For example, as shown in FIG. 14A, the CL signal [1: 0] is supplied as a signal of CL [1: 0] = [00] when there is no LA line length difference from the LCK. . As shown in FIG. 14B, when the LA transmission path length is longer than the LCK, that is, when the LA is delayed with respect to the LCK, a signal CL [1: 0] = [01] is obtained. Supplied. On the contrary, as shown in FIG. 14C, when the transmission line length of the LA is shorter than the LCK, that is, when the LA is advanced with respect to the LCK, CL [1: 0] = [10] Is supplied as a signal.

  This CL signal is transmission line information including the board wiring on the transmission side. Therefore, since this information is information that can be known on the connected transmission side, even if there is a change on the transmission side, it is possible to cope with any transmission line change on the transmission side by controlling this signal.

  The CL signal is not limited to 2 bits as long as the relationship between LCK and LA is set in advance. By setting information in which the relationship of LCK to LA is set in the CL signal in the register control unit 205, it is possible for the register control unit 205 to detect the CL signal and obtain information on whether skew has occurred. It becomes.

  On the other hand, the Vth detection circuit 206 detects a combination of Vth caused by variations in the manufacturing process of the LVDS reception control device 250.

  Here, the combination of Vth will be described with reference to FIG.

  The combination of characteristics of the P-channel MOS transistor 241 and the N-channel MOS transistor 242 is roughly limited to the following five conditions. That is, Vth (Pch, Nch) = (Typical, Typical), (High, High), (High, Low), (Low, High), (Low, Low). Therefore, the Vth detection circuit 206 detects which characteristic corresponds to the above five conditions.

  For example, if Vth (Pch, Nch) = (High, High), the Vth detection circuit 206 outputs the output voltage V of the CMOS inverter circuit in response to this, and AD is shown to indicate (high, high). Encoded by the converter.

  In the present invention, the typical value means the Vth target value of the manufacturing process. High means that the Vth voltage is higher than the typical value. Conversely, Low means that the Vth voltage is lower than the typical value.

  In addition, the threshold voltage Vth of the transistor formed on the semiconductor varies for each manufacturing process. If the manufacturing target Vth center value (Typical) is, for example, Vth (Pch, Nch) = (− 0.70 V, 0.55 V), there is a variation of about ± 0.15 V.

  In this case, Vth (Pch, Nch) = (High, High) means a combination having a high absolute value of Vth in the range of the above-described variation, and Vth (Pch, Nch) = (− 0.85 V, 0 .70V). On the other hand, the value in the case of Vth (Pch, Nch) = (Low, Low) means a combination having a low absolute value of Vth, and Vth (Pch, Nch) = (− 0.55V, 0.40V). It becomes.

  That is, in the Vth detection circuit 206, the voltage value of the output voltage V shown in FIG. 5 differs depending on the combination of Vth of the P-channel MOS transistor 241 and the N-channel MOS transistor 242.

  Therefore, the output voltage V when Vth (Pch, Nch) = (High, High) is higher than the output voltage V when Vth (Pch, Nch) = (Typical, Typical). On the other hand, the output voltage V when Vth (Pch, Nch) = (Low, Low) is lower than the output voltage V when Vth (Pch, Nch) = (Typical, Typical).

  In the Vth detection circuit 206, since the combination range of Vth is determined, the result of encoding the output voltage V by the A / D converter 243 is determined within a range corresponding to the combination. Therefore, it is possible to detect the state of Vth (High, Typical, Low) by allocating the encoding range for each combination.

  For example, when the A / D converter 243 is a 4-bit AD converter, when Vth (Pch, Nch) = (Typical, Typical), [0100] to [1100], Vth (Pch, Nch) = (High, High) In the case of [1101] to [1111], the encoding range can be allocated.

  Therefore, since the output voltage V of the CMOS inverter circuit varies depending on the combination of Vth, the output after AD conversion of the Vth detection circuit 206 is encoded to reflect the variation of the Vth characteristic. It is possible to detect Vth with a data signal.

  As described above, the CL signal and the output signal (Vth detection result VthS) of the Vth detection circuit 206 are input to the register control unit 205.

  In the register control unit 205, the CL signal and the Vth detection result VthS are combined, and the LUT data LTR corresponding to the combination result is supplied to the strobe selection circuit 202 with reference to the LUT 204.

  As an example, the Vth detection result VthS is 2 bits, the CL signal is 2 bits, and the output signal RG from the register control unit 205 is a 4 bit [3: 0] register. Assuming that RG [3: 0] = [VthS + CL], the LUT data LTR of the LUT 204 corresponding to the RG [3: 0] value is supplied to the strobe selection circuit 202.

  The combinations of VthS are: when VthS = (Typical, Typical): VthS = [01], when VthS = (High, High): VthS = [11], when VthS = (Low, Low): VthS = [ 00]. Further, as shown in FIG. 14 as the transmission line information, the CL signal [1: 0] is (A) when there is no skew between LA and LCK: CL [1: 0] = [00], (B ) When LA is delayed for LCK: CL [1: 0] = [01], (C) When LA is advanced for LCK: CL [1: 0] = [10] .

  For example, when VthS [1: 0] = [01] and CL [1: 0] = [00], the register control unit 205 sets RG [3: 0] = [0100] ([01: VthS, 00: CL]) and output to the LUT 204.

  In the LUT 204, table data corresponding to a combination of RG = [VthS + CL] is set, and setting data of optimum strobe signal selection conditions to be supplied to the strobe selection circuit 202 is stored according to the combination of RG. .

  In the LUT 204 to which RG [3: 0] = [0100] is supplied, the LUT data corresponding to RG = [0100] (Vth is [Typical, Typical], CL is no skew) is the optimum strobe signal selection condition. It is output to the strobe selection circuit 202.

  Next, based on the LUT data corresponding to the RG value, that is, the optimum strobe signal selection condition, the strobe selection circuit 202 selects the optimum strobe signal and supplies it to the serial / parallel conversion circuit 201. Thereby, it is possible to provide the LVDS reception control device 250 having an excellent skew margin.

  Further, by adding the detection result of the temperature sensor 207, an LVDS reception control device 250 having an excellent skew margin is provided without being affected by the operating environment in addition to the manufacturing variation (Vth) and the state (CL) of the printed circuit board 161. be able to.

  As an example, the Vth detection result VthS of the Vth detection circuit 206 is 2 bits, the CL signal indicating the skew information such as the substrate wiring is 2 bits, the detection result SC of the temperature sensor 207 is 1 bit, and the LVDS reception reflecting the result of the temperature sensor 207 is received. The operation of the control device 250 will be described. At this time, the output signal RG from the register control unit 205 is a 5-bit [4: 0] register.

  The detection result SC of the temperature sensor 207 outputs “1” when the temperature is higher than a certain temperature, and outputs “0” when the temperature is lower than a certain temperature. The combination of VthS and the CL signal are the same as those described above.

  The register control unit 205 outputs RG [4: 0] = [VthS + CL + SC], which is a combination of VthS, CL, and SC, to the LUT 204. In the LUT 204, LUT data LTR corresponding to the RG [4: 0] value is supplied to the strobe selection circuit 202 and supplied to the serial / parallel conversion circuit 201. Accordingly, it is possible to provide the LVDS reception control device 250 that is not affected by the operating environment and has an excellent skew margin.

  Note that the combination of VthS, CL, and SC in the output signal RG of the register control unit 205 is not limited to the order described above, and other parameters may be combined. A control data table stored in the LUT 204 is set according to the combination of the output signals RG of the register control unit 205.

  Subsequently, as an example, when Vth (Pch, Nch) = (Typical, Typical) and there is no CL signal (that is, there is no skew due to an external factor), a process of selecting an optimum strobe signal is illustrated. Is shown in FIG.

  In the case illustrated in FIG. 15, the register control unit 205 refers to the LUT 204 according to the CL signal [00] and the Vth detection result (Typical, Typical), and sets the LUT data [00] as the optimum strobe signal selection condition. Identified. The LUT data [00] is output to the strobe selection circuit 202.

  The LUT data [00] includes Vth (Typical, Typical) and a plurality of sampling clocks (output signals Phi1 to Phi28 (Phi [1:28])) output from the PLL circuit 203 when there is no external skew. The optimum strobe signal selection condition for selecting the optimum sampling clock from the above and creating the optimum strobe signal is defined.

  In the strobe selection circuit 202, an output signal is selected from the output signals Phi1 to Phi28 generated by the PLL circuit 203 in accordance with the LUT data [00], and an optimal strobe signal is generated. It is output to the conversion circuit 201. In the example shown in FIG. 15, the strobe signal indicated by the thick line arrow is selected as the optimum for the data D1, such as Phi [3], according to the LUT data [00]. Yes.

  As a result, the serial / parallel conversion circuit 201 can convert serial data into parallel data in synchronization with the optimum strobe signal, and can prevent reception errors.

  FIG. 16 illustrates a process of selecting an optimum strobe signal when Vth (Pch, Nch) = (High, High) and there is no CL signal (that is, there is no skew due to an external factor). Shown in

  In the case illustrated in FIG. 16, the register control unit 205 refers to the LUT 204 in accordance with the CL signal [00] and the Vth detection result (High, High), and the LUT data [01] as the optimum strobe signal selection condition is obtained. Identified. The LUT data [01] is output to the strobe selection circuit 202.

  The LUT data [01] selects an optimum sampling clock from a plurality of sampling clocks (output signals Phi1 to Phi28) output from the PLL circuit 203 when there is no Vth (High, High) and external skew. The optimum strobe signal selection condition for creating the optimum strobe signal is defined.

  In the strobe selection circuit 202, an output signal is selected from the output signals Phi1 to Phi28 generated by the PLL circuit 203 in accordance with the LUT data [01], and an optimal strobe signal is generated. It is output to the conversion circuit 201. In the example shown in FIG. 16, the strobe signal indicated by the bold arrow is selected as the optimum for the data D1, such as Phi [2], according to the LUT data [01]. Yes.

  Here, the output signals Phi1 to Phi28 created by the PLL circuit 203 shift back and forth due to manufacturing process variations, that is, combinations of Vth. It can be known in advance by performing a simulation of the PLL circuit 203 whether to move forward or backward depending on the combination of Vth.

  For example, as shown in FIG. 16, in the case of Vth (High, High), as indicated by an arrow X, the output signals Phi1 to Phi28 are shifted to the Delay side with respect to the position at the time of Typical. This is because the response speed of the transistor becomes slow when the absolute value of Vth is high. As a result, Phi [1:28] for sampling data is delayed for the time indicated by arrow X.

  Therefore, paying attention to the data D1, in the example shown in FIG. 15, since there is no Vth detection, the data D1 is sampled with Phi [3]. On the other hand, in the example shown in FIG. 16, Phi [1:28] is delayed, so Phi [3] is shifted to the Delay (right) side with respect to data D1. For this reason, the hold time, that is, the hold margin is small.

  Therefore, since it is known that Phi [1:28] shifts to the Delay side when Vth is high, the Vth detection circuit 206 performs Vth detection, so that the absolute value of the detection result Vth is high. If so, Phi [2] is selected as in the example shown in FIG. As a result, it is possible to sample the data D1 using Phi that maximizes the setup and hold time margins of Phi for the data D1.

  Therefore, the serial / parallel conversion circuit 201 is supplied with the optimum strobe signal in consideration of the shift effect of the output signals Phi1 to Phi28. Therefore, the serial data is converted into parallel data in synchronization with the optimum strobe signal without any problem. Conversion is possible, and reception errors can be prevented.

  In addition, it is known in advance that the characteristics of semiconductor elements are shifted depending on the operating temperature. That is, Vth shifts to a higher absolute value side as the temperature rises. Therefore, a Vth detection circuit 206, a CL signal indicating transmission line information, and a temperature sensor 207 are provided, and these results are combined by the register control unit 205, and LUT data supplied from the LUT 204 to the strobe selection circuit 202 according to the combination result. By reading the value of the LTR, it is possible to provide a stable LVDS reception control device 250 without being affected by manufacturing variations, transmission line information such as substrate wiring, and the operating environment.

  As described above, since it is possible to prevent reception errors without being affected by variations in manufacturing processes and skew due to transmission line differences, a stable LVDS reception control device 250 can be realized. Become.

  That is, the LVDS reception control devices 200 and 250 of the present embodiment detect variations in the manufacturing process, and based on the detection results and external factor data such as transmission line length differences such as user boards, connectors, and cables. Means for specifying an optimum strobe signal selection condition and generating an optimum strobe signal based on the specified condition.

  As a result, it is possible to select an optimum strobe signal that is not affected by variations in manufacturing processes and external skew such as transmission line length differences.

  In addition, the LVDS reception control devices 200 and 250 according to the present embodiment are optimum in that the influence of the ambient temperature is further suppressed by considering the operating ambient temperature in addition to the external factors such as the variation of the manufacturing process and the transmission line length difference. Specific strobe signal selection conditions are specified. As a result, even when the operating environment is severe, it becomes possible to perform serial-parallel change stably.

  Furthermore, in LVDS reception control apparatuses 200 and 250 of the present embodiment, there is no influence of skew during conversion, and there is no need to detect skew. In other words, since the LVDS reception control devices 200 and 250 of the present embodiment suppress the influence of skew by the CL signal, they are provided with a function (De-Skew function) for correcting (cancelling) skew. Become.

  For this reason, in the LVDS data transmission system, on the host side (LVDS transmitters 100 and 150), it is possible to improve the degree of freedom of user design including the mechanism design of transmission lines such as set boards, connectors, and cables. .

  Further, in the LVDS transmission apparatus, it is not necessary to control the skew of the serial data and the clock signal input to the LVDS reception apparatus to be within a margin that can be reliably converted into parallel data. Therefore, a stable transmission / reception system can be realized.

  By the way, the LVDS reception control devices 200 and 250 of the present embodiment may be built in a semiconductor device. Thereby, the LVDS reception control devices 200 and 250, or the LVDS reception control devices 200 and 250 and their peripheral circuits can be easily realized in the form of an IC.

  In addition, this invention is not limited to embodiment mentioned above, A various change is possible in the range shown to the claim. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be applied to an LVDS receiver used for an FPD panel interface, represented by a large LCD panel, which has a severe operating temperature environment due to high-speed operation and requires accurate impedance matching of a substrate and a transmission line. Not limited to this, it can be applied to other fields. For example, due to the effects of fluctuations such as heat treatment that occur in the manufacturing process, the fluctuations affect the element shape and physical properties, and the built-in component characteristics vary, so the circuit may not operate as specified. The present invention can also be applied to a receiving device that is generated.

It is a block diagram which shows one Embodiment of the LVDS receiver in this invention. It is a schematic block diagram which shows the outline of the LVDS data transmission system containing the said LVDS receiver. It is a block diagram which shows the structure of the PLL circuit in the said LVDS receiver. It is a circuit diagram which shows the structure of VCO in the said PLL circuit. It is a circuit diagram which shows the structure of the Vth detection circuit in the said LVDS receiver. It is a timing chart which shows input data, a clock signal, a strobe signal, and output data in time series when there is no skew in the LVDS receiver. It is a timing chart which shows input data, a clock signal, a strobe signal, and output data in time series when the strobe signal in the LVDS receiver shifts to the delay side. It is a timing chart which shows input data, a clock signal, a strobe signal, and output data in time series when the strobe signal in the LVDS receiver shifts to the advance side. FIG. 5 is a timing chart showing time series of input data, a clock signal, a strobe signal, and output data when the strobe signal is shifted to the delay side and there is a lead skew and a reception error occurs in the LVDS receiver. is there. It is a timing chart which shows the result of having selected the optimal strobe signal in the said LVDS receiver. It is a block diagram which shows other embodiment of the LVDS receiver in this invention. It is a schematic diagram which shows the connection structure of the said LVDS receiver and LVDS transmitter. It is a block diagram which shows the structure of the PLL circuit in the said LVDS receiver. It is a figure for demonstrating the combination of the state of CL signal in the said LVDS receiver. It is a figure for demonstrating an example of the process which selects the optimal strobe signal in the said LVDS receiver. It is a figure for demonstrating the other example of the process which selects the optimal strobe signal in the said LVDS receiver. It is a schematic block diagram which shows the outline of the conventional LVDS data transmission system. It is a block diagram which shows the structure of the conventional LVDS receiver. It is a figure for demonstrating the example of a skew detection when there is no skew in the said conventional LVDS receiver. It is a figure for demonstrating the example of a skew detection in the said conventional LVDS receiver in case there exists advance skew. It is a figure for demonstrating the example of a skew detection in the said conventional LVDS receiver in case there exists a delay skew.

Explanation of symbols

100,150 LVDS transmitter 162 Connector 171,172 Cable 200,250 LVDS reception controller (LVDS receiver)
201 serial / parallel conversion circuit 202 strobe selection circuit (strobe signal generating means)
203 PLL circuit (signal generating means)
204 LUT
205 Register control unit (optimum condition specifying means, external load detecting means)
206 Vth detection circuit (manufacturing process characteristic detection means)
207 Temperature sensor (temperature detection means)
210 Characteristic detection control unit (characteristic detection control means)
211 to 215 LVDS / CMOS converter 241 P-channel MOS transistor (CMOS inverter circuit)
242 N-channel MOS transistor (CMOS inverter circuit)
243 A / D converter (analog / digital conversion circuit)
251 connector

Claims (7)

An LVDS receiver that inputs serial data and a clock signal and converts the serial data into parallel data in synchronization with a strobe signal,
Signal generating means for creating a plurality of clock signals having different phases based on the clock signal;
Characteristic detection control means for detecting information on at least one of manufacturing process variation and external load, and identifying optimum conditions for creating the strobe signal based on the detected information;
An LVDS receiving apparatus comprising: strobe signal generating means for generating the strobe signal from a plurality of clock signals generated by the signal generating means in accordance with the optimum condition specified by the characteristic detection control means. . The characteristic detection control means includes
An LUT in which the optimum conditions defined corresponding to the manufacturing process variation information and the external load information are stored;
Manufacturing process characteristic detecting means for detecting variations in the manufacturing process;
An external load detecting means for detecting the external load;
Referring to the LUT, an optimum condition for specifying an optimum condition stored in the LUT from information on the variation in the production process detected by the production process characteristic detection means and information on the external load detected by the external load detection means The LVDS receiver according to claim 1, further comprising a specifying unit. The manufacturing process characteristic detecting means includes:
A CMOS inverter circuit;
3. The LVDS receiver according to claim 2, comprising an analog / digital conversion circuit that encodes and outputs an output voltage of the CMOS inverter circuit. The characteristic detection control means includes a temperature detection means for detecting an ambient temperature,
In the LUT, the optimum condition defined corresponding to the ambient temperature information is stored.
The optimum condition specifying means refers to the LUT, the manufacturing process variation information detected by the manufacturing process characteristic detecting means, the external load information detected by the external load detecting means, and the ambient temperature detected by the temperature detecting means. 3. The LVDS receiver according to claim 2, wherein an optimum condition stored in the LUT is specified from temperature information. An LVDS receiving method for inputting serial data and a clock signal and converting the serial data into parallel data in synchronization with a strobe signal,
A first step of creating a plurality of clock signals having different phases based on the clock signal;
A second step of detecting information on at least one of manufacturing process variation and external load;
A third step of specifying an optimum condition for generating the strobe signal based on the information detected in the second step;
LVDS reception comprising: a fourth step of generating the strobe signal from a plurality of clock signals generated in the first step according to the optimum condition specified in the third step Method. LVDS receiver according to any one of claims 1 to 4,
An LVDS data transmission system comprising: an LVDS transmission device that outputs the serial data and the clock signal to the LVDS reception device via an LVDS transmission means.   A semiconductor device comprising the LVDS receiver according to claim 1.

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