JP2008217848A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device such as a DRAM, wherein a circuit evaluation of a relief circuit is made possible even though there is no product in which the defective cell exists, and efficiency of debugging of a program for evaluating the relief circuit or relieving a defective address is improved. <P>SOLUTION: A pseudo error signal generation circuit 2 is incorporated in a data amplifier 1 which reads data stored in a memory cell of the semiconductor integrated circuit device. The pseudo error signal generation circuit 2 deactivates the data amplifier 1 when a test mode enable signal is activated, and outputs a signal becoming defective data ("H" or "L" signal against expected data) in place of the data amplifier 1. Also, when a data amplifier enable signal is activated, the data amplifier 1 is activated and data of the memory cell read by the data amplifier 1 are output. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor memory device such as a DRAM (Dynamic Random Access Memory).

  In a memory product represented by a DRAM, a semiconductor circuit technology for relieving a defective address (defective memory cell) in a post-assembly process has been generalized.

  FIG. 2 is a block diagram showing a circuit configuration of a conventional semiconductor integrated circuit device (see Patent Document 1), and FIG. 4 is a diagram showing a configuration example obtained by improving the semiconductor integrated circuit device shown in FIG. (See Patent Document 2).

  Details of the circuits shown in FIGS. 2 and 4 are described in Patent Documents 1 and 2, and an outline thereof will be described here.

  FIG. 2 is a diagram showing a circuit configuration of the semiconductor integrated circuit device (SDRAM) disclosed in Patent Document 1. In FIG. In the circuit shown in FIG. 2, in addition to a fuse 20B used to relieve a defective address of a memory cell, an electrically programmable non-volatile memory for the purpose of relieving a defect after the assembly of a DRAM. (NVRAM) 20A is mounted. Note that all the circuit blocks shown in FIG. 2 are formed on one semiconductor chip such as single crystal silicon.

  An SDRAM (Synchronous Dynamic Random Access Memory) 10 shown in FIG. 2 operates in synchronization with a clock. The SDRAM 10 includes a memory cell array 11, an address buffer 12, a row address decoder 13, a column address decoder 14, a sense amplifier 15, a command decoder 16, a mode register 17, a control circuit 18, and a data input / output circuit 19. And an address comparison circuit 20 and a clock generation circuit 21.

  The memory cell array 11 includes a plurality of memory cells arranged in a matrix, and includes, for example, four banks BANK0 to BANK3. The address buffer 12 takes in address data (hereinafter abbreviated as “address”) input from the outside in a multiplex manner. The column address decoder 14 decodes the column address fetched by the address buffer 12 and selects a corresponding column (bit line) in the memory cell array 11.

  The row address decoder 13 decodes the row address fetched by the address buffer 12 and selects a corresponding word line in the memory cell array 11. The sense amplifier 15 amplifies and outputs the potential of the selected bit line when reading data, and writes external data into the memory cell when writing data. The command decoder 16 interprets a command in response to a control signal such as a chip select signal / CS input from the outside.

  An operation mode is set in the mode register 17 according to the input command. The control circuit 18 generates an internal control signal according to the input command and the state of the mode register 17. The data input / output circuit 19 outputs the data read from the memory cell array 11 to the outside, takes in the data input from the outside, and passes it to the sense amplifier 15.

  The address comparison circuit 20 stores a defective address (address information corresponding to a defective line) using a nonvolatile storage element (nonvolatile memory) such as EPROM or EEPROM, or a fuse (such as an antifuse or a laser fuse). The defective address and the address input (accessed) from the outside are compared, and if they match, the spare memory row (redundant line) 11a or the memory column (redundant line) 11b in the memory cell array 11 is selected instead of the defective line. To be. By this processing, functionally defective lines are replaced with redundant lines.

  A plurality of defective addresses (two in the example shown in FIG. 2) can be set for each memory bank BANK0 to BANK3 of the memory cell array 11 according to the number of spare memory rows 11a or spare memory columns 11b. Configured as follows.

  Control signals input from the outside to the command decoder 16 include a chip select signal / CS for selecting a chip, a row address strobe signal / RAS, a write enable signal / WE for instructing a data write operation, and the like. is there. Among these signals, those having “/” in front of the sign mean that the low level is an effective level.

  The command decoder 16 decodes these control signals / CS, / RAS, / CAS, / WE and a part of the address signal to interpret the input command. Further, the commands in the SDRAM shown in FIG. 2 include a READ command for instructing reading, a WRITE command for instructing writing, and an MRS command instructing setting of an operation mode in the mode register 17.

  The address comparison circuit 20 is provided with a first defective address setting and comparison circuit (NVRAM) 20A and a second defective address setting and comparison circuit (FUSE) 20B. The first defective address setting & comparing circuit 20A has an EPROM or EEPROM (NVRAM) cell for setting defective address information, and compares the set address with the input address to determine whether or not they match. The second defective address setting & comparing circuit 20B has a fuse for setting defective address information.

  For the first defective address setting & comparison circuit (NVRAM) 20A, there is a method of using a fuse such as an antifuse in place of EPROM or EEPROM.

  The defective address detected before enclosing the package is set in the second defective address setting & comparison circuit (FUSE) 20B. The defective address detected after the package is enclosed is set in the first defective address setting & comparison circuit (NVRAM) 20A. The control circuit 18 generates a switching control signal for selecting the spare memory row 11a or the spare memory column 11b when they match as a result of comparing the set defective address with the input address, and supplies it to the address decoder 13 or 14. A circuit is provided.

  Setting of a defective address by a fuse is performed by cutting with an antifuse (or a laser fuse or the like). Setting of the defective address in the EPROM or EEPROM is performed by inputting the data fetched by the address buffer 12 in the test mode to the first defective address setting & comparing circuit 20A as write data of the EPROM or EEPROM cell. . Thereby, even after the package is sealed, the defective bit can be relieved.

  Further, the step of detecting a defective address is performed by a method using a test pattern by a test apparatus 200 as shown in FIG. 3, for example. That is, the test apparatus 200 inputs the address and data of the memory cell array 11 to the memory (chip) 201, writes the predetermined data to the predetermined address of the memory cell array 11, and then reads the data read from the memory cell array 11. The expected value data is compared, and the comparison result is written in an FBM (Fail Bit Memory) of the test apparatus 200 (relief process 1).

  Next, the test apparatus 200 performs repair determination with software based on the data written in the FBM, and detects a defective address (repair process 2). When a defective address is detected by the test apparatus 200, a test mode for programming the defective address in the relief circuit is executed (relief process 3).

  The test apparatus 200 inputs a defective address to the address buffer 12 in the memory 201, inputs a control signal to the command decoder 16, enters a test mode, and the control circuit 18 sets the defective address to the first defective address setting & comparison circuit ( NVRAM) 20A. By the above procedure, the defective address is programmed in the non-volatile memory, and the repair process is completed.

  The circuit shown in FIG. 4 is a diagram showing a configuration example obtained by improving the circuit shown in FIG. In the configuration shown in FIG. 2, the defective address information obtained by the test apparatus is programmed to a nonvolatile memory (EEPROM or the like) in the semiconductor integrated circuit device using the test mode, and the test device and the chip (semiconductor integrated circuit) This is a solution to the problem that the transfer of information between the devices has become a bottleneck and has increased the test time.

  For this purpose, a nonvolatile memory cell array (NVRAM) 105 into which a defective address of a memory cell in the memory cell array 11 is written, and a data comparison & relief determination circuit 110 are provided. Since the other configuration is the same as that of the circuit shown in FIG. 2, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The data comparison & relief determination circuit 110 compares read data read from the memory cell of the memory cell array 11 with expected value data to be read from the memory cell, and generates a mismatch signal (err) indicating the result of the comparison. A data comparison circuit for output and a repair determination circuit for detecting a defective address based on the mismatch signal (err) are provided. The data comparison & relief determination circuit 110 detects a defective address inside the chip, and continuously programs the detected defective address into the nonvolatile memory 105 (without requiring access from the test apparatus). Circuit. Further, since the expected value is generated in the chip in the test mode state of the parallel test and on-chip compare, the expected value is not output from the test apparatus 200, and the memory cell corresponding to the input address in the chip. The data read from is compared with the expected value at any time.

  As for the nonvolatile memory (NVRAM) 105, there is a method of using a fuse such as an antifuse in place of the EPROM or the EEPROM.

  As described above, in a conventional semiconductor integrated circuit device, a parallel test or the like is performed, and when a defective memory cell exists, the address of the defective memory cell is programmed into a fuse or a non-volatile memory. Have bailout.

However, the conventional method has the following problems.
The first problem is that the designed relief circuit cannot be evaluated unless there is a defective cell in the actual product.
The second problem is that a sample relieved with an antifuse or the like cannot be used for failure analysis. The cause of this problem is that the defective sample becomes non-defective when repair is performed with an antifuse or the like.
A third problem is that when a relief test is actually performed using a sample for evaluation, a sufficient number of defective chips used in the test may not be secured.

As the above-described circuit for repairing defective bits of memory cells (such as antifuses) is widely used, the demand for incorporating a dedicated mode (test mode) is increasing in order to efficiently implement circuit evaluation and repair program debugging using actual products. is there.
JP 2002-25288 A JP 2003-257194 A

  The repair circuit represented by the above-described conventional semiconductor integrated circuit device does not repair a defective cell unless an actual product is tested by a parallel test or the like and determined to be defective. Therefore, as long as there are no defective cells in the chip, it is impossible to debug whether the designed relief circuit operates normally or whether the tester program for relieving defective cells in the post-assembly process operates normally. There was a problem.

  In addition, when a relief test is actually performed using a sample for evaluation, a sufficient number of defective chips used in the test may not be ensured.

  The present invention has been made to solve such a problem, and an object of the present invention is to evaluate a circuit of a relief circuit in a semiconductor integrated circuit device such as a DRAM without a product having a defective memory cell. In addition, it is possible to improve the efficiency of debugging of a program for evaluating a repair circuit and repairing a defective address, and to ensure a sufficient number of defective chips used in a test.

The present invention has been made to solve the above problems, and a semiconductor integrated circuit device according to the present invention has a memory cell array for storing data in a memory cell, and the address of a defective memory cell in the memory cell array is defective. A semiconductor integrated circuit device having a relief circuit for storing and relieving as an address, which is output as read data of the memory cell when data stored in a memory cell at a predetermined address in the memory array is read out A test mode is provided in which data is manipulated so that it becomes defective data contrary to preset expected value data, thereby converting the address of the memory cell into a defective address.
In the semiconductor integrated circuit device of the present invention having the above-described configuration, a predetermined address selected in advance only when the test mode is enabled (activated) in the parallel test of memory cells (parallel test of a plurality of memory cells). The output data of the memory cell is forced to become defective data (data contrary to expected data).
As a result, in a semiconductor integrated circuit device such as a DRAM, it is possible to perform circuit evaluation of a relief circuit even if there is no product in which a defective memory cell exists. The debugging efficiency can be improved, and a sufficient number of defective chips can be secured for testing.

The semiconductor integrated circuit device according to the present invention is characterized in that the relief circuit is composed of one or both of a fuse for storing the defective address and a nonvolatile memory.
As a result, it is possible to improve the efficiency of debugging a program for evaluating a repair circuit using a fuse or a nonvolatile memory and repairing a defective address.

In the semiconductor integrated circuit device of the present invention, in the test mode, an output signal of the data amplifier is used as a signal of the defective data for a data amplifier that reads data of the memory cell to be converted to the defective address. It is characterized by incorporating a pseudo error signal generation circuit that outputs a replacement.
In the semiconductor integrated circuit device of the present invention having the above-described configuration, the output signal of the data amplifier is forcibly transmitted to the data amplifier that reads data of the memory cell to be determined as defective in the test mode. A pseudo error signal generation circuit that incorporates a signal (data contrary to expected data) is incorporated.
As a result, the data output from the memory cell to be converted into a defective address can be replaced with defective data. Therefore, in a semiconductor integrated circuit device such as a DRAM, it is possible to perform circuit evaluation of a relief circuit even if there is no product in which a defective memory cell exists, and a program for evaluating a relief circuit and repairing a defective address Debugging efficiency can be improved.

In the semiconductor integrated circuit device according to the present invention, the data amplifier includes an enable signal input terminal for activating or deactivating the data amplifier, and the pseudo error signal generation circuit is a signal for activating the test mode. When a test mode enable signal is input, a signal that deactivates the data amplifier is output to the enable signal input terminal of the data amplifier, and a signal that becomes defective data is output instead of the data amplifier And when the test mode enable signal is not input and the data amplifier enable signal, which is a signal for activating the data amplifier, is input, the data to the enable signal input terminal of the data amplifier Outputs a signal that activates the amplifier, and records data from the data amplifier to the memory cell. Characterized in that it comprises a means for outputting the data, the.
In the semiconductor integrated circuit device of the present invention having the above-described configuration, the pseudo error signal generation circuit deactivates the data amplifier when the test mode enable signal is activated, and the signal becomes defective data instead of the data amplifier. ("H" or "L" signal contrary to expected data) is output. When the data amplifier enable signal is input, the data amplifier is activated and the data of the memory cell read by the data amplifier is output.
Thereby, by selecting the test mode enable signal or the data amplifier enable signal, the data amplifier outputs a defective data signal (“H” or “L” signal contrary to expected data), or The operation of outputting the memory cell data can be easily performed.

In the semiconductor integrated circuit device of the present invention, as a first effect, the circuit evaluation of the relief circuit in the semiconductor integrated circuit device can be performed without a product having a defective cell.
As a second effect, since the conventional relief circuit replaces the defective cell, if the relief is performed on the chip in which the defective cell exists, the defective cell itself cannot be evaluated on the chip. Since any product can be replaced if it is a product equipped with the pseudo error signal generation circuit of the present invention, a sample used for evaluation of a relief circuit and program debugging can be selected.
In addition, as a third effect, when a relief test is actually performed using a sample for evaluation, a sufficient number of defective chips used in the test can be secured.

[Overview]
In the semiconductor integrated circuit device (DRAM or the like) of the present invention, the circuit according to the present invention (pseudo error) is used only when the test mode is enabled (ENABLE) in the parallel test of memory cells (parallel test of a plurality of memory cells). The memory cell at the address incorporating the signal generation circuit) is forced to be defective.

  In a conventional semiconductor integrated circuit device, a defective address of a defective cell is set in a relief circuit using a fuse (such as an antifuse or a laser fuse) or a nonvolatile memory (such as an EPROM or an EEPROM). Although it is possible to relieve a defective address (defective cell) in a process, by using the present invention, evaluation of a relieving circuit using a fuse or a nonvolatile memory and program debugging for relieving a defective address Can increase the efficiency.

[Description of Configuration of the Present Invention]
Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a pseudo error signal generation circuit added to a data amplifier in the semiconductor integrated circuit device according to the first embodiment of the present invention.
In a semiconductor integrated circuit (DRAM or the like) represented by the above-described conventional technology (see Patent Document 1 and Patent Document 2), the data amplifier 1 in the sense amplifier 15 corresponding to a memory cell at an arbitrary address to be made defective is used. By mounting the pseudo error signal generation circuit 2 shown in FIG. 1, a memory cell at a predetermined address is forcibly determined to be defective during a parallel test or the like.

  Addresses determined to be defective in the parallel test are relieved by programming the defective addresses in a relief circuit (fuse or nonvolatile memory) in the same manner as in the above-described conventional semiconductor integrated circuit. Therefore, it becomes possible to confirm that the designed relief circuit is operating normally by passing a sample that has failed in the test before relief after passing the relief.

[Description of circuit operation]
The circuit shown in FIG. 1 has a configuration in which a pseudo error signal generation circuit 2 (a portion surrounded by a dotted line) is incorporated in a data amplifier 1, and the data amplifier in the conventional sense amplifier 15 shown in FIGS. 1 shows a circuit configuration in which a pseudo error signal generation circuit 2 is added. This portion of the pseudo error signal generation circuit 2 is incorporated in the data amplifier 1 corresponding to the address of the memory cell that is always failed when using the test mode. The data amplifier 1 is a circuit that amplifies a data signal read from the memory cell onto the common data line.

  In the circuit shown in FIG. 1, when the test mode enable signal becomes “H (High)” and is activated, the inverter element 3 causes the gate of the P-channel transistor (P-CH_Tr) 4 to become “L (Low)”. The P-channel transistor 4 is turned on, and the output of the data amplifier 1 outputs “H” even if the actual output data is “L”.

  Therefore, when the address bit (memory cell to be made defective) in which the pseudo error signal generation circuit 2 is charged is selected when the test mode is entered, the cell data is always “H” regardless of “H / L”. When the cell data “L” is output and has an expected value (preliminary expected data), the address is always defective.

  In the circuit shown in FIG. 2, when the pseudo error signal generation circuit 2 is incorporated in the data amplifier 1, the expected value data is held in the test apparatus 200 (see FIG. 3). The read data output from the amplifier 1 is compared with the expected data to determine a defective address.

  In addition, in the circuit shown in FIG. 4, when the pseudo error signal generation circuit 2 is incorporated in the data amplifier 1, the expected value is generated in the chip in the parallel test and on-chip compare test mode. An expected value is not output from the device 200. In the chip, the data read from the memory cell corresponding to the input address is compared with the expected value as needed.

  Returning to FIG. 1, the pass gate (TG1) is composed of a P-channel transistor 5A and an N-channel transistor 5B, and the pass gate (TG2) is composed of an N-channel transistor 6A and a P-channel transistor 6B.

  The circuit composed of the pass gate (TG1), the pass gate (TG2), and the inverter element 7 alternately selects the test mode enable signal and the data amplifier enable signal to enable the data amplifier 1 enable signal. It is configured to output to the terminal (EN).

  When the test mode enable signal terminal becomes “H”, the pass gate (TG2) is selected, the enable signal terminal (EN) of the data amplifier 1 becomes “L”, the output of the data amplifier 1 stops, and the P channel transistor 4 is output to the data output line (RWBS).

  When the test mode enable signal is “L”, the pass gate (TG2) is selected, and the data amplifier enable signal is applied to the enable signal terminal (EN). By setting the data amplifier enable signal to “H”, the data amplifier 1 is driven to output cell data read from the memory cell to the data output line (RWBS).

  Thus, the function of the pass gate (TG1) and the pass gate (TG2) prevents the data amplifier 1 from being activated at the time of test mode entry so that the output of the data amplifier 1 and the output from the P-channel transistor 4 interfere with each other. Don't be afraid.

  With the above configuration, for example, when the pseudo error signal generation circuit 2 is incorporated in the data amplifier 1 corresponding to the memory cells of two addresses, when the actual product is tested using the test mode in the parallel test, the two addresses are It is detected as a 2-bit defect.

  After that, the 2 bits are relieved by a relieving circuit similar to the above-described conventional semiconductor integrated circuit device.

  For example, in the circuit shown in FIG. 2, the defective address is transferred to the first defective address setting & comparing circuit (NVRAM) 20A or the second defective address setting & comparing circuit (FUSE) 20B provided in the address comparing circuit 20. Set. The first defective address setting & comparing circuit 20A has an EPROM or EEPROM (NVRAM) cell for setting defective address information, and compares the set address with the input address to determine whether or not they match. The second defective address setting & comparing circuit 20B has a fuse for setting defective address information.

  When an address is input from the outside, the address comparison circuit 20 receives the input address and the first defective address setting & comparison circuit (NVRAM) 20A or the second defective address setting & comparison circuit (FUSE). The address set to 20B is compared, and if they match, the spare memory row (redundant line) 11a or memory column (redundant line) 11b in the memory cell array 11 is selected instead of the defective line.

  In the semiconductor integrated circuit device of the present invention described above, when the pseudo error signal generation circuit 2 shown in FIG. 1 is in the test mode enable (ENABLE), the “H” is used regardless of the cell data stored in the memory cell. ”And forcibly fail when cell data“ L ”is expected, but this may be forced to output“ L ”when cell data“ H ”is expected. Good.

  In the semiconductor integrated circuit device of the present invention described above, the pseudo error signal generation circuit 2 is incorporated in the data amplifier 1 in the sense amplifier section, so that a memory cell parallel test (a parallel test of a plurality of memory cells) is performed. Only when the test mode is enabled (ENABLE), the memory cell at the address in which the circuit of the present invention is loaded is forced to be defective. Then, the defective address (defective cell) is relieved by an antifuse (or laser fuse, EPROM, EEPROM, or the like).

Thereby, as a first effect, circuit evaluation of the relief circuit in the semiconductor integrated circuit device can be performed without a product having a defective cell.
As a second effect, since the repair circuit replaces the defective cell, if the defective address is repaired on the chip in which the defective cell exists, the defective cell itself cannot be evaluated on the chip. As long as the product is equipped with the circuit of the present invention, it can be replaced with any sample, so that the sample used for evaluation of the relief circuit and program debugging can be selected.

  Although the embodiments of the present invention have been described above, the semiconductor integrated circuit device of the present invention and the pseudo error signal generation circuit in the semiconductor integrated circuit device are not limited to the above-described illustrated examples. Of course, various changes can be made without departing from the scope of the present invention.

  In the present invention, circuit evaluation of a relief circuit in a semiconductor integrated circuit device can be performed without a product having a defective cell. Therefore, the present invention provides a semiconductor integrated circuit for relieving a defective memory cell in a post-assembly process. This is useful for circuit evaluation of the above and debugging of a program for relieving a defective memory cell in a post-assembly process.

It is a figure which shows the structure of the pseudo | simulation error signal generation circuit in the semiconductor integrated circuit device concerning embodiment of this invention. It is a figure which shows the circuit structure of the semiconductor integrated circuit device of a prior art. It is a figure for demonstrating the test method of a semiconductor integrated circuit device. FIG. 3 is a diagram showing a configuration example in which the semiconductor integrated circuit device shown in FIG. 2 is improved.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Data amplifier, 2 ... Pseudo error signal generation circuit, 3, 7 ... Inverter element 4, 5A, 6B ... P channel transistor (PMOS), 5B, 6A ... N channel transistor (NMOS), 11 ... memory cell array, 11a ... spare memory row, 11b ... spare memory column, 12 ... address buffer, 13 ... row address decoder, 14 ... column address decoder, DESCRIPTION OF SYMBOLS 15 ... Sense amplifier, 16 ... Command decoder, 17 ... Mode register, 18 ... Control circuit, 19 ... Data input / output circuit, 20 ... Address comparison circuit, 20A ... No. 1 defective address setting & comparison circuit (NVRAM), 20B... 2nd defective address setting & comparison circuit (FUSE), 21. · Nonvolatile memory (NVRAM), 110 ... data comparison and repair decision circuit, TG1, TG2, ... pass gates, 200 ... test apparatus, 201 ... memory

Claims (4)

A semiconductor integrated circuit device having a memory cell array for storing data in a memory cell, and having a relief circuit for storing and relieving an address of a defective memory cell in the memory cell array as a defective address,
When reading data stored in a memory cell at a predetermined address in the memory array, an operation is performed so that data output as read data of the memory cell is defective data contrary to preset expected data. A semiconductor integrated circuit device comprising: a test mode for converting the address of the memory cell into a defective address. 2. The semiconductor integrated circuit device according to claim 1, wherein the relief circuit includes one or both of a fuse for storing the defective address and a nonvolatile memory. During the test mode,
A pseudo error signal generation circuit is provided for a data amplifier that reads out data of a memory cell to be converted into a defective address, and outputs the data amplifier by replacing an output signal of the data amplifier with the signal of the defective data. The semiconductor integrated circuit device according to claim 1 or 2. The data amplifier includes an enable signal input terminal for activating or deactivating the data amplifier,
The pseudo error signal generation circuit includes:
When a test mode enable signal, which is a signal for activating the test mode, is input, a signal for deactivating the data amplifier is output to the enable signal input terminal of the data amplifier, and the data amplifier is also output. Instead, means for outputting a signal that becomes defective data,
When the test mode enable signal is not input and the data amplifier enable signal, which is a signal for activating the data amplifier, is input, the data amplifier is activated with respect to the enable signal input terminal of the data amplifier And a means for outputting data stored in a memory cell from the data amplifier,
The semiconductor integrated circuit device according to claim 3, further comprising:

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