JP2008205180A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method, wherein a capacitance element of a large capacitance is constituted in a small area by a conventional production line arrangement without complicating a production process. <P>SOLUTION: A plurality of local select oxide films 4 are formed in a region surrounded by a select oxide film 2 for element isolation serving as an element separation region, and also there is formed the capacitance element configured by sequentially laminating a lower electrode 5, a dielectric film 6 and an upper electrode 7 which are curved along a rugged shape of the local select oxide films 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device characterized by a configuration for miniaturizing a capacitor element integrated in a semiconductor integrated circuit device and a method for manufacturing the same.

In a semiconductor integrated circuit, a capacitive element using SiN as a dielectric film is larger than other elements in order to obtain a required capacitance, and occupies a large proportion of the area in the chip.
Such a SiN capacitance pattern is formed on a flat element isolation field oxide film, and thus has a planar capacitance element shape, so that the pattern area is large (see, for example, Patent Document 1). .

Here, with reference to FIGS. 10 and 11, a conventional process of forming a SiN capacitor will be described. See FIG.
First, after sequentially forming an initial oxide film 72 and a SiN film 73 on a p-type silicon substrate 71, for example, an oxidation resistant mask 74 having an element isolation portion having a width of 100 μm is formed.
Note that the region where the oxidation-resistant mask 74 is formed becomes a later element formation region.

  Next, thermal oxidation is performed in an oxidizing atmosphere using the oxidation-resistant mask 74 as a mask, thereby forming an element isolation field oxide film 75 with an opening having a thickness of 600 nm, for example.

Next, after removing the oxidation-resistant mask 74 by etching, an n-type polycrystalline silicon film is deposited on the entire surface, and then etched into a predetermined shape to form the lower electrode 76 of the capacitor.
Next, after a SiN film is deposited on the entire surface, the capacitor insulating film 77 is formed by etching into a predetermined shape.

See FIG.
Next, after depositing an interlayer insulating film 78 on the entire surface, etching is performed to form a capacitor window 79 exposing most of the capacitor insulating film 77.

  Next, after again depositing an n-type polycrystalline silicon film on the entire surface, the upper electrode 80 of the capacitor is formed by etching into a predetermined shape.

Next, after forming a contact hole 81 for the lower electrode 76, although not shown in the figure, by forming contact vias or wirings for the lower electrode 76 and the upper electrode 80 according to the required circuit configuration, the basics of the capacitor element are formed. Complete manufacturing process.
JP 05-090492 A

  In the manufacturing process of the semiconductor integrated circuit device, the manufacturing efficiency is higher when the number of chips that can be manufactured in one wafer is higher. However, in order to increase the number of chips per wafer, it is effective to reduce the chip size. There is a tendency to reduce the chip size.

  In such a trend, in order to reduce the chip size of the semiconductor integrated circuit device, it is necessary to reduce the area of each device in the chip, but in the case of a capacitive element having a planar shape In order to secure the necessary capacity, a certain area is required, and the area of such a capacitive element is an obstacle to the reduction in size of the chip.

In order to obtain a large capacity with a small area, a high dielectric constant film such as an Al ₂ O ₃ film, a Ta ₂ O ₅ film, or an HfO ₂ film may be used instead of the SiN film. Unlike the SiN film normally used in the manufacturing process of the apparatus, it is necessary to prepare a new film forming apparatus and a new etching apparatus associated therewith, and there is a problem that it does not necessarily lead to high manufacturing efficiency. is there.

  Alternatively, it is possible to obtain a large capacity with a small area by adopting a three-dimensional structure such as a fin structure such as a DRAM memory capacitor. However, in order to do so, the manufacturing process becomes complicated, and in this case also, it is not always necessary. There is a problem that it does not lead to high production efficiency.

  Accordingly, an object of the present invention is to configure a large-capacity capacitive element with a small area by a conventional production line configuration without complicating the production process.

FIG. 1 is a block diagram showing the principle of the present invention, and means for solving the problems in the present invention will be described with reference to FIG.
Reference numeral 8 in the figure denotes an interlayer insulating film.
Refer to FIG. 1. In order to solve the above-described problem, the present invention includes a plurality of local selective oxide films 4 in an element isolation region and a region surrounded by an element isolation selective oxide film 2 in a semiconductor device. In addition, a capacitive element having a structure in which a lower electrode 5, a dielectric film 6, and an upper electrode 7 that are curved along the uneven shape of the local selective oxide film 4 are sequentially stacked is provided.

  As described above, by using the uneven shape of the local selective oxide film 4, the effective area of the capacitive element can be increased without complicating the manufacturing process and using the conventional manufacturing line configuration. It is easy to reduce the size of the semiconductor device, whereby the chip size of the semiconductor device can be reduced.

  In this case, it is possible to provide a recess where the region between the adjacent local selective oxide films 4 is lower than the main surface of the semiconductor substrate 1 so that the curve of the capacitor element also follows the recess. The effective area can be further increased.

  Alternatively, an oxidation-resistant mask may be left in a region between the adjacent local selective oxide films 4, and thereby insulation for preventing a short circuit between the semiconductor substrate 1 and the lower electrode 5 constituting the capacitor element. A step of forming a film is not necessary.

  In this case, it may be configured such that at least the surface of the region surrounded by the element isolation selective oxide film 2 is covered with the vapor phase growth insulating film, whereby the uneven shape is further curved. Capacitance elements can be further reduced in size.

  In this case, the local selective oxide film 4 is desirably arranged in a two-dimensional matrix, whereby the effective surface area in the same plane area can be further increased.

Note that the dielectric film 6 constituting the capacitive element in this case is typically a silicon nitride film (Si ₃ N ₄ film), and the capacitive element can be constituted by a conventional production line configuration.

  Further, according to the present invention, in the method of manufacturing a semiconductor device, when the element isolation selective oxide film 2 is formed by selectively oxidizing the semiconductor substrate 1 using an oxidation resistant mask, A step of simultaneously forming a local selective oxide film 4 by providing a plurality of oxidation-resistant mask patterns 3 in a region surrounded by the selective isolation oxide film 2, and a selective oxide film for element isolation that is an element isolation region A step of forming a capacitive element by sequentially laminating a lower electrode 5, a dielectric film 6, and an upper electrode 7 that are curved along the uneven shape of the local selective oxide film 4 in a region surrounded by 2. Features.

  In this way, by forming the local selective oxide film 4 for forming the uneven shape simultaneously with the element isolation selective oxide film 2, the effective area of the capacitive element can be increased without increasing the number of manufacturing steps. Can do.

  In this case, it is desirable to provide a step of forming a recess by etching a region between a plurality of adjacent local selective oxide films 4 before the step of forming the capacitor element. Since the oxide film 4 may be used as an etching mask, the effective surface area can be increased by omitting the manufacturing process of the etching mask.

  Further, in the step of forming the capacitive element, the capacitive element may be formed without removing the plurality of oxidation resistant mask patterns 3, thereby short-circuiting the semiconductor substrate 1 and the lower electrode 5 constituting the capacitive element. The step of forming an insulating film for preventing the above can be omitted.

  In addition, an insulating film may be formed by vapor phase epitaxy on the surface of at least the region surrounded by the element isolation selective oxide film 2 including the plurality of oxidation resistant mask patterns 3 before the step of forming the capacitor element. Good, thereby making it possible to further curve the concavo-convex shape with only a simple film formation process.

  According to the present invention, since the concavo-convex shape is formed in the field region using the selective oxidation process for forming the element isolation region, a novel material such as a ferroelectric film or a manufacturing apparatus is not required, Capacitance elements having a large capacity and a small occupation area can be configured by a conventional production line configuration.

  The present invention provides an element isolation region and a region surrounded by the element isolation selective oxide film when the element isolation selective oxide film is formed by selectively oxidizing a semiconductor substrate using an oxidation resistant mask. A plurality of oxidation-resistant mask patterns are provided to form a local selective oxide film at the same time, and the unevenness of the local selective oxide film is formed in an element isolation region and a region surrounded by the element isolation selective oxide film. A capacitive element is formed by sequentially laminating a lower electrode, a dielectric film, and an upper electrode that are curved along the line.

  At this time, before the step of forming the capacitor element, a recess may be formed by etching a region between a plurality of adjacent local selective oxide films, or a plurality of oxidation resistant mask patterns may be formed. The capacitor element may be formed without being removed, and further, an insulating film may be vapor-phase grown thereon.

Here, with reference to FIG. 2 thru | or FIG. 4, the formation process of the SiN capacitive element of Example 1 of this invention is demonstrated.
See Figure 2
First, after the initial oxide film 12 and the SiN film 13 are sequentially formed on the p-type silicon substrate 11, for example, frame-shaped openings 14 and 15 for forming element isolation portions having widths of 3.0 μm and 2.0 μm, respectively. Then, a lattice-shaped oxidation-resistant mask 17 is formed so that rectangular openings 16 each having a thickness of 1.0 μm are formed inside the frame-shaped openings 14 and 15 at a pitch of 2.0 μm, for example.

  Next, thermal oxidation is performed in an oxidizing atmosphere using the oxidation resistant mask 17 as a mask, thereby simultaneously forming a field oxide film 18 for element isolation having a thickness of, for example, 600 nm and a local selective oxide film 19 in the opening. To do.

  Next, after removing the oxidation-resistant mask 17 by etching, the exposed portion of the p-type silicon substrate 11 is etched using the field oxide film 18 and the local selective oxide film 19 as a mask, so that the depth from the main surface of the p-type silicon substrate is reduced. For example, the trench 20 of 600 nm is formed.

See Figure 3
Next, by performing thermal oxidation again in an oxidizing atmosphere, an oxide film 21 having a thickness of, for example, 100 nm is formed on the bottom surface and side surface of the trench 20, and a capacitor element to be formed later and the p-type silicon substrate 11 are formed. An insulating film is used to insulate.

  Next, after depositing an n-type polycrystalline silicon film having a thickness of, for example, 260 nm on the entire surface by using the CVD method, the lower electrode 22 of the capacitor element is formed by etching into a predetermined shape.

  Next, a SiN film having a thickness of, for example, 25 nm is deposited on the entire surface by plasma CVD, and then etched into a predetermined shape to form a capacitor insulating film 23.

See Figure 4
Next, a CVD window is used to deposit an SiO ₂ film having a thickness of, for example, 500 nm on the entire surface to form the interlayer insulating film 24, and then etching is performed to expose a large portion of the capacitor insulating film 23. 25 is formed.

  Next, an n-type polycrystalline silicon film having a thickness of, for example, 100 nm is deposited on the entire surface again using the CVD method, and then etched into a predetermined shape to form the upper electrode 26 of the capacitor element.

  Next, after forming a contact hole 27 for the lower electrode 22, although not shown in the drawings, contact vias or wirings for the lower electrode 22 and the upper electrode 26 are formed in accordance with the required circuit configuration, thereby forming the present invention. The basic manufacturing process of the SiN capacitor of Example 1 is completed.

  In the first embodiment of the present invention, a local selective oxide film 19 is formed in the capacitor element forming region to form a convex portion, and a trench is formed by etching and digging between adjacent local selective oxide films 19. Since 20 is formed, the effective surface area can be significantly increased compared to a plane, thereby reducing the occupied area when forming a SiN capacitor of the same capacity.

  For example, when the ratio of the flat portion, that is, the bottom surface of the trench 20 is 1/3, the convex portion formed of the sidewall of the trench 20 and the local selective oxide film 19 is hemispherical, and the ratio is evaluated as 2/3. The size of the SiN capacitor can be reduced by about 28%.

  In the first embodiment of the present invention, the local selective oxide film 19 is formed simultaneously with the field oxide film 18, and the local selective oxide film 19 and the field oxide film 18 are formed when the trench 20 is formed. Since the etching mask is used, the SiN capacitor element can be reduced in size without significantly increasing the number of steps.

Next, with reference to FIGS. 5 and 6, the process of forming the SiN capacitor according to the second embodiment of the present invention will be described.
See Figure 5
First, after the initial oxide film 12 and the SiN film 13 are sequentially formed on the p-type silicon substrate 11, for example, frame-shaped openings 14 and 15 for forming element isolation portions having widths of 3.0 μm and 2.0 μm, respectively. Then, the lattice-shaped oxidation resistant mask 32 is formed so that the rectangular openings 31 each having a thickness of 1.0 μm are formed in the frame-shaped openings 14 and 15 at a pitch of 1.0 μm, for example.

  Next, thermal oxidation is performed in an oxidizing atmosphere using the oxidation-resistant mask 17 as a mask to simultaneously form a field oxide film 18 for element isolation having a thickness of, for example, 600 nm and a local selective oxide film 33 in the opening. To do.

  Next, only the oxidation-resistant mask 32 formed in the element formation region is removed by etching, and then an n-type polycrystalline silicon film having a thickness of, for example, 260 nm is deposited on the entire surface by using the CVD method, and then formed into a predetermined shape. The lower electrode 34 of the capacitive element is formed by etching.

  Next, a SiN film having a thickness of, for example, 25 nm is deposited on the entire surface by plasma CVD, and then etched into a predetermined shape to form a capacitor insulating film 35.

See FIG.
Next, a CVD window is used to deposit an SiO ₂ film having a thickness of, for example, 500 nm on the entire surface to form the interlayer insulating film 36, and then etching is performed to expose the capacitor insulating film 35 most of the capacitor window. 37 is formed.

  Next, an n-type polycrystalline silicon film having a thickness of, for example, 100 nm is deposited on the entire surface by CVD, and then etched into a predetermined shape to form the upper electrode 38 of the capacitor element.

  Next, after forming a contact hole 39 for the lower electrode 34, although not shown in the drawings, contact vias or wirings for the lower electrode 34 and the upper electrode 38 are formed in accordance with a required circuit configuration, thereby forming the present invention. The basic manufacturing process of the SiN capacitor of Example 2 is completed.

  In the second embodiment of the present invention, the oxidation-resistant mask 32 used for forming the local selective oxide film 19 is left as it is to form an insulating film that separates the p-type silicon substrate 11 and the lower electrode 34. This eliminates the need for a new insulating film forming step as in the first embodiment.

  Incidentally, when the ratio of the flat portion, that is, the region between the local selective oxide films 19 is set to 1/3 and the ratio of the arc portion formed of the local selective oxide film 19 is evaluated as 2/3, the SiN capacitance is evaluated. The element size can be reduced by about 3%.

Next, with reference to FIGS. 7 to 9, the process of forming the SiN capacitor according to the third embodiment of the present invention will be described.
See FIG.
First, after the initial oxide film 12 and the SiN film 13 are sequentially formed on the p-type silicon substrate 11, for example, frame-shaped openings 14 and 15 for forming element isolation portions having widths of 3.0 μm and 2.0 μm, respectively. Then, the lattice-shaped oxidation resistant mask 32 is formed so that the rectangular openings 31 each having a thickness of 1.0 μm are formed in the frame-shaped openings 14 and 15 at a pitch of 1.0 μm, for example.

  Next, thermal oxidation is performed in an oxidizing atmosphere using the oxidation-resistant mask 17 as a mask to simultaneously form a field oxide film 18 for element isolation having a thickness of, for example, 600 nm and a local selective oxide film 33 in the opening. To do.

Next, after removing only the oxidation-resistant mask 32 formed in the element formation region by etching, a SiO ₂ film 41 having a thickness of, for example, 200 nm is deposited on the entire surface by CVD.

See FIG.
Next, after depositing an n-type polycrystalline silicon film having a thickness of, for example, 260 nm on the entire surface by using the CVD method, the lower electrode 42 of the capacitor element is formed by etching into a predetermined shape.

  Next, a SiN film having a thickness of, for example, 25 nm is deposited on the entire surface by plasma CVD, and then etched into a predetermined shape to form a capacitor insulating film 43.

Next, a CVD window is used to deposit an SiO ₂ film having a thickness of, for example, 500 nm on the entire surface to form the interlayer insulating film 44, and then etching is performed to expose the capacitor insulating film 43 for the most part. 45 is formed.

See FIG.
Next, an n-type polycrystalline silicon film having a thickness of, for example, 100 nm is deposited on the entire surface by CVD, and then etched into a predetermined shape to form the upper electrode 46 of the capacitor element.

  Next, after forming a contact hole 47 for the lower electrode 42, although not shown in the following, contact vias or wirings for the lower electrode 42 and the upper electrode 46 are formed in accordance with the required circuit configuration, thereby forming the present invention. The basic manufacturing process of the SiN capacitor of Example 3 is completed.

In the third embodiment of the present invention, since the SiO ₂ film 41 is deposited on the surface including the oxidation resistant mask 32 after the local selective oxide film 19 is formed, the uneven shape on the surface is further emphasized, The occupied area of the SiN capacitive element can be made smaller than in the second embodiment.

  For example, when the flat portion, that is, the ratio of the region between the local selective oxide films 19 is almost 0 and most of the area is an arc portion made of the local selective oxide film 19, the size of the SiN capacitor element is evaluated. The thickness can be reduced by about 4.5%.

The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations, conditions, and numerical values shown in the embodiments, and various modifications are possible. For example, in the above embodiments, Uses a SiN film as a capacitor dielectric film, but is not limited to a SiN film. Like a SiN film, a SiO ₂ film or a SiON film that can be formed without changing a conventional production line is used. It is good.

  In addition, the size and pitch of the local selective oxide film in each of the above-described embodiments is an example, and may be appropriately changed according to the required capacity or the allowable occupied area.

  In each of the above embodiments, the oxidation-resistant mask pattern is formed in a lattice pattern and the local selective oxide film is formed in a two-dimensional matrix. Conversely, the oxidation-resistant mask for forming the local selective oxide film is used. The pattern may be a two-dimensional matrix, and the local selective oxide film may be formed in a lattice shape.

  Furthermore, the oxidation-resistant mask pattern for forming the local selective oxide film may be formed in a line and sous (L & S) pattern, and the local selective oxide film may be formed in an L & S pattern.

Here, referring to FIG. 1 again, the detailed features of the present invention will be described again.
Again see Figure 1
(Supplementary Note 1) The element isolation region has a plurality of local selective oxide films 4 in a region surrounded by the element isolation selective oxide film 2 and is curved along the uneven shape of the local selective oxide film 4. A semiconductor device comprising a capacitive element having a structure in which a lower electrode, a dielectric film, and an upper electrode are sequentially stacked.
(Additional remark 2) The area | region between the said adjacent local selective oxide films 4 is a hollow lower than the main surface of the semiconductor substrate 1, The curve of the said capacitive element is a shape along the said hollow. The semiconductor device according to appendix 1.
(Supplementary note 3) The semiconductor device according to supplementary note 1, wherein an oxidation-resistant mask exists in a region between the adjacent local selective oxide films 4.
(Supplementary note 4) The semiconductor device according to supplementary note 3, wherein at least a surface of a region surrounded by the element isolation selective oxide film 2 is covered with a vapor phase growth insulating film.
(Supplementary note 5) The semiconductor device according to any one of supplementary notes 1 to 4, wherein the local selective oxide film 4 is arranged in a two-dimensional matrix.
(Supplementary note 6) The semiconductor device according to any one of supplementary notes 1 to 5, wherein the dielectric film 6 constituting the capacitive element is a silicon nitride film.
(Supplementary Note 7) When the element isolation selective oxide film 2 is formed by selectively oxidizing the semiconductor substrate 1 using an oxidation resistant mask, the element isolation region is surrounded by the element isolation selective oxide film 2. Providing a plurality of oxidation-resistant mask patterns 3 in the region, and simultaneously forming a local selective oxide film 4; and a region surrounded by the element isolation selective oxide film 2 in the element isolation region. Manufacturing of a semiconductor device comprising a step of forming a capacitive element by sequentially laminating a lower electrode 5, a dielectric film 6, and an upper electrode 7 that are curved along the uneven shape of the local selective oxide film 4. Method.
(Additional remark 8) Before the process of forming the said capacitive element, it has the process of forming the hollow by etching the area | region between the said several adjacent local selective oxide films 4, The additional remark 7 characterized by the above-mentioned. A method for manufacturing a semiconductor device.
(Supplementary note 9) The method of manufacturing a semiconductor device according to supplementary note 7, wherein in the step of forming the capacitive element, the capacitive element is formed without removing the plurality of oxidation-resistant mask patterns 3.
(Additional remark 10) Before the process of forming the said capacitive element, it has the process of forming an insulating film by the vapor phase growth method at least in the surface of the area | region enclosed by the selective oxide film 2 for element isolation. 10. A method for manufacturing a semiconductor device according to 9.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the formation process to the middle of the SiN capacitive element of Example 1 of this invention. It is explanatory drawing of the formation process to the middle after FIG. 2 of the SiN capacitive element of Example 1 of this invention. It is explanatory drawing of the formation process after FIG. 3 of the SiN capacitive element of Example 1 of this invention. It is explanatory drawing of the formation process to the middle of the SiN capacitive element of Example 2 of this invention. It is explanatory drawing of the formation process after FIG. 5 of the SiN capacitive element of Example 2 of this invention. It is explanatory drawing of the formation process to the middle of the SiN capacitive element of Example 3 of this invention. It is explanatory drawing of the formation process to the middle after FIG. 7 of the SiN capacitive element of Example 3 of this invention. It is explanatory drawing of the formation process after FIG. 8 of the SiN capacitive element of Example 3 of this invention. It is explanatory drawing of the formation process to the middle of the conventional SiN capacitive element. It is explanatory drawing of the formation process after FIG. 10 of the conventional SiN capacitive element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Selective oxide film 3 for element isolation Oxidation-resistant mask pattern 4 Local selective oxide film 5 Lower electrode 6 Dielectric film 7 Upper electrode 8 Interlayer insulating film 11 P-type silicon substrate 12 Initial oxide film 13 SiN film 14 Frame Shaped opening 15 frame shaped opening 16 rectangular shaped opening 17 oxidation resistant mask 18 field oxide 19 local selective oxide 20 trench 21 oxide 22 lower electrode 23 capacitor insulating film 24 interlayer insulating film 25 capacitor window 26 upper electrode 27 contact Hole 31 Rectangular opening 32 Antioxidation mask 33 Local selective oxide film 34 Lower electrode 35 Capacitor insulating film 36 Interlayer insulating film 37 Capacitor window 38 Upper electrode 39 Contact hole 41 SiO ₂ film 42 Lower electrode 43 Capacitor insulating film 44 Interlayer insulating film 45 Capacitor window 46 Upper electrode 47 Contact hole 71 p-type silicon substrate 72 initial oxide film 73 SiN film 74 oxidation resistant mask 75 field oxide film 76 lower electrode 77 capacitor insulating film 78 interlayer insulating film 79 capacitor window 80 upper electrode 81 contact hole

Claims (5)

A lower electrode that has a plurality of local selective oxide films in a region surrounded by an element isolation selective oxide film and that is curved along the uneven shape of the local selective oxide film, and a dielectric film And a capacitor element having a structure in which upper electrodes are sequentially stacked. 2. The region between the adjacent local selective oxide films is a depression lower than the main surface of the semiconductor substrate, and the curvature of the capacitive element has a shape along the depression. Semiconductor device. 2. The semiconductor device according to claim 1, wherein an oxidation resistant mask exists in a region between the adjacent local selective oxide films. 4. The semiconductor device according to claim 3, wherein at least a surface of a region surrounded by the element isolation selective oxide film is covered with a vapor phase growth insulating film. When forming a selective oxide film for element isolation by selectively oxidizing a semiconductor substrate using an oxidation-resistant mask, a plurality of acid resistant films are also formed in the element isolation region and the area surrounded by the selective oxide film for element isolation. Forming a local selective oxide film at the same time by providing an oxidizable mask pattern, and along the uneven shape of the local selective oxide film in the element isolation region and a region surrounded by the element isolation selective oxide film A method of manufacturing a semiconductor device, comprising forming a capacitor element by sequentially laminating a lower electrode, a dielectric film, and an upper electrode that are bent in a curved line.

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