JP2008204488A - Multi-processor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem such as a cost increase since an inexpensive cache memory cannot be used because a processing time is necessary for monitoring processing, and a processing speed is lowered due to being unable to be formed as a light back cash. <P>SOLUTION: A common bus terminal 11a of an CPU 11 is connected to a global common bus 15b, and a bus terminal of a local cache memory 12 is connected to a global uncommon bus 15a. The global common bus is connected to an external common memory 19b storing common information used by the CPU, and the global uncommon bus 15a is connected to an external uncommon memory 19a storing uncommon information used by the CPU. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multiprocessor device in which a plurality of processor units are connected to a global bus.

  FIG. 21 is a block diagram showing a conventional multiprocessor device. In the figure, reference numerals 1 and 1A denote processor units, and each processor has a CPU 5 and a cache memory 6 having a write-through function and a write monitoring function. The cache memory 6 of each processor 1, 1 A is connected to a common global bus 2, and this global bus 2 is connected to an external memory 4 via an interface 3. The problem here is the data cache, and the instruction cache is not a problem, and is not shown.

The following operation will be described.
The CPU 5 exchanges data necessary for processing with the external memory 4 via the global bus 2 and interface 3, but the global bus 2 and interface 3 are slow in processing operation, and this speed becomes a bottleneck. The CPU 5 did not achieve the original processing speed.

  In view of this, there has been considered a method for improving the speed by holding the contents of the external memory 4 frequently used by the CPU 5 near the CPU. The local cache memory 6 is a memory that is provided near the CPU 5 and records the contents of the external memory 4 frequently used by the CPU.

Hereinafter, the operation of the local cache memory 6 will be described.
1. Read by local cache memory.

  Now, when the CPU 5 reads the address 0013 in the external memory 4, the local cache memory 6 confirms whether it has the contents at the address 0013. If there is, the content of address 0013 is returned to the CPU 5. As a result, the CPU 5 can operate at high speed without using the slow global bus 2 and interface 3.

  If the content of the address 0013 is not in the local cache memory 6, the local cache memory 6 selects the content of the memory that the CPU 5 it owns will not use for the time being (the selection method is the same as that of the present invention). The description is omitted because it is not essential, and this is erased (which will be described later, erased from the cache after being written into the memory), and the address 0013 and its contents are transferred to an empty place. By doing so, when the CPU 5 reads the address 0013 after the second time, the local cache memory 6 has the contents of the address 0013, so that it can be read at high speed. This mechanism is called purge.

2. Write by local cache memory.
When the CPU 5 performs writing to the external memory 4, there are two methods. One is a method called a write-back method (Write Back), and the other is a method called a write-through method (Write Through).

  First, the write-through method will be described. When the CPU 5 writes to the address 0013 of the external memory 4, it checks whether the local cache memory 6 has the contents of the address 0013 as in the case of reading. If the local cache memory 6 has the contents at the address 0013, the contents at the address 0013 in the local cache memory are rewritten, and the external memory 4 is also rewritten. If the local cache memory 6 does not have the contents of the address 0013, the local cache memory 6 erases other contents that the CPU 5 determines not to use, writes the contents of the address 0013 in an empty place, and stores them in the external memory 4. Also write. As a result, the global bus 2 and interface 3 which are slow in operation are used every time writing is performed.

  Next, the write back method will be described. This write back method is different in write timing from the write through method. That is, when writing, the local cache memory 6 is written, but not written to the external memory 4 and written when the local cache memory 6 purges the contents. As a result, only when purging, the slow global bus 2 and interface 3 are used, and the processing operation is faster than the write-through method.

3. Application of local cache memory in a multiprocessor device When the local cache memory is applied in a multiprocessor, it must have a “monitoring function” for processing by the write-through method and monitoring the written contents of other CPUs.

  First, the reason why the write-through method must be used (that is, the reason why the write-back method should not be used) is that when address 0013 is written by the write-back method, it is not written to the external memory 4 until the contents are purged. As a result, even if the other CPU reads address 0013, the other CPU can read only the old contents until purged.

  On the other hand, even if the write-through method is used, if another CPU has the contents of address 0013, the contents are not changed. Therefore, the local cache memory 6 monitors the writing of the other local cache memory, and when there is a writing, invalidates this content when there is the same content as compared with the address information of the local cache memory that it has. Will have to.

  In a cache memory configuration in a multiprocessor device, various methods have been conceived so far in order to maintain the identity between each local cache memory or between the local cache memory and the shared memory. For example, in Japanese Patent Publication Nos. 22-22757 and 4-175946, a memory to be accessed is divided according to sharing / non-sharing of data, and writing of the shared data is monitored by the above method. Employs invalidation technology.

U.S. Pat. No. 4,939,641 introduces a method of placing shared / non-shared information in a cache memory and reading / writing the cache using the write-back method if non-shared and the write-through method if shared. Collectively, there are numerous configurations of “with write monitoring” multiprocessors and cache memories, and some have “with monitoring function” as a prerequisite.
JP-B-2-22757 Japanese Examined Patent Publication No. 4-175946 U.S. Pat. No. 4,939,641

  Since the conventional multiprocessor device is configured as described above, it has the following problems.

The first is the time for the monitoring process.
If the monitoring process is performed each time writing is performed, the CPU cannot use the local cache memory during the process, resulting in a decrease in the operation speed of the CPU. For example, the number of readings of a certain process is 1,000,000 times, one clock (Clock) per reading, and the number of writings is 10,000 times per writing (because it is write-through, all writing is performed through the bus. Suppose that it takes 4 clocks and 2 clocks for the monitoring process for writing. When five CPUs perform this process at the same time, the writing of all the CPUs is 5 [CPU] × 10,000 [times] = 50,000 times, so that the monitoring process requires 100,000 clocks. Since the time excluding the monitoring process is 1,000,000 + 10,000 × 4 = 1,040,000 clocks, the processing time becomes nearly 10% longer for the monitoring process.

  In the same example, when the number of writes is 200, the processing time excluding the monitoring processing is 1,080,000 clocks, and the monitoring processing time is 200,000 clocks, which is about 20% longer. Further, when the number of writings is 200 and the CPU is 10, the monitoring processing time is 400,000 clocks, which is nearly 40% longer. Generally, as in the above example, the monitoring processing time is proportional to the number of CPUs and cache memories and the number of writes.

The second is a decrease in processing speed due to the fact that write-back cache cannot be used.
If the same processing as described above is performed and 50% of the write processing hits the cache memory, and the write processing time at that time is 1 clock, the processing time (excluding the monitoring time) is 1. , 000,000 × 1 clock + 10,000 × 5 × 4 clock = 1,0255,000 clocks, which is about 2% shorter. When the number of times of writing is doubled, it becomes 1,050,000 clocks in the same manner, and is similarly shortened by about 3%. The higher the hit rate, the shorter the write-back cache time. However, in the multiprocessor, as described above, in the write-back cache, other CPUs can read only the old contents, so that only the write-through cache with a slow speed can be used.

The third is the cost issue.
If a multiprocessor system with a write monitoring function is realized for one chip, this monitoring process increases the cache memory function. The addition of the monitoring function means that the normal cache memory that has been stored in the library cannot be used or needs to be revised. If revision is necessary, the design time is increased accordingly. Moreover, the chip layout area increases due to the addition of functions. As a result of increase in design time and layout area, both chip development cost and production cost increase.

  There is also a problem in procuring this monitoring process with chip external components. If it is just a write cache or a write-through only cache, it is inexpensive and available. This is because there is currently a great demand for single processors, and no single processor write monitoring is required.

  However, a cache memory with some “write monitoring” function as described above cannot be obtained at a low cost. This is because multiprocessors are currently used only in special fields and the market is small, resulting in high volume production and high parts.

  The present invention has been made to solve the above-described conventional problems, and does not require a cache memory write monitoring process, reduces the load on the bus and the load on the data cache, and realizes a high-speed data cache process. An object is to obtain a multiprocessor device.

  A multiprocessor device according to the present invention includes a CPU, a processor unit that is connected to the CPU and includes a first cache memory that exclusively stores information for each CPU, and a first processor that connects each of the plurality of processor units. A shared bus, a second cache memory connected to the plurality of processor units and storing information shared by the plurality of processor units, and a shared information connected to the first shared bus and shared by the plurality of processor units And an interface unit that outputs a control signal for accessing an external memory that stores data.

  The second cache memory of the multiprocessor device according to the present invention is a cache memory positioned lower than the first cache memory, and is connected to the first shared bus.

  According to the present invention, since the cache memory is provided in the shared data bus, there is an effect that the speed can be further increased.

An embodiment of the present invention will be described below.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing the configuration of a multiprocessor device according to Embodiment 1 of the present invention, in which a write-back cache is used and no shared cache is used.

  Here, “shared” is not a resource that is used / transferred / stored by each CPU, but a resource that simply transfers / stores “shared data”. Further, “non-shared” is not a resource that is used / transferred / stored only by a single CPU, but a resource that simply transfers / stores “non-shared data”. A resource used only by a single CPU is a “dedicated” resource, and a resource used by a plurality of CPUs is a “shared” resource.

  In FIG. 1, reference numeral 11 denotes an iCPU having a device capable of determining whether data to be read / written is shared data or non-shared data according to an instruction or an address to be accessed, and selecting a bus based on the result. This determination method will be described in the tenth and subsequent embodiments. The i-th CPU 11 has a (i, 1) shared bus terminal and an (i, 1) non-shared bus terminal, which determine the instruction or whether the CPU to be accessed is shared data or non-shared data. Is to be selected.

  Reference numeral 12 denotes an (i, 1) local cache memory that does not have a write monitoring function from another CPU. Here, the (i, 1) th local cache memory 12 performs only data transfer. As described above, this is because the program does not need to be rewritten in principle, and an instruction cache is not shown in this figure. The (i, 1) local cache memory 12 has a (i, 1) CPU side bus terminal 12a and an (i, 1) CPU external side bus terminal 12b. The (i, 1) CPU side bus terminal 12a is connected to the (i, 1) non-shared bus terminal 11b. The (i, 1) local cache memory 12 is a dedicated resource for the i-th CPU 11.

  13a is the (i, 1) local unshared bus connected to the (i, 1) external bus terminal 12b of the (i, 1) local cache memory 12, and 13b is the (i, 1) of the iCPU11. ) The (i, 1) local shared bus connected to the shared bus terminal 11a.

  Reference numeral 14 denotes an i-th processor unit including an i-th CPU 11, an (i, 1) local cache memory 12, an (i, 1) local unshared bus 13a, and an (i, 1) local shared bus 13b.

  The i-th processor unit 14 has an (i, 1) unit unshared bus terminal 14a and an (i, 1) unit shared bus terminal 14b, each of which is connected to the (i, 1) local unshared bus 13a. (I, 1) Connected to the local shared bus 13b. Here, the total number of processor units is I. Reference numeral 14 </ b> A denotes an (i + 1) -th processor unit adjacent to the i-th processor unit 14 and has the same configuration as the i-th processor unit 14.

  A first global unshared bus 15 a is connected to the (i, 1) unit unshared bus terminal 14 a of the i-th processor unit 14. The first global unshared bus 15a is a bus for transferring non-shared data from each CPU to an external non-shared memory 19a. A bus arbiter device (not shown) that performs arbitration in response to an access request from each local unshared bus terminal 14a is provided. This resource is shared by each CPU (processor unit).

  A first global shared bus 15 b is connected to the (i, 1) unit shared bus terminal 14 b of the i-th processor unit 14. The first global shared bus is a bus for transferring shared data from each CPU to the external shared memory 19b. The first global shared bus 15b includes a bus arbiter device (not shown) that performs arbitration in response to an access request from each local shared bus terminal 14b. This resource is shared by each CPU (processor unit).

  Reference numeral 17a denotes a first non-shared interface from which an external non-shared memory 19a and the like are accessed. This resource is shared by each CPU (processor unit).

  Reference numeral 17b denotes a first shared interface from which an external shared memory 19b and the like are accessed. This resource is shared by each CPU (processor unit).

  The non-shared memory 19a is a memory for storing non-shared data. This non-shared memory 19a is not dedicated to each processor unit, but may be shared by each processor unit. It is assumed that the write area from each CPU to this (shared) non-shared memory 19a is divided by, for example, addresses. Specifically, for example, if the non-shared memory 19a is assigned to addresses 0000 to 7FFF, the first CPU assigns the area to be used to 0000 to 0FFF, the second CPU assigns the area to be used to 1000 to 1FFF, and so on. It is assumed that Accordingly, in this example, the area of the non-shared memory 19a becomes “dedicated” for the first CPU from 0000 to 0FFF.

  Reference numeral 19b denotes a shared memory. This shared memory is a memory for storing shared data. The areas on the address map of the shared memory and the non-shared memory should not overlap.

(Restriction of the outside world from the interface in the above configuration)
Here, the bus configuration ahead of the first non-shared interface 17a and the first shared interface 17b is not the essence of the present invention. Accordingly, a certain memory block may be readable only via the first non-shared interface 17a, and another memory block may be readable from either. However, the memory block in which the shared data is stored must be accessible via the first shared interface, and the non-shared data must be accessed via the first non-shared interface as well.

  Hereinafter, for the sake of explanation, a case where the shared memory 19b and the non-shared memory 19a are placed as illustrated will be described.

(Description of non-shared data work area)
The present invention closes the contents (work area contents) used only by the corresponding process in the local cache, and further writes the contents used in a plurality of processes only in one memory and does not enter each local cache. This is intended to increase the speed and cost by eliminating the write monitoring process. Here, a description will be given by taking as an example a program in which five CPUs obtain the average score of five subjects.

  The contents of the memory in the multiprocessor include contents that should be shared and contents that do not need to be shared. For example, it is assumed that there is a certain score database, and five CPUs calculate the average score of “English”, “Mathematics”, “Japanese”, “Science”, and “Society”.

  At this time, a memory for storing the total score of “English” and a memory for storing the number of samples are required, but these are not necessary for obtaining other average points such as “math”. A storage area that is not necessary for these other processes is generally called a work area. The contents of this work area are stored in the (i, 1) th local cache memory 12 because there is no need for other CPUs to know.

  This operation will be described. When the CPU goes to access the work area, the CPU judges this access as “unshared data”, selects the (i, 1) CPU unshared bus terminal, and executes the access. The (i, 1) th local cache memory 12 searches for the contents of the corresponding address in accordance with the access information from the CPU, and returns the contents to the CPU if there is. If there is no corresponding access content, the cache memory requests access to the non-shared memory 19a via the (i, 1) local non-shared bus 13a, the first global non-shared bus 15a, and the first non-shared interface 17a. To do.

  As a result of the arbitration, when the first global non-shared bus 15a is opened and the (i, 1) local cache memory 12 fetches the corresponding address of the non-shared memory 19a, the (i, 1) local cache memory 12 Capture a copy. At this time, since the non-shared area of the non-shared memory 19a is “dedicated” by each CPU, there is no writing from other CPUs and there is no influence on each CPU.

  From the second time onward, the i-th CPU 11 accesses only the (i, 1) -th local cache memory 12 while the contents of the address fetched by the (i, 1) -th local cache memory 12 are held. In addition, since the contents of the (i, 1) local cache memory 12 do not need to be known by other CPUs, even if the contents of the (i, 1) local cache memory 12 are rewritten, (I, 1) There is no need to monitor the local cache memory 12 for writing.

(Description of shared data and its operation)
On the other hand, it is assumed that the deviation value is taken from the total average score of each subject to know the difficulty level of each subject. At this time, the average score of each subject obtained is necessary to find the deviation value and should be shared. The contents required by other CPUs (other processes) after this are accessed from the (i, 1) local shared bus 13b to the shared memory 19b through the first global shared bus 15b and the first shared interface 17b, and the local cache It is not stored in the memory 12.

  This operation will be described. The i-th CPU 11 determines that the data is shared data, and thereby selects the (i, 1) -th CPU shared bus terminal 11a. From the (i, 1) local shared bus 13b connected thereto, the i-th CPU 11 requests access to the shared memory 19b via the first global shared bus 15b and the first shared interface 17b. Due to the arbitration, the first global shared bus 15b is opened, and the i-th CPU 11 takes out the corresponding address in the shared memory 19b.

  When this operation is writing, it will be described that the writing monitoring device is not necessary. When writing from the i-th CPU 11 is completed, the shared memory 19b stores the latest writing information. On the other hand, when another CPU goes to read data at the same address to the shared memory 19b immediately after that, the shared memory 19b surely has the latest contents, and the other CPUs can obtain the latest contents. In addition, since there is no local cache memory for fetching shared data, there is no need to perform write monitoring, which has been implicitly understood in parallel processing so far.

(Effect of not sharing and sharing into cache memory 1)
Since it is not necessary to know that the content of the work area is rewritten by another CPU every time it is rewritten, the (i, 1) local cache memory 12 does not need to be a write-through cache, and is a write-back cache. Good. That is, the contents of the work area are closed in the (i, 1) th local cache memory 12. Usually, the work area is accessed very often.

  The contents to be written in the (i, 1) local cache memory 12 are accessed via the (i, 1) local cache memory 12 even if the contents (constants, etc.) that do not need to be written from the beginning to the end of the process are accessed. Also good. This is because the contents are not changed and other processes are not affected.

(Effect 2 of sharing and non-sharing, and not sharing the cache memory)
It was found that by dividing the contents to be accessed by the contents to be shared and the contents not to be shared, the (i, 1) local cache memory 12 may be a write-back cache that does not require a monitoring function. Therefore, read 1,000,000 times, of which 5,000 are via the shared bus, 10,000 are written, 5,000 of these are via the shared bus, and read / write via the local cache uses a write-back cache Assuming that 1 clock takes 4 clocks for reading and writing via the shared bus, the time required for this processing is (995,000 + 5,000) × 1 + (5,000 + 5,000) × 4 = 1,004,000 clocks. Thus, it can be seen that it is about 10% faster than the time of 1,140,000 when the conventional monitoring function is required.

  Conventionally, only the write-through cache can be used. However, in the first embodiment, either the write-back cache or the write-through cache can be used as the local cache. It may be a write-through cache for design reasons).

(Effect 3 of sharing and non-sharing, and not sharing the cache memory)
As described above, the (i, 1) -th local cache memory 12 does not require special write monitoring for the multiprocessor. This means that a general-purpose cache memory can be used instead of an expensive multi-microprocessor dedicated cache memory. Costs can be reduced by using a cache memory that does not have this function.
Embodiment 2. FIG.
FIG. 2 is a block diagram showing a multiprocessor device according to the second embodiment of the present invention. In FIG. 2, the same parts as those in the first embodiment shown in FIG. A duplicate description will be omitted. In the second embodiment, the first global shared cache memory 16 is provided in the middle of the first global shared bus 15b inside the first shared interface 17b.

  In this configuration, even if the (i + 1) CPU (not shown) reads the contents of the same address immediately after the i-th CPU 11 has written to the first global shared-cache memory 16, the contents of the first global-shared cache memory 16 Since the content updated immediately before is taken in, the new content can be read. Further, by installing the first global shared cache memory 16, the processing can be further speeded up.

Therefore, when reading and writing shared data is performed in two clocks due to the presence of the first global shared cache memory 16, the processing time is (995,000 + 5,000) by comparing the time with the same processing as in the first embodiment. ) × 1 + (5,000 + 5,000) × 2 = 1,002,000 clocks, which is slightly faster than the first embodiment. However, this is only when there is little read / write of the shared data. Generally, when the read / write of the shared data is large, the second embodiment is faster.
Embodiment 3 FIG.
FIG. 3 is a block diagram showing a multiprocessor device according to the third embodiment of the present invention. In FIG. 3, the same parts as those in the first embodiment shown in FIG. A duplicate description will be omitted. In the third embodiment, the first global non-shared bus 15a and the first global shared bus 15b are connected to the shared / non-shared memory 39 via the shared interface 37. The shared / non-shared memory 39 is shared / non-shared. The shared areas do not overlap.

Next, the operation will be described.
When the i-th CPU 11 accesses non-shared data, first, an access request is made to the (i, 1) cache memory 12 from the (i, 1) CPU non-shared bus terminal. The (i, 1) cache memory 12 accesses itself, and when there is no content, the dedicated non-shared memory of the iCPU 11 of the shared / non-shared memory 39 via the first global non-shared bus 15a and the shared interface 37. Go to the shared area. The “dedicated” non-shared area of the i-th CPU 11 does not write from other CPUs, and the i-th CPU 11 itself cannot write to the areas of other CPUs. In addition, since the non-shared area dedicated to the i-th CPU 11 does not perform writing as a shared area, the write data is guaranteed 100% for the i-th CPU 11. Therefore, of course, write monitoring is not necessary.

  On the other hand, in the case of shared data access, the i-th CPU 11 starts access from the CPU shared bus terminal and accesses the shared area to which the shared / non-shared memory 39 is allocated via the first global shared bus 15b and the shared interface 37. To do. When shared data is written, the contents are immediately reflected in the reading of other CPUs, so that writing monitoring is not required.

  In this method, both shared data and non-shared data pass through the shared interface 37. However, in particular, when the hit rate to the (i, 1) th local cache memory 12 is high and there is little reading / writing of shared data, the bus usage rate is low, and this method is effective.

If you want to store a multi-microprocessor system on a single chip, you must design the area as small as possible. If the requested area must be satisfied and no two buses can run, the first global unshared bus 15a and the first global shared bus 15b are combined as shown in FIG. One global bus 35 can be used. Although the third embodiment shows the same effect as the second embodiment, the bus usage rate is higher in the third embodiment, so the processing is slightly slower.
Embodiment 4 FIG.
FIG. 5 is a block diagram showing a multiprocessor device according to a fourth embodiment of the present invention, with the same parts as those in the third embodiment shown in FIG. Are denoted by the same reference numerals and redundant description is omitted. In the fourth embodiment, the first global shared cache memory 16 is provided in the middle of the first global shared bus 15b inside the shared interface 37.

  Such a form is effective when the hit rate of the local cache memory 12 is high (the bus usage rate is low) and the shared data is frequently read and written. At this time, in order to reduce the area, such a configuration may be adopted. The fourth embodiment shows the same effect as the second embodiment, but the fourth embodiment is slightly slower because the bus utilization rate is higher.

Further, as shown in FIG. 6, the first global unshared bus 15a and the first global shared bus 15b may be combined into one first global bus 35. In this case, since the first global cache memory 16 provided in the middle of the first global bus 35 also captures non-shared data, it is preferable that the capacity be as large as possible. Since the fourth embodiment is also the same as the third embodiment in principle, no write monitoring is required.
Embodiment 5. FIG.
FIG. 7 is a block diagram showing a multiprocessor device according to a fifth embodiment of the present invention. In this fifth embodiment, a recursive processor is formed by a plurality of processor units 14, 14A,... Shown in the first embodiment. The units 54 and 54A are configured. 54a is a first (recursive) unit unshared bus terminal, which is equivalent to the (i, 1) unit unshared bus terminal 14a, and 54b is a first (recursive) unit shared bus terminal, i, 1) Equivalent to the unit shared bus terminal 14b.

  55a is a first (recursive) global unshared bus, which is equivalent to the first global bus 15a, and 55b is a first (recursive) global shared bus, which is equivalent to the first global shared bus 15b.

  57a is a first (recursive) non-shared interface, which is equivalent to the first non-shared interface 17a, and 57b is a first (recursive) shared interface, which is equivalent to the first shared interface 17b.

As can be seen from the figure, the structure of the processor unit 14 of the first embodiment and the recursive processor unit 54 are recursively the same. As a result, the recursive processor unit 54 is further set as one processor unit, so that double and triple recursion is possible. Further, although the recursive processor unit 54 is shown in the case of the first embodiment, it may be configured based on the second embodiment. In this way, by performing recursion, various configurations can be assembled according to the purpose.
Embodiment 6 FIG.
FIG. 8 is a block diagram showing a multiprocessor device according to Embodiment 6 of the present invention. The same parts as those in Embodiment 1 shown in FIG. Duplicate explanation is omitted. Further, in Embodiment 6, Embodiment 1 will be described, but since the same can be applied to Embodiments 2 to 4, description of these embodiments will be omitted.

  The i-th CPU 11 has two CPU non-shared bus terminals 11b and 11c. The conventional part is referred to as the (i, 1) CPU non-shared bus terminal 11b, and the additional part is referred to as the (i, 2) CPU non-shared bus terminal 11c. Reference numeral 62 denotes a (i, 2) local cache memory connected to the (i, 2) CPU non-shared bus terminal 11c, and its function is the same as that of the (i, 1) local cache memory 12. The (i, 2) local cache memory 62 has an (i, 2) CPU side bus terminal 62a and an (i, 2) bus side bus terminal 62b. The (i, 2) CPU-side bus terminal 62a is connected to the (i, 2) CPU non-shared bus terminal 11c added to the i-th CPU 11. Reference numeral 63 a denotes a (i, 2) local unshared bus, which is connected to the (i, 2) bus side bus terminal 62 b of the added (i, 2) local cache memory 62.

  The i-th processor unit 14 has an added (i, 2) unit unshared bus terminal 14c, and is connected to the (i, 2) local unshared bus 63a. 65a is an added second global non-shared bus, 67a is an added second non-shared interface, and 69a is a second non-shared memory connected to the second non-shared interface 67a.

  Although not shown, the first non-shared memory 19a and the second non-shared memory 69a may be accessible from the first non-shared interface 17a or the second non-shared interface 67a as a shared data storage memory. Also, other devices may be connected to each global interface.

Next, the operation will be described.
For example, when more than two addresses are read when the cache memory can store two pieces of address information, purging is likely to occur. When the purge occurs, the usage rate of the first global unshared bus 15a becomes high and becomes congested. Here, the congestion is that the i-th CPU 11 wants to use the first global unshared bus 15a, but the other CPU uses the first global unshared bus 15a. This means a state that must be waited (in this state, the CPU waits and the processing capability is reduced).

  When a large number of addresses for non-shared data are used and the capacity of the (i, 1) local cache memory 12 is small, purge occurs and the bus is congested. As described above, the bus load can be reduced by adding the second global unshared bus 65a.

  The i-th CPU 11 selects which of the conventional bus and the additional bus is used when accessing the non-shared data. The simplest method of this selection is a method of assigning addresses according to even / odd addresses. Assuming that the (i, 2) non-shared bus terminal is selected, the i-th CPU 11 accesses the second non-shared memory 69a through the (i, 2) local cache memory 62 and the second non-shared interface 67a.

  On the other hand, there is no path for other CPUs such as the (i + 1) th CPU (not shown) to go to the first unshared data storage memory 19a from the first global unshared bus 15a through the first unshared interface 17a. ing. As a result, other CPUs can use this path.

  In the sixth embodiment, there are timings of using the bus, but two CPUs can access the non-shared data memory. As a result, waiting time is reduced, bus congestion is reduced, and processing speed is improved. Here, the case where one global non-shared bus is added has been described. However, if the number of buses is increased in the same manner, the degree of congestion is further reduced. Such a configuration is better configured with one chip as a whole rather than with multiple chips. The reason is that there are at most about 300 entrances / exits (pins) of one chip in the current technology, and the number of buses cannot be increased infinitely.

  Here, it is generally meaningless to add more buses than the number of processor units (the number of CPUs). For example, even if 100 buses are prepared for 10 CPUs, since the number of buses used at one time is at most 10 (10), the remaining 90 buses are unused. In general, the optimal number of buses can be expressed as:

Number of global buses = CPU x (average number of non-shared data accesses within unit time x access time / unit time)
Embodiment 7 FIG.
Although not shown, the shared bus may be multibused by applying the sixth embodiment. In this case, the same effect as in the sixth embodiment can be expected.
Embodiment 8 FIG.
FIG. 9 is a block diagram showing a multiprocessor device according to an eighth embodiment of the present invention. The same parts as those in the first embodiment shown in FIG. A reference numeral is attached and a duplicate description is omitted.

  Reference numeral 11 denotes an i-th CPU. This i-th CPU 11 has a (i, 1) -th CPU external device bus terminal 11d. Reference numeral 73c denotes an (i, 1) local external device bus, which is connected to the (i, 1) CPU external device bus terminal 11d. Reference numeral 14 denotes an i-th processor unit, and a new (i, 1) unit external device bus terminal 14d is newly added and is internally connected to the (i, 1) local external device bus 73c. 75c is a first global external device bus. The first global external device bus 75 c is connected to the (i, 1) unit external device bus terminal 14 d of each i-th processor unit 14. 77c is a first external device interface, and 79C is an external device. This external device 79C takes a very long access time.

Description of Bus Stop In the eighth embodiment, bus stop due to access to the slow external device 79C can be avoided. Here, the bus stop will be described. It is assumed that in the circuit as in the first embodiment, there is a slow external device 19b outside the shared interface 17b, and the access time is 10,000 clocks. When the first CPU accesses the slow external device 19b through the first global shared bus 15b, the other CPUs cannot use the first global shared bus 15b until the access of the first CPU is completed.

  As a result, if another CPU uses the first global shared bus for access, the worst wait is 10,000 clocks until the first CPU completes access. Since no one can do anything until the access is completed, the bus is stopped. Assuming that there are 10 CPUs as the worst case, it is assumed that each CPU accesses the external device once during 1,000,000 clocks. The time for accessing the external device is 10,000 clocks × 1 [times] × 10 [CPU] = 100,000 clocks, and about 10% of time is the bus stop time. As a result, all CPUs are under a speed of about 10% at maximum. In the eighth embodiment, in order to avoid such a bus stop, a bus for an external device is added.

Next, the operation will be described.
The i-th CPU 11 determines from the address information to be accessed (or from the instruction) whether this address is assigned to the external device 79c. If it is determined that the address is assigned to the external device 79c, the i-th CPU 11 starts access from the (i, 1) CPU external device bus terminal 11d, and this is the (i , 1) The external device 79c is accessed through the unit external device bus terminal 14d, the first global external device bus 75c, and the first external device interface 77c. In this case, the first global shared bus 15b and the first global shared bus 15b are accessed. The 1 global unshared bus 15a is not used at all.

As a result, even if other CPUs are accessing shared / non-shared data, the processing can be continued without reducing the speed without being involved in stopping the bus. Further, in the eighth embodiment, the first embodiment has been described. However, the present invention is not limited to the first embodiment, and the same applies to the second to fourth embodiments. In addition, a recursive configuration is possible as in the fifth embodiment, and buses can be multiplexed as in the sixth or seventh embodiment.
Embodiment 9 FIG.
Put unshared data in local memory.

  10 is a block diagram showing a multiprocessor device according to Embodiment 9 of the present invention. The same parts as those in Embodiment 1 shown in FIG.

  Here, the non-shared data, especially the work area, is allocated only to a certain address. When the CPU accesses the work area, the (i, 1) th local memory 86 is accessed from the address information. This (i, 1) local memory 86 is dedicated to the i-th CPU 11. Since the work area itself is closed by the corresponding process (CPU), there is no need to go outside. If it is not necessary to go outside, the first global bus 35 may not be used. As a result, the bus usage rate is extremely reduced.

If the local memory 86 for the work area is small, the memory hung on the first global bus may be used as the work area. Further, when the local memory 86 is slow as shown in FIG. 11, the local memory 86 may be accessed through the (i, 1) local cache memory 12. In any case, in the ninth embodiment, since the bus usage rate decreases, higher speed can be expected. When the bus usage rate decreases, it is advantageous to implement the third or fourth embodiment. Implementing this Embodiment 3 or 4 leads to area reduction. 10 and 11 are based on the third embodiment from this viewpoint. When based on Embodiment 3, it becomes a very simple structure.
Embodiment 10 FIG.
Judgment method 1 of shared / non-shared Judgment by address 1
Up to this point, the embodiment has been described on the assumption that the CPU can determine whether the CPU is shared or not. However, from this embodiment, what kind of CPU is appropriate for constructing the previous embodiments. Or what kind of peripheral circuit should be attached even if it is a general CPU.

  FIG. 12 is a block diagram showing a multiprocessor device according to Embodiment 10 of the present invention. Reference numeral 11 denotes a CPU according to Embodiment 1 (or an embodiment based on this). Reference numeral 101 denotes an i-th CPU main body. The i-th CPU main body 101 itself does not need a function for determining whether to share or not share. The i-th CPU main body unit 101 is an i-th CPU main body address bus terminal 101a indicating an address to be accessed, an i-CPU main body data bus terminal 101b for conveying information read from the address or transmitting information to be written, reading, writing, etc. An i-th CPU main body control bus terminal 101c for outputting i-CPU main body control information is provided.

  Reference numeral 102 denotes an i-th address sharing / non-shared bus selection device. The i-th CPU address selection device CPU side terminal 102a, the i-th address selection device sharing side terminal 102b connected to the i-th CPU body address bus terminal 101a of the CPU body 101, An i-th address selection device non-shared terminal 102c and an i-th address selection device determination input terminal 102d are provided. In this i-th address sharing / non-shared bus selection device 102, if the information "shared" is input to the i-th address selection device determination input terminal 102d, the i-th CPU selection device CPU side terminal 102a and the i-th address selection device sharing side terminal When 102b is connected and information “non-shared” is input to the i-th address selection device determination input terminal 102d, the i-th CPU address selection device CPU-side terminal 102a and the i-th address selection device non-shared side terminal 102c are connected.

  Reference numeral 103 denotes an i-th data sharing / non-shared bus selection device. The i-th CPU data selection device CPU side terminal 103a, the i-th data selection device sharing side terminal 103b connected to the i-th CPU main body data bus terminal 101b of the CPU main body 101, An i-th data selection device non-shared terminal 103c and an i-th data selection device determination input terminal 103d are provided. In this i-th data sharing / non-shared bus selection device 103, if the information "shared" is input to the i-th data selection device determination input terminal 103d, the i-th data selection device CPU side terminal 103a and the i-th data selection device sharing side terminal If the information “non-shared” is input to the i-th data selection device determination input terminal 103d, the i-th CPU data selection device CPU-side terminal 103a and the i-th data selection device non-shared side terminal 103c are connected.

  Reference numeral 104 denotes an i-th control shared / non-shared bus selection device. The i-th CPU control selection device CPU side terminal 104a, the i-th control selection device sharing side terminal 104b connected to the i-th CPU main body control bus terminal 101c of the CPU main body 101, It has an i-th control selection device non-shared side terminal 104c and an i-th control selection device determination input terminal 104d. In this i-th control shared / non-shared bus selection device 104, if the information "shared" is input to the i-th control selection device determination input terminal 104d, the i-th CPU control selection device CPU side terminal 104a and the i-th control selection device sharing side terminal If 104b is connected and the information “non-shared” is input to the i-th control selection device determination input terminal 104d, the i-th CPU control selection device CPU-side terminal 104a and the i-th control selection device non-shared side terminal 104c are connected.

  The i-th CPU 11 has a (i, 1) CPU-side shared bus terminal 11a and an (i, 1) CPU-side unshared bus terminal 11b. The wiring from the (i, 1) CPU-side shared bus terminal 11b of the i-th CPU 11 is divided into the address, data, and control inside the i-th CPU 11, and each of the i-th address shared / non-shared bus selection device 102 is divided. I-th address selection device shared side terminal 102b, i-th data selection / shared-bus selection device 103's i-th data selection device shared-side terminal 103b, i-th control shared / non-shared bus selection device 104's i-th control selection device It is connected to the shared terminal 104b.

  The wiring from the (i, 1) CPU-side unshared bus terminal 11a of the i-th CPU 11 is divided into three areas of address, data, and control inside the i-th CPU 11, and each of the i-th address sharing / non-shared bus selection is selected. Device 102, i-th address selection device non-shared side terminal 102c, i-th data sharing / non-shared bus selection device 103, i-th data selection device non-shared side terminal 103c, i-th control shared / non-shared bus selection device 104 The i control selection device is connected to the non-shared side terminal 104c.

  Reference numeral 105 denotes an i-th shared / non-shared determination device, which has an address bus input terminal 105a connected to the i-th CPU main body address bus terminal 101a, an i-th address shared / non-shared bus selection device 102, an i-th data shared / non-shared device. The i-th address selection device determination input terminal 102d, the i-th data selection device determination input terminal 103d, and the i-th control selection device determination input terminal of each of the non-shared bus selection device 103 and the i-th control shared / non-shared bus selection device 104. And an i-th selection determination output terminal 105b connected to 104d. The i-th shared / non-shared determination device 105 may be a fixed circuit.

Separating sharing / non-sharing according to address information to be accessed In the tenth embodiment, sharing or non-sharing is known from an address (address) to access. The user previously separates the address where shared data is placed (for example, addresses 0000 to 7FFF) and the address where unshared data is placed (for example, addresses 8000 to FFFF). The user creates a program according to the divided address information. When the i-CPU main unit 101 receives a data access command while decoding a program, it outputs information “read” or “write” from the control bus input / output, and in the case of read, outputs an address accessed from the address bus input / output In the case of writing, an address to be accessed is output from the address bus input / output, and data to be written is output from the data bus input / output.

  Next, the i-th shared / non-shared determination device 105 receives the data information output from the i-th CPU main body unit 101 and determines whether this is an address to which shared data is allocated or an address to which non-shared data is allocated. The result is sent to each of the i-th address sharing / non-shared bus selection device 102, the i-th data sharing / non-shared bus selection device 103, and the i-th control shared / non-shared bus selection device 104 through the i-th selection determination output terminal 105b. Information indicating that “shared data has been accessed” or “unshared data has been accessed” is transmitted to the i-th address selection device determination input terminal 102d, the i-th data selection device determination input terminal 103d, and the i-th control selection device determination input terminal 104d. . The i-th address sharing / non-shared bus selection device 102, the i-th data sharing / non-shared bus selection device 103, and the i-th control shared / non-shared bus selection device 104 connect the buses in response to this result.

  As described above, dividing shared / non-shared according to the assigned address is very effective for simplifying the logic circuit of the i-th shared / non-shared determining apparatus 105. When sharing / non-sharing is divided between 0000-7FFF and 8000-FFFF, the i-th sharing / non-sharing determination device 105 can be realized by adding at most one inverter to the highest line of the address. Thus, there is not much functional load that separates sharing / non-sharing. As a result, the functional load can be reduced as compared with the conventional example.

Further, the i-th CPU main body may be replaced with a general CPU that does not have shared / unshared determination, and each shared / non-shared determination device and determination device may be used as a peripheral circuit. Since it can be replaced with a normal CPU (which does not have shared / non-shared determination), it can be created with inexpensive components. Since each shared / non-shared determination device 105 is a simple selector, it can be created with a low price although it increases as a part. However, since this method is created when the CPU is created, the user cannot change the memory allocation between shared and non-shared.
Embodiment 11 FIG.
Shared / non-shared determination method 2-Determination by address 2
FIG. 13 shows an eleventh embodiment of the present invention. In the eleventh embodiment, as a shared / unshared determination device, an input is stored as an address and an output is stored as shared / unshared for that address (block). An i-shared / non-shared determination RAM 115 is used.

  In the eleventh embodiment, the upper address (for example, 8 bits) of the address to be accessed is input to the high-speed i-th shared / non-shared determination RAM 115. The i-th shared / non-shared determination RAM 115 stores information on whether the corresponding address is shared or non-shared, and transmits the result to the shared / non-shared decision line as it is. Although not shown, it is easy to rewrite the information in the i-th shared / non-shared determination RAM 115. For example, if the upper 8 bits are “00”, the i-th shared / non-shared determination RAM 115 can be accessed.

In this way, the user can designate a certain shared / non-shared area. However, there is no problem as long as the i-th shared / non-shared determination RAM 115 is large, but the i-th shared / non-shared determination RAM 115 is finite. As a result, it is impossible to set shared / non-shared determination in units of 1 byte. Also, with this method, since only the upper part of the address is viewed, only a fixed block boundary and a fixed length can be specified.
Embodiment 12 FIG.
Judgment method 3 of shared / non-shared Judgment by address 3
FIG. 14 shows an twelfth embodiment of the present invention. The i-th CPU main unit 101 conveys information read from the i-CPU main unit address bus terminal 101a indicating the address to be accessed, or information to be written. And an i-th CPU main body control bus terminal 101c for outputting i-CPU main body control information such as reading or writing.

  Reference numeral 127 denotes an i-th address decoder. The i-th address decoder 127 determines a device to be accessed by an address, and has signal lines “JdgReg”, “PTbl”, and “Other”. In this embodiment, if the address 0000-00FF is specified, a signal “permitted” is sent to “JdgReg”, and if it is 0100-03FF, a signal “permitted” is sent to the “PTbl” signal. “Allow” is sent to “Other”. Since these outputs control the operation of each device, they are treated as one of the control signal lines in the figure.

  The i-th address sharing / non-shared bus selection device 122, the i-th data sharing / non-shared bus selection device 123, and the i-th control shared / non-shared bus selection device 124 each have an operation permission terminal En, and this operation permission terminal. If the input “permitted” is input to En, the operation described in the tenth embodiment is performed. If the input signal is not “permitted”, the iCPU main body address bus terminal 101a of the iCPU main body 101 and the iCPU main body data are input. The bus terminal 101b and the i-th CPU main body control bus terminal 101c are not connected to any of the i-th address / data / control selection device sharing side terminal and the i-th address / data / control selection device non-sharing side terminal.

  The operation permission terminal En of this device is connected to the “Other” terminal of the i-th address decoder 127, and is connected when the i-th CPU main body 101 accesses 0400-FFFF. In the case of 0000-03FF, all buses are connected. Separate.

  The i-th shared / non-shared determination device 125 has an address input terminal 125a, a data input terminal 125b, and a control input terminal 125c, which are the iCPU main body address bus terminal 101a and the iCPU main body data bus terminal of the iCPU main body 101. 101b is connected to the i-th CPU main body control bus terminal 101c. This apparatus is connected to a signal line “JdgReg” of the CPU main body control bus. This apparatus has one latch, and operates when a “permission” signal is output from the “JdgReg” terminal by the i-th address decoder when the CPU accesses 0000-00FF, and becomes accessible at this time.

  Reference numeral 126 denotes an i-th pointer table storage memory. This device has an address input terminal 126a, a data input terminal 126b, and a control input terminal 126c, which are the iCPU main body address bus terminal 101a, the iCPU main body data bus terminal 101b, and the iCPU main body control bus of the iCPU main body 101. It is connected to the terminal 101c. This apparatus is connected to a signal line “PTbl” of the CPU main body control bus. This apparatus has one latch, and operates when a “permission” signal is output from the “PTbl” terminal by the i-th address decoder 127 when the CPU accesses 0100-03FF, and becomes accessible at this time. .

  For easier understanding, FIG. 15 shows a memory map of the twelfth embodiment viewed from the i-th CPU main body 101.

  The twelfth embodiment is described in detail in a computer configuration in which memory management is performed by software in a method called “handle” (this content is edited by Apple Computer, “Inside Macintosh Vol I, II” (Berkeley Publishing)). Applied).

  First, when a part of the memory is used as a block (for example, addresses 0400 to 04FF), the head address (address 0400) and the length (256 bytes = 0100 (Hex) bytes) of the memory block are paired in the pointer table. A certain address in the pointer table (here, “0400” at address 0010 and “0100” at address 0014) is described. When accessing this memory block, the access is made at the address (address 0010) on the pointer table where the contents of the start address of the memory block are placed by software. The address on the pointer table is called “handle”. Therefore, when a user-created program accesses a certain location (8th from the beginning) of this memory block, the content of the handle (address 0010) is read (the content of address 0010 is 0400), and this content (address 0010 is further read). The address (address 0407) obtained by adding the added value (8-1) from the address 0400) is accessed. The computer configuration used in this embodiment is all implemented by software.

  In this embodiment, a “shared / non-shared” bit is added to the information in this pointer table, and the operation when this shared / non-shared bit is added will be described with reference to FIG. When a user-created program accesses a location (eighth from the beginning) of this memory block, the contents of the handle (address 0010) (the content of address 0010 is 0400) are read (step ST121).

  At this time, the i-th address decoder 127 “permits” access only to the i-th pointer table, and the i-th CPU main body 101 can read the contents of the address 0100 from the pointer table. On the other hand, since the i-th address sharing / non-shared bus selection device 122, the i-th data sharing / non-shared bus selection device 123, and the i-th control shared / non-shared bus selection device 124 are not permitted to operate, they disconnect the bus. Next, the shared bit is similarly read (step ST122).

  Next, the read shared information is accessed (by accessing an arbitrary address of 0000-00FF) to the i-th shared / non-shared determination device 125 (step ST123). At this time, each shared / non-shared bus selection device 122, 123, 124 still keeps the bus disconnected.

  At the last step ST124, when the i-th CPU main body 101 goes to access the address (address 0407) obtained by adding the added value (8-1) from the handle contents (address 00010 which is the contents of address 0010), the address Each shared / non-shared bus selection device 122, 123, 124 starts operation by the decoder, and connects to a desired bus by determining shared or non-shared.

(Additional boundary degrees of freedom)
When comparing the twelfth embodiment and the eleventh embodiment, in the eleventh embodiment, only sharing / non-sharing with a fixed boundary and length can be set. Sharing or non-sharing can be set at the boundary (start address) and any length. As a precaution in the twelfth embodiment, it is necessary to prevent access to non-shared areas of other CPUs. In addition, since the determination of sharing / non-sharing is handled by the CPU in terms of software (it is difficult to be in charge of hardware), the memory access is slightly delayed.

  Although not shown, the i-th shared / non-shared determination device 125 may be used by this register as long as it is the i-CPU main body 101 (CPU component) that can immediately output the contents written in a certain register to the outside as it is. (For example, register B). As a result, step ST123 can be omitted, resulting in high speed. When the same thing is configured as a chip, it is possible to draw only one aluminum wiring from the i-th CPU main body 101 and connect it to each shared / non-shared selection terminal.

In this example, a case where a memory block is secured / deleted / changed will be briefly described. The pointer table is originally shared information of each CPU, but the pointer table information is often referred to in this system system, and is written when a memory block is secured, deleted, or changed (only explained below). Is rare. If there is a change in the memory block, the CPU that generated the change writes the changed handle and its contents somewhere in the shared area in advance, then interrupts all the CPUs at once, and all the CPUs The contents of the i-th pointer table storage memory 126 may be revised by reading the contents.
Embodiment 13 FIG.
Shared / non-shared determination method 4-Determination by address 4
In the tenth to twelfth embodiments, the method applied to the multiprocessor device shown in the first to ninth embodiments using the single-use CPU (CPU main body) as it is described. In the thirteenth embodiment, a case where the single-use CPU itself is applied and improved by mounting necessary functions will be described.

  In the thirteenth embodiment, a single-use CPU (CPU main unit) will describe an improved application method for performing sharing / non-sharing determination for a CPU that performs memory management in a segment. The segment itself is not different from the memory block of the twelfth embodiment. A segment is described by a segment descriptor (corresponding to the pointer table of the twelfth embodiment shown in FIG. 15), and the segment descriptor has a head address (for example, address 0400), a length (for example, 0100 bytes), status information bit, and the like. The segment descriptors are arranged in a segment descriptor table (corresponding to the pointer table in the twelfth embodiment), and each is given a segment number (given by 0, 1, 2,..., Corresponding to the handle in the twelfth embodiment). I'm leaning. When the CPU accesses the memory, it reads the start address (start address of segment 7, address 0400) and status bit from the storage address of this segment number (for example, 7) and the status bit with one instruction, and further from that address (address 0400) The relative address (8-1) is added (address 0407) to access the memory. A characteristic feature of this method is that this processing is implemented by hardware with one instruction in terms of software.

(Revision policy of single CPU (CPU main unit))
However, in general, a CPU that performs memory access by such segment management does not output “read segment” or “read segment descriptor” to the outside. Also, it does not output “which segment you are reading” now. Therefore, sharing / non-sharing determination by segment cannot be performed outside. As an easy method, a method of arranging a shared segment in the shared castle and a non-shared segment in the non-shared region based on the tenth embodiment is simple, but the flexibility does not work.

  If writing is performed to a shared / non-shared device by software at the time of memory access as in the twelfth embodiment, the past abundant software compatibility is lost. Therefore, in this embodiment, a simple revision of pulling out a wiring that is functional and closed inside from a CPU that is a black box in this embodiment is shared / not shared with this single CPU. Judgment can be made.

  FIG. 17 is a block diagram showing a multiprocessor device according to the thirteenth embodiment. In FIG. The CPU main body 386 has an “Sgr” terminal 131d for determining whether to read the segment descriptor table or to read the other segment descriptor table. The Sgr terminal 131d electrically outputs information “ReadSGT” when reading the segment descriptor table, and outputs information “AccMem” when reading the segment. The CPU main body 386 has a segment number output “SN0” terminal 131e for outputting a segment number to be accessed when the Sgr terminal 131d outputs AccMem information.

  The SN0 terminal 131e outputs a segment number when the CPU actually accesses the memory (Sgr: AccMem). Functionally, signals corresponding to these terminals should be present in the CPU main body, and it is not so much labor to draw them out with aluminum wiring.

  Reference numeral 136 denotes a segment descriptor table, which is a RAM. This segment descriptor table has an “enable (EN)” signal and is connected to the Sgr terminal 131 d of the CPU main body 386. The segment descriptor table 136 operates when the “permission (EN)” input becomes “ReadSDT” (Sgr: ReadSDT, when the CPU reads the segment disk table). Output a segment descriptor. When permission EN is other than ReadSDT, nothing is output and nothing is output.

  Reference numeral 135 denotes a shared / non-shared determination device which is a RAM and has a segment number having an input terminal 135a and a shared / non-shared determination output terminal 135b. This shared / non-shared determination device itself is the same as in the eleventh embodiment, and the difference is not the upper 8 bits of the address but the segment number output (accessed) from the SN0 terminal of the CPU main unit 386. As in the eleventh embodiment, the shared / unshared determination device 135 has shared / nonshared information corresponding to the input segment (the upper 8 bits of the address in the eleventh embodiment), and the given segment number. The shared / non-shared information is output to the shared / non-shared determination output.

  Each of the shared / non-shared bus selection devices 122, 123, and 124 has an operation permission terminal. This operation permission terminal is connected to the Sgr terminal of the CPU main body 386, and is shared if the operation permission terminal is “AccMem”. / Bus connection is performed according to the information of the non-sharing judgment input. When the operation permission signal is other than this, the bus is not operated and all the buses are disconnected.

Next, the operation will be described.
The CPU main body 386 performs an operation of reading the segment descriptor table by one software memory access instruction and an operation of accessing the segment itself. First, when the CPU body 386 accesses the segment descriptor table 136, the CPU body 386 outputs a memory access request according to a predetermined access procedure and outputs a signal “ReadSDT” from the Sgr terminal 131d. Each shared / non-shared bus selection device 122, 123, 124 does not operate because the signal input to the operation permission signal connected to the Sgr terminal 131d is “ReadSDT”, and all the buses are disconnected. Although the shared / non-shared determination device 135 may operate, the output becomes invalid because each shared / non-shared bus selection device 122, 123, 124 does not operate. On the other hand, the segment descriptor table 136 starts its operation because the EN signal becomes “ReadSDT”, and transmits the segment descriptor to the CPU main body 386.

  Next, when the CPU main unit 386 accesses a segment, “ReadMem” is output from the Sgr terminal 131d of the CPU main unit 386 and the number of the segment to be accessed is output from the SN0 terminal 131e. At this time, since the EN signal is “ReadMem”, the segment descriptor table 136 does not operate and outputs nothing. On the other hand, the shared / non-shared determination device 135 receives the segment number output from the SN0 terminal 131e of the CPU main body 386, and outputs the shared / non-shared determination of the corresponding segment from the information stored in the RAM. . Since each shared / non-shared bus selection device 122, 123, 124 has "AccMem" input to the operation permission terminal, each bus is connected according to the result from each shared / non-shared determination input. At this time, there is no need to change anything in terms of software.

  According to the thirteenth embodiment, the determination of sharing / non-sharing is made possible by implementing a revision to the single-use CPU (CPU main unit) with a minimum amount of effort. In the case of the thirteenth embodiment, the labor referred to here is to provide a terminal corresponding to the “Sgr” terminal 131d and to provide a terminal corresponding to the “SN0” terminal 131e, so that the aluminum wiring is exposed outside. There is no labor. In addition, these terminals should be present in the function of a single-use CPU that implements the above-mentioned segment embedding, and it is not necessary to mount a function of a single CPU. As a result, it can be revised relatively cheaply.

  Further, with the above method, there is nothing in terms of software even though internal and external hardware are added. This means that previous software assets can be inherited. Further, when a single CPU for performing segment management is mounted in the tenth embodiment, there is a restriction that the shared segment is placed in the shared area and the non-shared segment is placed in the non-shared area. Then, there is an advantage that such restrictions are eliminated and flexibility is available.

  Here, as in the twelfth embodiment, there may be a process of segment generation, change, and deletion and a change in information that maintains consistency in the shared / non-shared determination apparatus 135 accompanying this. Because it is not the essence of the patent and what happens infrequently, explanation is omitted.

  In the thirteenth embodiment, it is assumed that the CPU main body 386 is a single chip. However, as shown in FIG. 18, the CPU main body 386 may separately include a shared / non-shared determination device 135. As a result, the CPU main body 386 has a “Sgr” terminal and a “shared / non-shared determination” terminal 131f.

  In the thirteenth embodiment, it is assumed that the CPU main body 386 is a single chip. However, as shown in FIG. 19, it may include a shared / non-shared determination device 135 and a segment disk table 136 separately. . As a result, the CPU main body 386 has only the “shared / non-shared determination” terminal 131f.

  The shared / non-shared terminal 131f shown in FIGS. 18 and 19 may not be determined by the RAM, which is the shared / non-shared determination device 135. For example, it may be a fixed circuit. Further, the shared / non-shared determining apparatus 135 incorporated in the inside in the thirteenth and subsequent embodiments is applied so as to determine by segment, but other determination materials may be used.

As described above, in the thirteenth embodiment, the shared / unshared determination is applied to the CPU and cache configuration of the present invention by using the CPU that determines the segment number. 18 and 19 show that the shared / non-shared determination device 135 may be provided in the CPU. Further, although the shared / non-shared determination device 135 may be fixed, shared / non-shared may be divided according to an instruction.
Embodiment 14 FIG.
(Complex system)
FIG. 20 is a block diagram showing a multiprocessor device according to the fourteenth embodiment. The fourteenth embodiment is based on the fourth and eighth embodiments. In the figure, reference numeral 171 denotes a CPU according to the twelfth embodiment. Reference numeral 172 denotes a CPU according to the thirteenth embodiment.

  The fourteenth embodiment is a method of fusing nine or more different computer systems as one system. If this embodiment 14 is used for convenience, it is possible to fuse two or more computer systems as one system, as is apparent from the figure. As an effect, two systems can share one data. This CPU does not have to be limited to the twelfth and thirteenth embodiments. At least, the CPU and the cache configuration according to the present invention can be assembled as long as the CPU can clearly separate the shared data and the non-shared data and select the bus according to this.

1 is a block diagram of a multiprocessor device according to a first embodiment of the present invention. FIG. It is a block diagram of the multiprocessor device by Embodiment 2 of this invention. It is a block diagram of the multiprocessor device by Embodiment 3 of this invention. It is a block diagram of the other multiprocessor device by Embodiment 3 of this invention. It is a block diagram of the multiprocessor device by Embodiment 4 of this invention. It is a block diagram of the other multiprocessor device by Embodiment 4 of this invention. It is a block diagram of the multiprocessor device by Embodiment 5 of this invention. It is a block diagram of the multiprocessor device by Embodiment 6 of this invention. It is a block diagram of the multiprocessor device by Embodiment 8 of this invention. It is a block diagram of the multiprocessor device of Embodiment 9 of this invention. It is a block diagram of the other multiprocessor device by Embodiment 9 of this invention. It is a block diagram of the multiprocessor device by Embodiment 10 of this invention. It is a block diagram of the multiprocessor device by Embodiment 11 of this invention. It is a block diagram of the multiprocessor device by Embodiment 12 of this invention. 22 is a memory map according to the twelfth embodiment. 19 is memory access software according to the twelfth embodiment. It is a block diagram of the multiprocessor device by Embodiment 13 of this invention. It is a block diagram of the other multiprocessor device by Embodiment 13 of this invention. It is a block diagram of still another multiprocessor device according to the thirteenth embodiment of the present invention. It is a block diagram of the multiprocessor device by Embodiment 14 of this invention. It is a block diagram of the conventional multiprocessor device.

Explanation of symbols

  11 CPU, 11a shared bus terminal, 11b, 11c unshared bus terminal, 12, 62 local cache memory, 13a, 63a local unshared bus, 13b local shared bus, 14 processor unit, 15a, 55a, 65a global unshared bus, 15b, 55b Global shared bus, 16 Shared cache memory, 17a, 57a, 67a Non-shared interface, 17b, 37, 57b Shared interface, 19a, 69a Non-shared memory, 39 External memory, 54 Recursive processor unit.

Claims (2)

CPU,
A processor unit connected to the CPU and including a first cache memory that exclusively stores information for each CPU;
A first shared bus connecting each of the plurality of processor units;
A second cache memory connected to the plurality of processor units and storing information shared by the plurality of processor units;
An interface unit connected to the first shared bus and outputting a control signal for accessing an external memory storing shared information shared by the plurality of processor units;
A multiprocessor device. 2. The multiprocessor device according to claim 1, wherein the second cache memory is a cache memory positioned lower than the first cache memory, and is connected to the first shared bus. 3. .

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