JP2008191796A - Analysis device, analysis method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reproduce a memory state at any time in the past from information obtained by normal operation of equipment or a program of a debugging target. <P>SOLUTION: A bus access information storage part 1 stores bus access information wherein data flowing on a bus between a memory and a CPU of the debugging target equipment are arranged in time order. When failure occurs in the debugging target equipment, a bus information analysis part 2 traces a record of the bus access information back to a specific past time point based on memory information 6 when occurrence of the failure, and analyzes the bus access information. The bus information analysis part 2 decides a read data value as storage contents at the specific time point of an address when bus access is read to the memory, and sets the address written with the data as an indefinite area when write to the memory. An indefinite area search part 5 further traces and analyzes the bus access information from the specific time point, specifies the storage contents of the indefinite area at the specific time point, and reproduces memory contents at the specific time point. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory backtrace technique used, for example, when debugging a computer program.

  The conventional memory backtrace method reproduces the memory state at an arbitrary past time by adding a means for acquiring information necessary for memory backtrace to a program or device to be debugged ( For example, Patent Document 1).

11 and 12 are an overall view and a flowchart of the reverse step execution means in Patent Document 1.
The debugging means in FIG. 11 is assumed to be an instruction execution simulator or a debugger, and interprets and executes machine language instructions of the program to be debugged one by one.
The buffer writing means stores the contents of the register and memory that are changed when each instruction is interpreted in the execution history buffer.
The reverse step execution means shown in FIG. 12 realizes reproduction of past memory contents by sequentially writing back the pre-update register and memory information stored in the execution history buffer.
Japanese Patent Laid-Open No. 5-108404

Since the conventional memory backtrace method changes something to be debugged, there is a considerable difference from the operation of the original program.
As a result, it is difficult to reproduce timing failures (failures that occur as a result of unique execution order of multiple programs that have side effects on each other), which is one of the most difficult to analyze software failures. There was a problem of ending up.

  The main object of the present invention is to solve the above-mentioned problems, and reproduces the memory state at an arbitrary past time from the program to be debugged and information obtained by normal operation of the device. The main purpose is to improve the efficiency of debugging.

The analysis apparatus according to the present invention is
An analysis device for analyzing a program execution in a program execution device that executes a program using a processor and a memory,
When a failure occurs in the execution of the program of the program execution device, the time series information in which the information used between the processor and the memory before the occurrence of the failure is shown in time series A time series information analysis unit that analyzes retroactively to a specific point of time, and specifies storage contents at the specific point of time for each storage area of the memory,
An indeterminate area management unit for managing as an indeterminate area a storage area whose storage content is not specified by analysis by the time-series information analysis unit among the storage areas in the memory;
The time series information is further analyzed retrospectively from the specific time point, and an undefined area search unit for specifying the storage contents of the undefined area at the specific time point is provided.

  According to the present invention, time series information is analyzed retrospectively to a specific time point on the time series to specify the memory content of the memory at the specific time point, and the storage area where the memory content is not specified is managed as an indefinite area and specified. After the analysis up to the point in time, the stored contents of the undefined area at a specific point in time are further determined, so that only the data that normally flows between the processor and the memory of the program execution device can be Memory contents can be reproduced. For this reason, it is not necessary to change the program, and a situation in which the operation of the program is changed can be avoided. In addition, timing failure can be reproduced, and debugging efficiency can be improved.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram showing an overall configuration example of a memory backtrace device (analysis device) 100 according to the present embodiment.
The memory backtrace device 100 is a device that analyzes the execution of a program in a debug target device (program execution device) (not shown). The debug target device (program execution device) is a device that executes a program using a processor and a memory.

In FIG. 1, a bus access information storage unit 1 (time series information storage unit) stores bus access information (time series information). The bus access information is information in which data flowing on a bus between a CPU (Central Processing Unit) of a debug target device and a memory is arranged in time order.
The bus information analysis unit 2 (time-series information analysis unit) is means for reading and analyzing data from the bus access information in the reverse order of time.
The memory information update unit 3 is means for rewriting the contents of the memory information 6 in response to an instruction from the bus information analysis unit 2.
The indefinite area management unit 4 is a means for managing an area in which the contents of the memory information 6 are indefinite according to an instruction from the bus information analysis unit 2.
The indeterminate area search unit 5 is a means for reading and analyzing the bus access information in the reverse order of time in order to determine the value of the indeterminate area managed by the indeterminate area manager 4.
The memory information 6 is a memory area having, as an initial value, memory contents at the time when a failure occurs.

FIG. 2 shows an example of data held in the bus access information in FIG.
The bus access information includes a program counter value (PC value) indicating the address of an instruction fetched for program execution, an instruction fetched with the PC value, an address of a memory accessed by execution of the instruction, and a memory access Read. / Write attribute distinction, data accessed on the memory bus as a result of memory access (value read from memory in case of Read, value written in memory in case of Write) are arranged in the form of records in order of instruction execution It is what is.

FIG. 3 shows an example of the undefined area management table managed by the undefined area management unit 4 in FIG.
The indefinite area management table manages the location where the value of the memory information 6 to be reproduced becomes an indefinite value by the processing of the bus information analysis unit 2, and the address of the indefinite area and the indefinite area are indefinite. It is composed of a value (provisional memory value) temporarily set in the memory information 6 indicating this.

FIG. 4 is a diagram for assisting understanding of the following description, and shows the overall flow of the operation in the present embodiment.
The object of the present embodiment is to use a memory (memory back-up) such as a personal computer other than the device to be debugged from the memory information at the time of failure obtained from the device to be debugged (program execution device) and the bus access information accompanying the execution of the program. On the trace device 100), the memory information of “time point A at which memory contents are to be reproduced” of the debug target device is reproduced. Note that the memory information at the time of the failure is the initial value of the memory information 6 in FIG.
First, the bus access information from the time of failure occurrence to “time A at which the memory contents are to be reproduced” is analyzed by the bus information analysis unit 2 in FIG. 1 and reflected in the memory information as needed.
In this reflection, if the bus access is a read to the memory, the value is fixed, and if the write is to the memory, the value before that moment is overwritten and becomes an unknown value. . When the above is performed until “time point A at which memory contents are to be reproduced”, the memory information at time point A is reproduced in a so-called worm-eating state in which indefinite regions are scattered.
In order to determine the value of this worm-eating indeterminate area going back to the past from time A, the indeterminate area search unit 5 in FIG. Reflect in memory information.
Since the indeterminate area search unit 5 examines bus access information before time A, the value of the area at time A can be determined in both cases of Read and Write for the indefinite area.
By providing the two-stage bus access information analysis unit, the memory information at the time point A can be determined.

In the present embodiment, as shown in FIG. 2, the bus access information storage unit 1 includes the value of read data read from the memory of the debug target device (program execution device) to the processor, and the storage area from which the data has been read. , And bus access information (time-series information) composed of a record indicating the value of the write data written from the processor to the memory and the storage area where the data was written, and the like. When a failure occurs in the execution of the program, the contents of the information used between the processor and the memory are analyzed retrospectively for each record up to a specific point in time in the bus access information (time point A in FIG. 4). Then, the storage content at a specific time is specified for each storage area of the memory. Specifically, when the read data value is indicated in the acquired record, the bus information analysis unit 2 stores the value of the read data at a specific time in the storage area indicated in the record. When the value of write data is indicated in the acquired record, the storage area indicated in the record is set as an indefinite area.
The undefined area management unit 4 manages a storage area whose storage contents are not specified by analysis by the bus information analysis unit 2 among the storage areas in the memory as an undefined area.
Further, the indeterminate area searching unit 5 analyzes the bus access information retroactively from the specific time point (time point A in FIG. 4), and specifies the storage contents of the indefinite area at the specific time point. Specifically, the indeterminate area searching unit 5 acquires a record of bus access information while going back further from a specific time (time A in FIG. 4), and the storage area indicated in the acquired record matches the indefinite area. If the storage area indicated in the acquired record matches the indefinite area, the value of the data indicated in the record is specified as the storage content of the indefinite area at a specific point in time.

Next, the operation of each element will be described with reference to the flowcharts of FIGS.
First, FIG. 5 shows a processing flow (time-series information analysis step) of the bus information analysis unit 2.
First, the bus information analysis unit 2 initializes a Pos variable indicating from which position of the bus access information the record is read (S51).
Usually, it indicates the position of the last record, which is the last bus access information where a failure is detected.
Next, the bus information analysis unit 2 decrements Pos (S52), and then reads the bus access information record at the position of Pos from the bus access information (S53).
If the read bus access information record does not have a read / write memory access attribute in step S54, the bus information analysis unit 2 proceeds to analysis end condition determination (S57).
If there is a memory access attribute in step S54, the bus information analysis unit 2 determines whether it is Read or Write, and if it is Read, the memory contents at that time can be determined as the data value in the record, so that the memory information update unit 3 is called (S55), and the undefined area management unit 4 is instructed to delete the corresponding entry from the undefined area management table. If the memory access attribute is Write, the undefined area management unit 4 is instructed to add an entry to the undefined area management table (S56).
Thereafter, the bus information analysis unit 2 determines whether or not the bus access information analysis is finished in step S57. If the analysis is finished, the bus information analysis unit 2 calls the indeterminate area search unit 5 (S58) and ends the process.
If the analysis is not finished, the process returns to step S52 to continue analyzing the bus access information.
The end condition in step S57 is a condition for determining whether or not the record position corresponding to the specific time point A in FIG. 4 has been reached. For example, a specific number of records (for example, 100 records) are traced back. Or when a specific record specified in advance (a record characteristic in the analysis of bus access information) is reached.
In addition, time information (for example, time information incremented to the PC value indicated in each record) is added to each record of the bus access information, and the process ends when the time information of the bus access information goes back a specific time. You may do it.

FIG. 6 shows a processing flow (undefined area management step) of the undefined area management unit 4.
The undefined area management unit 4 starts the operation in response to an instruction from the bus information analysis unit 2, and first determines whether the access attribute of the bus access information record passed from the bus information analysis unit 2 is Read or Write (S61). In both cases of Read and Write, the undefined area management unit 4 acquires access attribute information from the bus information analysis unit 2.
In the case of Read, since the contents of the memory information are confirmed, the undefined area management unit 4 checks whether there is an entry with the same address already registered as an undefined area in the undefined area management table shown in FIG. 3 (S62). If there is an entry, the entry is deleted (S63), and if not, nothing is done and the process is terminated.
In the case of Write in step S61, the undefined area management unit 4 checks whether there is an entry with the same address already registered as an undefined area in the undefined area management table (S64). Add (S65), instruct the memory information updating unit 3 to write data indicating indefinite (S66), and terminate the process.
If there is no entry with the same address in step S64, the processing is terminated without doing anything.

FIG. 7 shows a processing flow (indefinite area search step) of the indeterminate area search unit 5.
The indeterminate area search unit 5 is executed immediately before the processing of the bus information analysis unit 2 ends, and obtains an indeterminate area entry of the indeterminate area management table from the indeterminate area management unit 4 (S71).
Next, the undefined area search unit 5 holds the record position of the bus access information passed from the bus information analysis unit 2 and copies it to the new variable rPos (S72).
The undefined area search unit 5 decrements rPos (S73), and then reads the record at the position of rPos from the bus access information (S74).
If the read record has a memory access attribute (S75), the undefined area search unit 5 checks whether the address indicated in the undefined area entry matches the address indicated in the read bus access information record. Determination is made (S76).
If there is no memory access attribute in the bus access information record (S75), or the address of the bus access information record does not match the address indicated in the indefinite area entry (S76), the indefinite area searching unit 5 The process returns to step S73 in order to obtain the bus access information at the next position.
If the address of the undefined area entry matches in step S76, the memory information update unit 3 is instructed to write the data value of the bus access information record to the memory information 6 (S77), and then the entry is deleted from the undefined area management table. (S78). Thereafter, the presence / absence of an entry in the undefined area is checked (S79). If there is an entry, the process is repeated from step S71. If there is no entry, the process is terminated.
The data value written to the memory information in step S76 is the data value stored in the indefinite area at the specific time A shown in FIG.

  Note that the memory information update unit 3 is a process for writing only the specified value to the address specified by the bus information analysis unit 2, the indeterminate region management unit 4, or the indeterminate region search unit 5 for the memory information 6. The description of the processing flow and processing is omitted.

  As described above, when writing to the memory, the memory contents are once indefinite, and after analyzing the necessary bus access information, the value of the indefinite memory area is determined by going back in time. The memory contents at the past time can be reproduced only from the data normally flowing through the bus.

As described above, in the present embodiment, for the bus access information flowing through the bus between the processor and the memory and the memory information indicating the memory contents at the time of the failure,
(A) Bus information analysis means for tracing the bus access information in reverse order of time and analyzing the update status of the memory,
(B) memory information updating means for rewriting the contents of the memory information;
(C) Undefined area management means for managing an area in which the value of the previous time cannot be specified by writing to the memory;
(D) A memory back that has indefinite area search means for tracing the bus access information in the reverse order of time and specifies the value of the indefinite area in the memory information, and reproduces the memory contents at an arbitrary past time from the point of failure. The trace method was explained.

Embodiment 2. FIG.
In the first embodiment described above, the memory contents are reproduced at an arbitrary time point in the past. Next, the embodiment in the case of reproducing the memory contents at a specific point on the program will be described. Show.
Note that the memory backtrace apparatus 100 according to the present embodiment also has the same configuration as that shown in FIG.

FIG. 8 shows a processing flow (time-series information analysis step) of the bus information analysis unit 2 when reproducing the memory contents when passing through a specific position of the program.
In FIG. 8, S51 to S58 are the same as FIG.
In FIG. 8, after the analysis of the bus access information and the update of the memory information and the undefined area management table are completed in steps S54 to S56, the PC value of the bus access information at the Pos position is equal to the predesignated value in S81. If the two match, the analysis of the bus access information is terminated, and the process proceeds to S58.
Thereby, the analysis of the bus access information can be interrupted at a specific position (PC value) of the program, and the memory contents at that time can be reproduced.

That is, in the example shown in FIG. 8, the bus information analysis unit 2 sets a record indicating a specific program counter value among the records of the bus access information as a specific time point in time series (time point A in FIG. 4), The bus access information record is acquired retroactively to the record indicating the specific program counter value, and each acquired record is analyzed, and the indefinite area search unit 5 records the specific program counter value indicated The bus access information record is acquired further retroactively, and each acquired record is analyzed.
In the example of FIG. 8, the bus information analysis unit 2, the memory information update unit are the same as those in the first embodiment except that the PC value is referred to as one of the criteria for determining the end of analysis of the bus information analysis unit 2. 3. The operations of the undefined area management unit 4 and the undefined area search unit 5 are the same as those described in the first embodiment.

FIG. 9 shows a processing flow (time-series information analysis step) of the bus information analysis unit 2 when reproducing the memory content at the time when the content at the specific position in the memory is changed to a specific value.
In FIG. 9, S51 to S58 are the same as FIG. 5, and when the bus access information has the Write attribute, the management information of the indefinite area is updated in S56, and then the address and data value of the bus access information are previously set in S91. It is determined whether or not it matches the specified value, and if it matches, the analysis of the bus access information is terminated and the process proceeds to S58.
As a result, the analysis of the bus access information can be interrupted at the time when the content at the specific location in the memory is changed to a specific value, and the location of the program at that time can be identified and the memory content can be reproduced.

In other words, in the example illustrated in FIG. 9, the bus information analysis unit 2 selects a record indicating at least one of a specific data value and a specific storage area among the records of the bus access information at a specific point in time ( As shown in FIG. 4A), the bus access information record is acquired retroactively until a record indicating at least one of a specific data value and a specific storage area, and each acquired record is analyzed to obtain an indefinite area. The search unit 5 acquires a record of bus access information further retroactively from a record in which at least one of a specific data value and a specific storage area is indicated, and analyzes each acquired record.
In the example of FIG. 9, the bus information analysis unit 2, the memory information update unit are the same as those in the first embodiment except that the data value or the address is referred to as one of the analysis end determination criteria of the bus information analysis unit 2. 3. The operations of the undefined area management unit 4 and the undefined area search unit 5 are the same as those described in the first embodiment.

  As described above, in the present embodiment, the memory back trace method has been described in which the bus information analyzing unit interrupts the tracing of the bus access information when the bus counter is matched with the program counter value specified in advance.

  In this embodiment, a memory back trace method is described in which the bus information analysis means interrupts the tracing of the bus access information when it matches the address of the memory designated in advance and the data value written to the address. did.

Embodiment 3 FIG.
In the above embodiment, the reproduction position of the memory contents is specified. Next, an embodiment in the case where the indeterminate area search unit is executed at high speed will be described.
Note that the memory backtrace apparatus 100 according to the present embodiment also has the same configuration as that shown in FIG.

FIG. 10 shows that not all memory information is required when debugging software, and there are many cases where memory information in a very narrow limited area is used as a clue. The processing flow (indefinite area search step) of the indefinite area search part 5 in the case of limiting is shown.
10, S71 to S79 are the same as FIG.
When the entry of the undefined area is obtained in step S71, the undefined area searching unit 5 determines whether or not the address of the undefined area is in the memory area in the range (analysis target storage area range) designated in advance in S101, If it is within the area, the process proceeds to S79 to obtain the next indefinite area.
As a result, the bus access information search process from S73 to S76 can be omitted for an indeterminate area that does not require value determination, and the entire indeterminate area search process can be executed at high speed.

That is, in the example of FIG. 10, the indeterminate area searching unit 5 designates the range of the storage area to be analyzed as the analysis target storage area range, and acquires the bus access information record while going back further from the specific time point. If the storage area indicated in the record is included in the analysis target storage area range and the storage area indicated in the acquired record is included in the analysis target storage area range, the acquired record It is determined whether or not the storage area shown in FIG. On the other hand, when the storage area indicated in the acquired record is not included in the analysis target storage area range, the record is not analyzed.
As the analysis target storage area, only the memory around the memory address last detected by the bus information analysis unit 2 may be the analysis target.
The present embodiment is the same as the first embodiment except that the indeterminate area searching unit 5 determines whether or not it is within the analysis target storage area range for speeding up the processing. The operations of the memory information update unit 3, the undefined area management unit 4, and the undefined area search unit 5 are the same as those described in the first embodiment.

  As described above, the present embodiment has described the memory backtrace method in which only the memory in the vicinity of a specific address is subjected to value specification in the indeterminate region search means.

  Further, in the present embodiment, the memory back trace method is described in which only the memory in the vicinity of the memory address detected last by the bus information analysis unit in the undefined region search unit is targeted for value specification.

Finally, a hardware configuration example of the memory backtrace device 100 shown in the first to third embodiments will be described.
FIG. 13 is a diagram illustrating an example of hardware resources of the memory backtrace apparatus 100 illustrated in the first to third embodiments. Note that the configuration in FIG. 13 is merely an example of the hardware configuration of the memory backtrace device 100, and the hardware configuration of the memory backtrace device 100 is not limited to the configuration described in FIG. There may be.

In FIG. 13, the memory backtrace apparatus 100 includes a CPU 911 (also referred to as a central processing unit, a central processing unit, a processing unit, a processing unit, a microprocessor, a microcomputer, and a processor) that executes a program. The CPU 911 is connected to, for example, a ROM (Read Only Memory) 913, a RAM (Random Access Memory) 914, a communication board 915, a display device 901, a keyboard 902, a mouse 903, and a magnetic disk device 920 via a bus 912. Control hardware devices. Further, the CPU 911 may be connected to an FDD 904 (Flexible Disk Drive), a compact disk device 905 (CDD), a printer device 906, and a scanner device 907. Further, instead of the magnetic disk device 920, a storage device such as an optical disk device or a memory card read / write device may be used.
The RAM 914 is an example of a volatile memory. The storage media of the ROM 913, the FDD 904, the CDD 905, and the magnetic disk device 920 are an example of a nonvolatile memory. These are examples of a storage device or a storage unit.
The communication board 915, the keyboard 902, the scanner device 907, the FDD 904, and the like are examples of an input unit and an input device.
Further, the communication board 915, the display device 901, the printer device 906, and the like are examples of an output unit and an output device.

The communication board 915 may be connected to a network. For example, the communication board 915 may be connected to a LAN (local area network), the Internet, a WAN (wide area network), or the like.
The magnetic disk device 920 stores an operating system 921 (OS), a window system 922, a program group 923, and a file group 924. The programs in the program group 923 are executed by the CPU 911, the operating system 921, and the window system 922.

The program group 923 stores programs that execute the functions described as “˜unit” and “˜means” in the description of the first to third embodiments. The program is read and executed by the CPU 911.
In the file group 924, in the description of the first to third embodiments, “determination of”, “calculation of”, “comparison of”, “registration of”, “update of”, “setting of” Information, data, signal values, variable values, and parameters indicating the results of the processing described as “.” Are stored as items “˜file” and “˜database”. The “˜file” and “˜database” are stored in a recording medium such as a disk or a memory. Information, data, signal values, variable values, and parameters stored in a storage medium such as a disk or memory are read out to the main memory or cache memory by the CPU 911 via a read / write circuit, and extracted, searched, referenced, compared, Used for CPU operations such as calculation, calculation, processing, editing, output, printing, and display. Information, data, signal values, variable values, and parameters are stored in the main memory, registers, cache memory, and buffers during the CPU operations of extraction, search, reference, comparison, calculation, processing, editing, output, printing, and display. It is temporarily stored in a memory or the like.
In addition, arrows in the flowcharts described in the first to third embodiments mainly indicate input / output of data and signals, and the data and signal values are the memory of the RAM 914, the flexible disk of the FDD904, the compact disk of the CDD905, and the magnetic field. Recording is performed on a recording medium such as a magnetic disk of the disk device 920, other optical disks, mini disks, DVDs, and the like. Data and signals are transmitted online via a bus 912, signal lines, cables, or other transmission media.

  In addition, in the description of the first to third embodiments, what is described as “to part” and “to means” may be “to circuit”, “to device”, and “to device”. , “˜step”, “˜procedure”, and “˜processing”. That is, what is described as “˜unit” and “˜means” may be realized by firmware stored in the ROM 913. Alternatively, it may be implemented only by software, or only by hardware such as elements, devices, substrates, and wirings, by a combination of software and hardware, or by a combination of firmware. Firmware and software are stored as programs in a recording medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD. The program is read by the CPU 911 and executed by the CPU 911. That is, the program causes the computer to function as “to part” and “to means” in the first to third embodiments. Alternatively, the procedures and methods of “to part” and “to means” in the first to third embodiments are executed by a computer.

  As described above, the memory backtrace device 100 shown in the first to third embodiments includes a CPU that is a processing device, a memory that is a storage device, a magnetic disk, a keyboard that is an input device, a mouse, a communication board, and a display device that is an output device, A computer including a communication board and the like, and as described above, functions indicated as “˜unit” and “˜means” are realized by using these processing devices, storage devices, input devices, and output devices.

1 is a diagram illustrating a configuration example of a memory backtrace device according to a first embodiment. FIG. 3 is a diagram showing an example of bus access information according to the first embodiment. FIG. 4 shows an example of an indefinite area management table according to the first embodiment. FIG. 3 is a diagram showing an overall flow of data reproduction processing according to the first embodiment. FIG. 3 is a flowchart showing an operation example of a bus information analysis unit according to the first embodiment. FIG. 6 is a flowchart showing an operation example of an undefined area management unit according to the first embodiment. FIG. 6 is a flowchart showing an operation example of an indeterminate area searching unit according to the first embodiment. FIG. 9 is a flowchart showing an operation example of a bus information analysis unit according to the second embodiment. FIG. 9 is a flowchart showing an operation example of a bus information analysis unit according to the second embodiment. FIG. 9 is a flowchart showing an operation example of an indeterminate area searching unit according to the third embodiment. The figure explaining a prior art. The figure explaining a prior art. FIG. 3 is a diagram illustrating a hardware configuration example of a memory backtrace device according to the first to third embodiments.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Bus access information storage part, 2 Bus information analysis part, 3 Memory information update part, 4 Undefined area management part, 5 Undefined area search part, 6 Memory information, 100 Memory backtrace apparatus.

Claims (9)

An analysis device for analyzing a program execution in a program execution device that executes a program using a processor and a memory,
When a failure occurs in the execution of the program of the program execution device, the time series information in which the information used between the processor and the memory before the occurrence of the failure is shown in time series A time series information analysis unit that analyzes retroactively to a specific point of time, and specifies storage contents at the specific point of time for each storage area of the memory,
An indeterminate area management unit for managing as an indeterminate area a storage area whose storage content is not specified by analysis by the time-series information analysis unit among the storage areas in the memory;
An analysis apparatus comprising: an indefinite area search unit that analyzes the time-series information further retroactively from the specific time point and specifies the storage contents of the indefinite area at the specific time point. The analysis device further includes:
A record indicating a value of read data read from the memory to the processor and a storage area from which the data has been read, and a value of write data written from the processor to the memory and the storage area from which the data has been written are indicated. A time-series information storage unit that stores information of a plurality of records having at least records as the time-series information,
The time series information analysis unit
When the record of the time series information is acquired while going back to a specific point in time series, and the value of the read data is indicated in the acquired record, the value of the read data is a storage area indicated in the record The storage area specified as the storage content at the specific time is specified, and when the value of the write data is indicated in the acquired record, the storage area indicated in the record is defined as an indefinite area. The analysis device described in 1. The indefinite region search unit
The record of the time series information is acquired while going back further from the specific time point, and it is determined whether or not the storage area indicated in the acquired record matches the indefinite area, and the storage area indicated in the acquired record 3. The analysis apparatus according to claim 2, wherein when the value matches an indefinite area, a value of data indicated in the record is specified as a storage content of the indefinite area at the specific time. The analysis device includes:
Memory information indicating storage contents of the memory at the time of the failure for each storage area, storage contents specified by the time-series information analysis unit and storage specified by the indefinite area search unit for each storage area The analysis apparatus according to claim 1, further comprising a memory information update unit that updates any of the contents. The analysis device further includes:
A time series information storage unit for storing, as the time series information, information of a plurality of records in which a program counter value of an instruction fetched by the processor in execution of a program is indicated in each record;
The time series information analysis unit
A record showing a specific program counter value among a plurality of records of the time series information is set as the specific time point on the time series, and the record of the time series information is traced back to the record showing the specific program counter value. Parse each acquired record,
The indefinite region search unit
The analysis apparatus according to claim 1, wherein a record of time series information is further acquired from a record indicating the specific program counter value, and each acquired record is analyzed. The analysis device further includes:
A record indicating a value of read data read from the memory to the processor and a storage area from which the data has been read, and a value of write data written from the processor to the memory and the storage area from which the data has been written are indicated. A time-series information storage unit that stores information of a plurality of records having at least records as the time-series information,
The time series information analysis unit
A record in which at least one of a specific data value and a specific storage area is indicated among the plurality of records of the time series information is set as the specific time point on the time series, and at least the specific data value and the specific storage area Get records of time series information back to the record where one is shown, analyze each acquired record,
The indefinite region search unit
2. The time series information record is further acquired from a record indicating at least one of the specific data value and the specific storage area, and each acquired record is analyzed. The analysis device described. The indefinite region search unit
Specify the storage area range to be analyzed as the analysis target storage area range,
The record of the time series information is acquired further going back from the specific time point, and it is determined whether the storage area indicated in the acquired record is included in the analysis target storage area range, and is indicated in the acquired record. 4. The analysis apparatus according to claim 3, wherein when the storage area included in the analysis target storage area range is included in the analysis target storage area, it is determined whether or not the storage area indicated in the acquired record matches the indefinite area. . An analysis method in which a computer performs an analysis on a program execution device that executes a program using a processor and a memory,
When a failure occurs in the execution of the program of the program execution device, time series information in which information used between the processor and the memory until the failure occurs is shown in time series, the computer A time series information analysis step of analyzing retroactively to a specific time point on the time series, and specifying the storage content at the specific time point for each storage area of the memory,
An undefined area management step in which the computer manages a storage area whose storage content is not specified by analysis by the time-series information analysis step among the storage areas in the memory as an undefined area;
An analysis method comprising: an indefinite area searching step in which the computer analyzes the time-series information further retroactively from the specified time point and specifies the storage contents of the indefinite area at the specified time point. A program that causes a computer to execute analysis for a program execution device that executes a program using a processor and a memory,
When a failure occurs in the execution of the program of the program execution device, the time series information in which the information used between the processor and the memory before the occurrence of the failure is shown in time series A time series information analysis process for analyzing retroactively to a specific point of time, and specifying storage contents at the specific point of time for each storage area of the memory,
An indeterminate area management process for managing as an indeterminate area a storage area whose storage content is not specified by the analysis by the time series information analysis process among the storage areas in the memory;
A program that analyzes the time-series information further from the specific time point and causes a computer to execute an indefinite area search process for specifying the storage contents of the indefinite area at the specific time point.

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