JP2008176731A - Multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow a false sharing to be detected by a simple configuration. <P>SOLUTION: When data to be accessed by a processor is stored in two or more cache memories out of a plurality of first cache memories and a second cache memory provided in common to a plurality of processors, in a multiprocessor system, the first cash memory having un-updated data stored therein is detected when data updated by a write of the processor to the data to be accessed and un-updated data before the write exist, and a detection output is output when it is detected that a write instruction to the data to be accessed has occurred for the first cache memory having the un-updated data stored therein. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multiprocessor system capable of detecting that cache coherency is not maintained with a simple configuration.

  Conventionally, a multiprocessor system in which a program is executed by a plurality of processors may be employed. Generally, in a multiprocessor system, a level 2 (L2) cache memory is shared by each processor, and a level 1 (L1) cache memory is provided in each processor. In this case, it is necessary to maintain data consistency (cache coherency) between the L1 cache memories.

  For example, assume that a processor in a multiprocessor system writes data to memory. In this case, when this data exists in the L1 cache memory inside the processor (cache hit), the contents (old data) of the corresponding line in this L1 cache are updated with this data (new data). Become. On the other hand, when the same data (old data) exists in the L1 cache memory of another processor, it is necessary to invalidate the corresponding line of the L1 cache memory or update it with new data.

As a hardware for guaranteeing such coherency of the cache memory, there is a snoop cache. The snoop cache maintains coherency by monitoring (snooping) access of each processor on the bus, and various methods have been proposed. (For example, Patent Document 1)
When a snoop cache is implemented, in addition to access by a load instruction or store instruction from a normal processor core, the cache memory is accessed to check whether the data at the corresponding address is in the cache from the access on the bus. There is a need to. For this reason, it is necessary to mediate access to the tag portion of the cache memory, or in some cases, to have two ports so that two accesses can be performed simultaneously, increasing the hardware scale.

  By the way, even when a plurality of processors share the same line of each L1 cache, there is actually access to different data in the line (hereinafter referred to as false sharing). When trying to maintain cache coherency, even in such a situation of false sharing, invalidation and updating of caches that are not actually required occur and performance deteriorates. Therefore, it is necessary to prevent false sharing in order to improve performance or to reduce power consumption by eliminating useless operations.

  On the other hand, the snoop cache has a large hardware scale and incurs high costs, so it may not be introduced in an embedded processor. In this case, it is necessary to maintain cache coherency by software. It is necessary to prevent the writing to the same line by false sharing by software.

However, programming to completely eliminate false sharing requires a huge amount of work. Moreover, it is actually extremely difficult to completely eliminate false sharing by software, and a bug occurs in software due to false sharing that cannot be found. This bug is extremely difficult to find and may reduce software productivity.
Japanese Patent Laid-Open No. 10-320283

  It is an object of the present invention to provide a multiprocessor system that can detect the occurrence of false sharing and can easily detect a software bug.

  A multiprocessor system according to one embodiment of the present invention is a multiprocessor system including a plurality of processors, and includes a first cache memory provided corresponding to each of the plurality of processors, and a plurality of the first cache memories. An output unit provided respectively for detecting a state of the first cache memory in response to an access to the first cache memory by the processor and outputting a state signal as a detection result; When the target data is stored in two or more cache memories of the plurality of first cache memories and the second cache memory provided in common to the plurality of processors, the access target Update data and writing by writing of the processor to the data to be When there is unupdated data before inclusion, the first cache memory storing the unupdated data is detected based on the status signal, and the change information as a detection result is held. Based on the change information holding unit, the status signal and the change information, it is detected that a write command for the data to be accessed is generated for the first cache memory in which the unupdated data is stored. In some cases, an error detection means for outputting a detection output is provided.

  According to the present invention, it is possible to detect occurrence of false sharing and to easily detect a software bug.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a multiprocessor system according to an embodiment of the present invention.

  In FIG. 1, the multiprocessor system includes n processors P1 to Pn (hereinafter, representatively referred to as processor P). Each of the processors P1 to Pn includes a processor core C1 to Cn (hereinafter, representatively referred to as the processor core C) that executes instructions and a primary (L1) cache memory M1 to Mn (hereinafter, representative) that stores programs and data. And L1 cache memory MC).

  All the processors P are commonly connected to the secondary (L2) cache memory 11. The L2 cache memory 11 is connected to a bus 12, and a main memory 13 and a peripheral circuit 14 are connected to the bus 12. The main memory 13 stores commands and various data used by the processor P.

  In the L1 cache memory MC and the L2 cache memory 11, writing and reading are managed in line units of a predetermined bit size. As the line size, for example, 32 bytes or 64 bytes can be set.

  The L2 cache memory 11 holds a copy of part of the data stored in the main memory 13. In addition, the L1 cache memory MC holds a copy of a part of the data stored in the L2 cache memory 11 or the main memory 13. The data held in the L1 cache memory MC and the L2 cache memory 11 can be accessed by the processor core C by designating the address of the main memory 13.

  The processor core C performs access by designating the address of the main memory 13 for a load instruction, a store instruction, and the like. In this case, when the data stored in the designated address of the main memory 13 is copied and stored in the L1 cache memory MC (that is, when there is a cache hit), the processor core C performs the L1 cache. Access is made to data (hereinafter referred to as target data) of a line (hereinafter referred to as target line) designated by an address in the memory MC. When the target data is not copied and stored in the L1 cache memory MC (that is, when there is a cache miss), the processor core C accesses the L2 cache memory 11.

  Further, when the processor core C accesses the L2 cache memory 11 and there is target data to be accessed to the L2 cache memory 11 (that is, in the case of an L2 cache hit), the L1 cache memory 11 to the L1 cache A line including target data is refilled in the memory MC. When the target data does not exist in the L2 cache memory 11 (in the case of a cache miss), first, a line including the target data is refilled from the main memory 13 to the L2 cache memory 11, and further, the L2 cache memory 11 The line including the target data is refilled in the memory MC.

  By the way, when data is written from the processor core C, the data held in the L1 and L2 cache memories MC and 11 may be different from the copy source data. Also, data copied from the cache memory 11 to the plurality of L1 cache memories MC may have different contents. In these cases, in order to maintain cache coherency, it is necessary to match the data at the copy source and all the copy destinations with the latest data corresponding to the write at a predetermined timing. Of these data accessed from the processor P by a common address, data that is not the latest is referred to as unupdated data, and the latest data is also referred to as updated data.

  In the present embodiment, a signal for determining whether each L1 cache memory holds unupdated data or updated data is output from each L1 cache memory MC to the L2 cache memory 11. Conventionally, transactions such as refill and write back have occurred between the L1 cache memory MC and the L2 cache memory 11. In the present embodiment, a signal indicating the occurrence of these transactions is further output to the L2 cache memory 11.

  The L2 cache memory 11 holds the received information and detects the presence / absence of false sharing by determining the state of each L1 cache memory MC.

  FIG. 2 is a circuit diagram showing a specific configuration of the L1 cache memory MC in FIG. The example of FIG. 2 shows the configuration of the direct mapped cache, but other cache configurations such as 2-way and 4-way may be employed. In FIG. 2, a write-back cache is assumed, but another method can be adopted.

  The L1 cache memory MC built in each processor P has the same configuration, and has a data storage area 21 for storing transferred data, a tag area 22 for holding address information of the stored data, and a state storage area 23. . The data storage area 21 includes a plurality of lines serving as management units. The example of FIG. 2 shows an example in which one line is configured by 32 bits (4 bytes) × 4 = 16 bytes, and the number of lines is 256, for example.

  The address specified by the processor core C at the time of data access is, for example, a tag, an index, a Bof (block offset), and an invalid bit (00) arranged as shown in FIG. In the direct mapped method, the line number of the L1 cache memory MC can be directly specified by the address (index) of the memory block of the main memory 13. In the example of FIG. 2, any of the 256 lines can be specified by the fourth to eleventh 8-bit ([11: 4]) indexes.

  The high-order bit tag of the address indicates which position in the memory block of the main memory 13 is the data. When the data is stored in the data storage area 21, the tag area 22 stores a tag indicating which position in the memory block the data is.

  Therefore, if the tag in the address specified by the processor core C matches the tag in the tag area 22 of the line specified by the index, a cache hit occurs, and if they do not match, a cache miss occurs. The comparator 25 is given a tag in the address and a tag from the tag area 22, performs this comparison, and outputs the comparison result to the AND circuit 26. Information from the state storage area 23 is also given to the AND circuit 26. In the state storage area 23, a valid bit V indicating whether or not valid data is stored in the line and a dirty bit D indicating that writing by the processor core C has been performed on the line are provided for each line. Hold. The valid bit V indicates that the line is valid by “1”, and the dirty bit D is set to “1” when the line is written. The AND circuit 26 outputs a cache hit only when the valid bit D is “1” and the comparison result of the comparator 25 is “1” indicating coincidence for the line specified by the address ( The hit signal is output to the control circuit 27.

  In addition to the hit signal, the control circuit 27 serving as an output unit is provided with a dirty bit V from the state storage area 23 and also with a cache access write signal (Write) and a read signal (Read). The control circuit 27 asserts the refill signal RD when the output of the AND circuit 26 is “0” (L1 cache miss) for the cache access by the write signal or the read signal. When the L1 cache miss is indicated by the output of the AND circuit 26 and the dirty bit D indicates that the line to be replaced by the refill is dirty, the control circuit 27 indicates the data of the dirty line. Is written back to the L2 cache memory 11 and a write back invalid signal WBI is asserted.

  In the present embodiment, the control circuit 27 not only outputs the refill signal RD and the write back invalid signal WBI to the L2 cache memory in a bus cycle, as in the conventional L1 cache memory, but also the change signal MOD and the invalid signal INV. Is also output.

  Further, the control circuit 27 makes an effective change when the dirty bit D changes from “0” to “1” because the processor core C first writes to the predetermined line of the L1 cache memory MC. The signal MOD is output. In this case, the control circuit 27 also outputs address information for which writing has been performed. The control circuit 27 asserts the invalid signal INV when data other than the target data is replaced by refill for the L1 cache miss. The control circuit 27 supplies a refill signal RD, a write back invalid signal WBI, and a change signal MOD as status signals to the L2 cache memory 11.

  FIG. 3 is a circuit diagram showing a specific configuration of the L2 cache memory 11 in FIG. FIG. 4 is a flowchart for explaining the control of the control circuit 37 in the L2 cache memory 11.

  The configuration of the L2 cache memory 11 is the same as that of the L1 cache memory MC, and includes a data storage area 31 for storing transferred data, a tag area 32 for holding address information of the stored data, and a state storage area 33. The data storage area 31 includes a plurality of lines serving as management units. The selector 34, the comparator 35, and the AND circuit 36 have the same configuration as the selector 24, the comparator 25, and the AND circuit 26 of the L1 cache memory MC, respectively.

  In the present embodiment, there is an update information area 38 that holds information on the update status for each processor P. The update information area 38 stores a mismatch bit IC, a valid bit V, and a change bit M. As for the mismatch bit (IC bit) stored in the update information area 38, the update data is stored in the L1 cache memory MC and the unupdated data is stored in the L2 cache memory 11 in accordance with the valid change signal MOD from the processor P. In the case of a state, it is set to “1”.

  The valid bit (V bit) stored in the update information area 38 indicates the validity or invalidity of the stored data for each processor P. The change bit (M bit) stored in the update information area 38 indicates that unupdated data is stored in a state where the update data is stored in the other L1, L2 cache memories MC, 11. ing.

  IC bits, V bits, and M bits stored in the update information area 38 are generated in the control circuit 37. A refill signal RD, a write back invalid signal WBI, a change signal MOD, and an invalid signal INV are supplied to the control circuit 37 from each processor P. In step S1 of FIG. 4, the control circuit 37 takes in the refill signal RD, the write back invalid signal WBI, the change signal MOD, and the invalid signal INV, generates IC bits based on the fetched signals, and for each processor. V bits and M bits are generated and stored in the update information area 38 of the corresponding cache line. The control circuit 37 and the update information area 38 constitute an error detection unit.

  Table 1 below shows the correspondence between the signal input to the control circuit 37 and each bit generated by the control circuit 37.

[Table 1]

┌─┬─────────┬─────────┬───────────┐
│ │ │ L2 cache │ L2 cache │
│ │ │ Previous state │ New state │
│ │Processor x ├─┬───┬───┼─┬───┬───┬─┤
Input signal from │ │ │Pro │Pro │ │Pro │Pro │ │
│ │ │ │Sessor│ Sessor│ │Sessor│Sessor│F│
│ │ │ │ x │other than x│ │ x │other than x │ │
│ ├─────────┤┤ ────┼───┤ ├───┼───┤ │
│ │RD WBI INV MOD │IC│VM │VM │IC│VM │VM │ │
├─┼─────────┼─┼───┼───┼─┼───┼───┼─┤
│a│ │0│0 0│- -│0│1 0│- -│0│
├─┤1 0 0 0 ├─┼───┼───┼─┼───┼───┼─┤
│b│ │1│0 0│- -│1│1 1│- -│0│
├─┼─────────┼─┼───┼───┼─┼───┼───┼─┤
│c│0 0 1 0 │-│1 -│- -│-│0 0│- -│0│
├─┼─────────┼─┼───┼───┼─┼───┼───┼─┤
│d│0 1 0 0 │1│1 1│- --│0│0 0│- --│0│
├─┼─────────┼─┼───┼───┼─┼───┼───┼─┤
│e│ │0│1 0│0 0│1│1 1│0 0│0│
├─┤ ├─┼───┼───┼─┼───┼───┼─┤
│f│0 0 0 1 │-│1 0│1 --│1│1 1│1 1│0│
├─┤ ├─┼───┼───┼─┼───┼───┼─┤
│g│ │-│1 1│- -│-│1 1│- -│1│
└─┴─────────┴─┴───┴───┴─┴───┴───┴─┘
Table 1 shows that when the refill signal RD, the write back invalid signal WBI, the change signal MOD, and the invalid signal INV are supplied from the L1 cache memory MC to the L2 cache memory 11, they are already stored in the L2 cache memory 11 at the time of supply. This shows a method of updating the IC, V, M, and F bit described later, which are newly stored in the L2 cache memory 11 from the relationship between the set IC, V, M bits and each signal input. Note that “−” indicates that the control circuit 37 does not update or may take any value of “0” or “1”.

  In Table 1, a and b are examples in which the refill signal RD is supplied, the case c is an example in which the write-back invalid signal WBI is supplied, and the case d is an example in which the invalid signal INV is supplied. Cases e to g are examples in which the change signal MOD is supplied.

  Case a is an example in which the refill signal RD is supplied from a predetermined processor x in the processor P when the IC bit of the target line of the L2 cache memory 11 is “0”. When a valid refill signal RD is generated, the V and M bits of the corresponding processor x are cleared to “0” before that. The target data is stored in the L1 cache memory Mx of the processor x by the valid refill signal RD. When a valid refill signal RD is input, the control circuit 37 proceeds from step S2 in FIG. 4 to step S3, and sets the V bit of the corresponding processor.

  Case b is an example in which the refill signal RD is supplied from a predetermined processor x in the processor P when the IC bit of the target line of the L2 cache memory 11 is “1”. Also by this refill signal RD, the target data read from the L2 cache memory 11 is stored in the L1 cache memory Mx of the processor x. However, in this case, the IC bit is “1”, and the target data stored in the L2 cache memory 11 is unupdated data. Therefore, in this case, the control circuit 37 sets the V bit of the corresponding processor in step S3 of FIG. 4 by inputting a valid refill signal RD, and shifts the processing from step S4 of FIG. 4 to step S5. Then, the M bit is also set to “1”.

  Case c is an example in which the invalid signal INV is supplied from a predetermined processor x in the processor P. The invalid signal INV indicates that the target line that has been valid until now becomes invalid. That is, when the invalid signal INV is input, the control circuit 37 proceeds from step S6 to step S7, and changes the V bit from “1” to “0”. The control circuit 37 also clears the M bit to “0”.

  Case d is an example in which the write back invalid signal WBI is supplied from a predetermined processor x in the processor P. When a valid write back invalid signal WBI is generated, update data is stored in the L1 cache memory Mx of the corresponding processor x before that, and unupdated data is stored in the L2 cache memory 11. Become. Therefore, immediately before the write back invalid signal WBI is input, the IC bit of the target line of the L2 cache memory 11 is “1”. Since the update data is stored, the V bit is “1” and the IC bit is “1”, so the M bit is also “1”. When the write-back by the valid write-back invalid signal WBI is performed and other data is written to the target line of the L1 cache memory Mx, the control circuit 37 shifts the processing from step S8 to step S9, IC, Clear all V and M bits to "0".

  Cases e to g are examples in which the change signal MOD is supplied from a predetermined processor x in the processor P, and will be described in three cases according to the state of the previous IC, V, and M bits. Case e is an example in which the V bit of the processor x is “1” and the M bit is “0”, and the V and M bits of the other processors are “0”. The IC bit is “0”. That is, the target data is stored only in the L1 cache memory Mx of the processor x, and the update data is stored in both the L1 and L2 cache memories Mx and 11. In this case, when a valid change signal MOD is input, the control circuit 37 shifts the processing from step S10 to step S11, sets the V and M bits for the processor x to “1”, and sets the IC. The bit is also set to “1”. The values of the V and M bits for other processors remain “0”.

  Case f is an example in which the V bit of the processor x is “1”, the M bit is “0”, and the V bits of the other processors are “1”. That is, in this example, the target data is stored not only in the L1 cache memory Mx of the processor x but also in the L1 cache memory MC other than the processor x. Also in this case, when a valid change signal MOD is input, the control circuit 37 sets the V and M bits for the processor x to “1” and the IC bit to “1”. Further, the M bit of another processor whose V bit is “1” is also set to “1” (step S11).

  That is, when a valid change signal MOD is input, the control circuit 37 refers to the V bit, sets all the M bits of all the processors for which the V bit is set to “1”, and sets the IC bit to “1”. To.

  Further, the case g is an example when a valid change signal MOD is generated from the processor x in which the M bit is set. As described above, if the V bit is set (if valid target data is held), the M bit is set for any processor writing to the L1 cache memory MC. The change signal MOD is generated only by the first writing when the dirty bit D is switched from “0” to “1”. That is, the case g is not an example in which the change signal MOD is generated from the L1 cache memory MC that holds the update data. Therefore, when a valid change signal MOD is generated from the processor x in which the M bit is set, unupdated data is stored in the processor x, and updated data is sent to any processor other than the processor x. Means stored. Therefore, in this case, the control circuit 37 shifts the processing from step S10 to step S12, and sets the F bit indicating the occurrence of false sharing to “1”.

  Note that steps S2 to S5, steps S6 and S7, steps S8 and S9, and steps S10 to S12 are independent of each other, and may be in any order.

  When the F bit indicating the occurrence of false sharing is set, the F register 40 generates an interrupt request signal to the processor, the specific processor, or all the processors that cause the F bit to be set. It has become.

  The FSA register 39 is supplied with an input address. When false sharing occurs, the FSA register 39 outputs the address that caused the occurrence of false sharing.

  Next, the operation of the embodiment configured as described above will be described with reference to the explanatory diagrams of FIGS. 5 to 9 show signals from the L1 cache memory MC in the center, values of the V, M, and IC bits in the update information area 38 on the left side, and the L1 cache memories MC (M0 to M3) and L2 on the right side. Data in the cache memory 11 (L2) is shown. 5 to 9 show that the latest data is retained in the double circle mark than in the circle mark and in the triple circle mark than the double circle mark. In addition, X mark is a state where cache coherency is not maintained, that is, a state where update data is stored in the other L1, L2 cache memories MC, 11 for the same target data, and L1 storing unupdated data. It shows that new writing is performed in the cache memory MC. Further, (a) to (g) in FIGS. 5 to 9 correspond to the cases a to g in Table 1 above.

  FIGS. 5 to 9 show examples having four processors P0 to P3, and description will be made assuming that the L1 cache memories M0 to M3 are built in the processors P0 to P3, respectively. The examples of FIGS. 5 to 9 are examples in which all of the data stored in the L1 cache memory MC is also stored in the L2 cache memory 11 (multilevel inclusion).

  FIG. 5 shows an example in which false sharing does not occur.

  Assume that data (target data) is held only in the L2 cache memory 11 for the target line as shown in the upper right side of FIG. Here, it is assumed that the processor core of the processor P0 accesses the target data. In this case, since the target data is not held in the L1 cache memory M0, the L1 cache memory M0 asserts the refill signal RD and supplies it to the L2 cache memory 11 (corresponding to case a in Table 1 above). .

  As a result, the control circuit 37 of the L2 cache memory 11 sets the V bit of the target line in the update information area 38 to “1” as shown on the left side of FIG. The target data is read from the L2 cache memory 11 and written to the target line of the L1 cache memory M0 as shown on the right side of FIG.

  Next, it is assumed that the processor core of the processor P0 writes to the target data as shown on the right side of FIG. As a result, the target data stored in the L1 cache memory M0 becomes the latest data indicated by double circles in FIG. 5, that is, update data. On the other hand, at this time, the target data stored in the L2 cache memory 11 is unupdated data as indicated by a single circle.

  In response to this write command, the L1 cache memory M0 of the processor P0 asserts the change signal MOD and supplies it to the L2 cache memory 11 (corresponding to e in Table 1 above). As a result, the control circuit 37 of the L2 cache memory 11 sets the M bit and the IC bit to “1” as shown on the left side of FIG.

  Next, it is assumed that the processor core of the processor P0 accesses other data to the line of the L1 cache memory M0 in which the target data is stored. In this case, a cache miss occurs in the L1 cache memory M0, and the L1 cache memory M0 asserts the write-back invalid signal WBI and supplies it to the L2 cache memory 11 (corresponding to d in Table 1 above). As a result, the target data stored in the L2 cache memory 11 becomes update data, and the target data in the L1 cache memory M0 becomes invalid data (right side in FIG. 5). The control circuit 37 of the L2 cache memory 11 clears the V bit, M bit, and IC bit of the target line (left side in FIG. 5).

  Next, an example of a case where cache coherency cannot be maintained by false sharing will be described with reference to FIG.

  Assume that data (target data) is held only in the L2 cache memory 11 for a predetermined line as shown on the right side of the uppermost stage in FIG. Here, as in the example of FIG. 5, it is assumed that the L1 cache memory M0 asserts the refill signal RD. The control circuit 37 of the L2 cache memory 11 sets the V bit of the target line in the update information area 38 to “1” as shown on the left side of FIG. The target data is read from the L2 cache memory 11 and written to the target line of the L1 cache memory M0, as shown on the right side of FIG.

  Next, as shown in the center of FIG. 6, it is assumed that the L1 cache memory M1 asserts the refill signal RD by accessing the processor core of the processor P1. The control circuit 37 of the L2 cache memory 11 sets the V bit of the processor P1 of the target line in the update information area 38 to “1” as shown on the left side of FIG. The target data is read from the L2 cache memory 11 and written to the target line of the L1 cache memory M1, as shown on the right side of FIG.

  Next, as shown on the right side of FIG. 6, it is assumed that the processor core of the processor P0 writes the target data. Thus, the target data stored in the L1 cache memory M0 becomes update data indicated by double circles in FIG. On the other hand, at this time, the target data stored in the L2 cache memory 11 and the L1 cache memory M1 is unupdated data as indicated by a single circle.

  In response to this write command, the L1 cache memory M0 of the processor P0 asserts the change signal MOD and supplies it to the L2 cache memory 11 (corresponding to f in Table 1). As a result, the control circuit 37 of the L2 cache memory 11 sets M bits. In this case, the control circuit 37 sets both M bits of the processors P0 and P1, as shown on the left side of FIG. That is, when a valid change signal MOD is input, the control circuit 37 refers to the V bit and sets the M bit of another processor in which the V bit is set. The IC bit is also set.

  In this state, it is assumed that the processor core of the processor P0 writes the target data in the L1 cache memory M0 again. In this case, the dirty bit D in the L1 cache memory M0 is already “1”, and no valid change signal MOD is generated from the processor P0. Therefore, the content of the update information area 38 of the L2 cache memory 11 does not change.

  Here, as shown in the center of FIG. 6, it is assumed that the processor core of the processor P1 also writes the target data. Then, a valid change signal MOD is supplied from the processor P1 to the control circuit 37 of the L2 cache memory 11 (corresponding to g in Table 1). The control circuit 37 sets the F bit in the F register 40 because the change signal MOD is input from the processor P1 in which the M bit is set. Further, the control circuit 37 causes the FSA register 39 to output the address designated by the processor P1. The F register 40 generates an interrupt request signal for the processor P1.

  Thus, in this embodiment, it is possible to generate an interrupt request signal by detecting that writing is separately performed on the same line between different L1 cache memories MC.

  Next, another example in the case where cache coherency cannot be maintained by false sharing will be described with reference to FIG.

  Now, it is assumed that data (target data) is held only in the L2 cache memory 11 for a predetermined line as shown on the right side of the uppermost stage in FIG. Here, as in the example of FIG. 6, the L1 cache memory M0 and the L1 cache memory M1 sequentially assert the refill signal RD, and then the processor core of the processor P0 writes the target data, thereby causing the L1 cache memory M0. Assume that the change signal MOD is asserted and supplied to the L2 cache memory 11.

  In this state, as shown in the fourth row on the left side of FIG. 7, the V bit and M bit of the processors P0 and P1 are “1”, and the IC bit is also “1”. Further, as shown in the fourth row on the right side of FIG. 7, unupdated data is stored in the cache memories M1 and 11, and updated data is stored in the L1 cache memory M0.

  Next, as shown in the center of FIG. 7, the processor core of the processor P0 accesses another line to the line of the L1 cache memory M0 in which the target data is stored, so that the L1 cache memory M0 Assume that the back invalid signal WBI is asserted and supplied to the L2 cache memory 11 (corresponding to d in FIG. 1). As a result, the target data stored in the L2 cache memory 11 becomes update data, and the target data in the L1 cache memory M0 becomes invalid data (right side of FIG. 7). In addition, the control circuit 37 of the L2 cache memory 11 clears the V bit and M bit of the target line and sets the IC bit to “0” (left side in FIG. 7).

  Here, as shown in the center of FIG. 7, it is assumed that the processor core of the processor P1 also writes the target data. Then, a valid change signal MOD is supplied from the processor P1 to the control circuit 37 of the L2 cache memory 11 (corresponding to g in FIG. 1). The control circuit 37 sets the F bit in the F register 40 because the change signal MOD is input from the processor P1 in which the M bit is set. Further, the control circuit 37 causes the FSA register 39 to output the address designated by the processor P1. The F register 40 generates an interrupt request signal for the processor P1.

  As described above, in this embodiment, when update data exists in the L2 cache memory 11, writing to the L1 cache memory MC holding unupdated data can be detected and an interrupt request signal can be generated. .

  Next, still another example when cache coherency cannot be maintained by false sharing will be described with reference to FIG.

  Now, as shown in the upper right side of FIG. 8, it is assumed that the target data is held only in the L2 cache memory 11 for a predetermined line. Here, the L1 cache memory M0 asserts the refill signal RD, and then the processor core of the processor P0 writes the target data, so that the L1 cache memory M0 asserts the change signal MOD and supplies it to the L2 cache memory 11 It shall be.

  In this state, as shown in the third row on the left side of FIG. 8, the V bit and M bit of the processor P0 are “1”, and the IC bit is also “1”. Further, as shown in the third row on the right side of FIG. 8, unupdated data is stored in the L2 cache memory 11, and updated data is stored in the L1 cache memory M0.

  Next, as shown in the center of FIG. 8, it is assumed that the L1 cache memory M1 asserts the refill signal RD (corresponding to b in Table 1) by accessing the processor core of the processor P1. The target data is read from the L2 cache memory 11 and written to the target line of the L1 cache memory M1, as shown in the fourth row on the right side of FIG. As shown on the left side of FIG. 8, the control circuit 37 of the L2 cache memory 11 sets the V bit of the processor P1 of the target line in the update information area 38 to “1”, and the update data is stored in the other cache memory M0. In this state, the M bit indicating that unupdated data is stored is also set to “1”.

  That is, in this state, as shown in the fourth row on the left side of FIG. 8, the V bit and M bit of the processors P0 and P1 are “1”, and the IC bit is also “1”. As shown in the fourth row on the right side of FIG. 8, unupdated data is stored in the cache memories M1 and 11, and updated data is stored in the L1 cache memory M0.

  Next, as shown in the center of FIG. 8, when the processor core of the processor P0 accesses another line to the line of the L1 cache memory M0 in which the target data is stored, the L1 cache memory M0 Assume that the back invalid signal WBI is asserted and supplied to the L2 cache memory 11 (corresponding to d in FIG. 1). As a result, the target data stored in the L2 cache memory 11 becomes update data, and the target data in the L1 cache memory M0 becomes invalid data (right side in FIG. 8). Further, the control circuit 37 of the L2 cache memory 11 clears the V bit and M bit of the target line, and sets the IC bit to “0” (left side in FIG. 8).

  Here, as shown in the center of FIG. 8, the processor core of the processor P1 also writes to the target data. Then, a valid change signal MOD is supplied from the processor P1 to the control circuit 37 of the L2 cache memory 11 (corresponding to g in FIG. 1). The control circuit 37 sets the F bit in the F register 40 because the change signal MOD is input from the processor P1 in which the M bit is set. Further, the control circuit 37 causes the FSA register 39 to output the address designated by the processor P1. The F register 40 generates an interrupt request signal for the processor P1.

  Thus, in this embodiment, even when unupdated data is read from the L2 cache memory 11, the M bit is set, and the M bit for other processors is cleared by the subsequent write-back processing. However, an interrupt request signal can be generated by detecting writing to the L1 cache memory MC holding unupdated data.

  Next, an example in which cache coherency is maintained by false sharing will be described with reference to FIG.

  Assume that data (target data) is held only in the L2 cache memory 11 for a predetermined line as shown in the upper right side of FIG. Here, as in the example of FIG. 7, the L1 cache memory M0 and the L1 cache memory M1 sequentially assert the refill signal RD, then the L1 cache memory M0 asserts the change signal MOD, and the L1 cache memory M0 further Assume that the write back invalid signal WBI is asserted and supplied to the L2 cache memory 11.

  In this state, as shown in the fifth row on the left side of FIG. 9, only the V bit and M bit of the processor P1 are “1”. Further, as shown in the fifth row on the right side of FIG. 9, the update data is stored in the L2 cache memory 11, and the non-update data is stored in the L1 cache memory M1.

  Here, as shown in the center of FIG. 9, it is assumed that the processor core of the processor P2 accesses the target data. In this case, since the target data is not held in the L1 cache memory M2, the L1 cache memory M2 asserts the refill signal RD and supplies it to the L2 cache memory 11 (corresponding to case a in Table 1).

  As a result, the control circuit 37 of the L2 cache memory 11 sets the V bit of the corresponding processor P2 in the update information area 38 to “1” as shown on the left side of FIG. The target data is read from the L2 cache memory 11 and written to the corresponding line of the L1 cache memory M2, as shown on the right side of FIG. The data read into the L1 cache memory M2 is update data written back by the L1 cache memory M0.

  Next, it is assumed that the processor core of the processor P3 also accesses the target data. As a result, the L1 cache memory M3 asserts the refill signal RD and supplies it to the L2 cache memory 11. As shown on the left side of FIG. 9, the control circuit 37 sets the V bit of the processor P3 to “1”. Also in this case, the data read into the L1 cache memory M3 is update data written back by the L1 cache memory M0 (right side in FIG. 9).

  Next, it is assumed that the processor core of the processor P2 writes the target data as shown in the center of FIG. As a result, the target data stored in the L1 cache memory M2 becomes update data indicated by a triple circle in FIG. Also, in response to this write command, the L1 cache memory M2 of the processor P2 asserts the change signal MOD and supplies it to the L2 cache memory 11 (corresponding to f in Table 1). As a result, the control circuit 37 of the L2 cache memory 11 sets the M bits of the processors P1 to P3 in which the V bit is set and also sets the IC bit, as shown on the left side of FIG.

  Thus, in the example of FIG. 9, cache coherency is maintained and the F bit is not set. Note that when a valid change signal MOD is output from the processor P1 or P3 in the state of the final stage in FIG. 9, the control circuit 37 sets the M bits of these processors P1 and P3. The F bit is set in the register 40.

  As described above, in the present embodiment, the refill signal RD, the write back invalid signal WBI, the change signal MOD, and the invalid signal INV are supplied from the L1 cache memory to the L2 cache memory, and each processor is validated in the L2 cache memory. The (V) bit, the change (M) bit, and the mismatch (IC) bit are stored, and it is determined whether or not to set the F bit according to the state of the M bit at the input time of the valid change signal MOD. As a result, it is possible to automatically detect that writing has occurred from a plurality of processors, that is, false sharing has occurred on a line shared by a plurality of processors. Further, when false sharing is detected, an interrupt request can be generated by setting the F bit, and execution of a program can be stopped to analyze a software fault. Note that the FSA register and the F register can also be read by a load instruction from the processor, and it is possible to easily grasp which address line has been written by a plurality of processors by software. . This facilitates detection of software defects and improves development efficiency.

  Thus, in this embodiment, false sharing can be detected without providing a snoop cache. In the present embodiment, it is possible to configure by simply adding a 2-bit information storage area corresponding to each processor to each line of the L2 cache memory, and the increase in hardware scale is slight. For example, in the case of 4 processors, it is only necessary to add 8 bits. In a cache having a line size of 32 bytes (256 bits) and a tag portion of 22 bits, the hardware increase is only about 2.9%.

  In the present embodiment, the example in which the error detection unit configured by the control circuit and the update information area is built in the L2 cache memory has been described. However, the state detection unit may be provided separately from the L2 cache memory. Is clear.

1 is a block diagram showing a multiprocessor system according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a specific configuration of an L1 cache memory MC in FIG. 1. FIG. 2 is a circuit diagram showing a specific configuration of an L2 cache memory 11 in FIG. 1. FIG. 4 is a flowchart for explaining control of a control circuit 37 in FIG. 3. FIG. Explanatory drawing for demonstrating operation | movement of embodiment. Explanatory drawing for demonstrating operation | movement of embodiment. Explanatory drawing for demonstrating operation | movement of embodiment. Explanatory drawing for demonstrating operation | movement of embodiment. Explanatory drawing for demonstrating operation | movement of embodiment.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 11 ... L2 cache memory, 13 ... Main memory, P1-Pn ... Processor, C1-Cn ... Processor core, M1-Mn ... L1 cache memory.

Claims (5)

In a multiprocessor system composed of a plurality of processors,
A first cache memory provided corresponding to each of the plurality of processors;
Provided in each of the plurality of first cache memories, detects the state of the first cache memory according to the access to the first cache memory by the processor, and outputs a status signal as a detection result An output section;
In a case where data to be accessed by the processor is stored in two or more cache memories of the plurality of first cache memories and the second cache memory provided in common to the plurality of processors. When the update data written by the processor with respect to the data to be accessed and unupdated data before writing exist, the state is determined to be the first cache memory storing the unupdated data. A change information holding unit that detects based on the signal and holds change information that is a detection result;
Based on the status signal and the change information, when it is detected that a write command for the data to be accessed is generated in the first cache memory in which the unupdated data is stored, the detection output An error detection means for outputting The multiprocessor system according to claim 1, wherein the change information holding unit and the error detection unit are built in the second cache memory. The multiprocessor system according to claim 1, wherein the error detection unit generates an interrupt request to the processor as the detection output. The multiprocessor system according to claim 1, wherein when a detection output is output by the error detection unit, a write address of data to be accessed is stored in a register. The status signal includes a change signal indicating that writing was first performed on the target line of the first cache memory and a refill signal indicating a refill request to the target line,
The change information holding unit includes, in addition to the change information, an area for holding valid information indicating that valid data is stored in the plurality of first cache memories for each of the first cache memories. ,
The valid information is set based on the refill signal, and the change information is set corresponding to the first cache memory in which the valid information is set based on the change signal. 2. The multiprocessor system according to 1.

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