JP2008176677A - Memory controller, nonvolatile storage device, and nonvolatile storage system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller capable of taking a power source interruption countermeasure with a simple configuration (inexpensively) without unnecessarily lowering the speed of data writing processing, and to provide a nonvolatile storage device, and a nonvolatile storage system thereof. <P>SOLUTION: An access apparatus includes a power source interruption countermeasure information input means 301 for inputting whether a mechanism, such as a lock mechanism, corresponding to the power source interruption countermeasure in a card exists or not. Before a writing command, the access apparatus notifies the nonvolatile storage device 100 of the necessity of the power source interruption countermeasure. Consequently, changeover is carried out between the performance of data writing by using a first nonvolatile memory control means 303 capable of quickly recording without holding the power source interruption countermeasure or the performance of data writing by using a second nonvolatile memory control means 304 holding the power source interruption countermeasure. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device such as a semiconductor memory card provided with a nonvolatile memory, a memory controller for controlling the nonvolatile memory, and a nonvolatile memory system in which an access device is added as a component to the nonvolatile memory device. .

  The demand for nonvolatile memory devices including a rewritable nonvolatile memory is increasing, especially for semiconductor memory cards. Semiconductor memory cards are more expensive than optical discs and tape media, but due to their advantages such as small size, light weight, earthquake resistance, and ease of handling, they can be used for recording in portable devices such as digital still cameras and mobile phones. The demand for the medium has increased, and recently it has come to be used as a recording medium for professional video recording equipment for broadcasting stations that handle commercial content.

  This semiconductor memory card includes a flash memory as a nonvolatile main memory, and has a memory controller for controlling the flash memory. The memory controller performs read / write control on the flash memory in response to a read / write instruction from an access device such as a digital still camera body.

  Under such circumstances, the nonvolatile semiconductor memory is required to have high recording density and high-speed data recording performance, and at the same time, data protection is required.

  In order to further improve the recording capacity of the flash memory, a flash memory (multi-value flash memory) capable of storing a plurality of bits of data in one memory cell has been developed. According to this, not only the recording density can be increased and the recording capacity can be increased, but also the number of memory cells in the same recording capacity can be reduced, and the cost can be reduced. Hereinafter, a recording method of the multilevel flash memory will be described.

  In general, a nonvolatile semiconductor memory such as a flash memory stores data by injecting electrons into a floating gate (or trap gate) of a memory cell to change a threshold voltage of the memory cell. The threshold voltage of the memory cell increases when electrons are present in the floating gate and decreases when electrons are not present in the floating gate.

  FIG. 19 is a diagram showing the threshold voltage distribution of the memory cell in the quaternary flash memory. The threshold voltage of the memory cell is distributed in any of the regions L0, L1, L2, and L3 according to programmed (data written) data. The regions L0, L1, L2, and L3 correspond to 2-bit data “11”, “10”, “00”, and “01”, respectively.

  Data writing (programming) is performed in each memory cell until the threshold voltage exceeds the verification voltage VV (VV1, VV2, VV3). For example, when logic “10” is written in a memory cell, the program operation is repeated until the threshold voltage of the memory cell exceeds the verification voltage VV1. The threshold voltage of each memory cell is set to one of the regions L0 to L3.

  Data is read by comparing the threshold voltage of the memory cell with the reference voltage VR (VR1, VR2, VR3). When the threshold voltage of the memory cell is lower than the reference voltage VR1, it is determined that the data held in the memory cell is “11”. When the threshold voltage of the memory cell is between the reference voltages VR1 and VR2, it is determined that the data held in the memory cell is “10”. When the threshold voltage of the memory cell is between the reference voltages VR2 and VR3, it is determined that the data held in the memory cell is “00”. When the threshold voltage of the memory cell is higher than the reference voltage VR3, it is determined that the data held in the memory cell is “01”.

  The erase operation of the memory cell is performed by supplying a low voltage to the control gate of the memory cell to be erased, supplying a high voltage to the well region of the memory cell, and releasing electrons accumulated in the floating gate. At this time, the control gate of the memory cell that is not erased is controlled to be in a floating state, for example.

  When multi-value data is recorded in one nonvolatile memory cell, data is written to the nonvolatile memory cell a plurality of times. For example, as shown in FIG. 6, when the regions L0, L1, L2, and L3 correspond to 2-bit data “11”, “10”, “00”, and “01”, respectively, the lower 1 Writing is performed in two stages: writing bit data and writing upper 1-bit data. (Hereinafter, writing after the second stage to the memory cell is referred to as “additional writing”.)

  When the lower 1-bit data is “1”, the area L0 is set. When the lower 1-bit data is “0”, the area L1 is set. Thereafter, in the additional writing of the upper 1-bit data, if the upper 1-bit data is “1”, each area does not change. When the upper 1-bit data is “0”, the area L0 changes to the area L3 or the area L1 to the area L2.

  Here, when power interruption occurs in the process of changing from the region L0 to the region L3, the state of the region L1 or the region L2 may occur. Therefore, if the power supply is interrupted during the additional writing of the upper 1-bit data, the already written lower 1-bit data may be changed into erroneous data in addition to the upper 1-bit data being written.

  The range specified in one write from the access device is not necessarily a set of lower 1-bit data and upper 1-bit data corresponding to the lower 1-bit data.

  Therefore, there is a possibility that data outside the range designated by the access device by one writing may be destroyed by the power interruption during the additional writing of the upper 1-bit data. That is, the contents of written data cannot be protected.

  As a method for avoiding such data destruction in a region not to be written due to power shutdown, the written data is destroyed by controlling the writing method to the memory cell in the nonvolatile multi-valued memory as in Patent Document 1. A method to prevent this has been considered.

In addition, as in Patent Document 2, there has been considered a method for preventing memory destruction by a mechanism that detects power interruption using a sensor or the like when the power is interrupted.
JP 2006-195565 A Japanese Patent No. 1517379

  However, the above prior art has the following problems. That is, in the power shutdown countermeasure described in Patent Document 1, since the power shutdown countermeasure is taken along with the data writing process and the erasing process, the speed of data writing and erasing always decreases. In the power-off countermeasures described, there is a problem that the cost of the sensor and the cost for creating a special mold are required and the cost increases.

  Accordingly, in view of the above problems, the present invention provides a memory controller, a nonvolatile storage device, and a nonvolatile storage system that can take measures against power interruption with a simple configuration (low cost) without unnecessarily reducing the speed of data writing processing. The purpose is to provide.

  In order to achieve the above object, the present invention takes the following technical means. That is, the technical means in the present invention is a memory controller that writes data to a nonvolatile memory and reads data from the nonvolatile memory, and the memory controller includes the memory controller and the nonvolatile memory. A power shutdown countermeasure information input means for inputting information as to whether or not an access device that performs access control of the non-volatile storage device includes a mechanism for power shutdown countermeasures is provided.

  The memory controller preferably further includes a nonvolatile memory control selection unit that selects a control method of the nonvolatile memory based on information set by the power shutdown countermeasure information input unit.

  More preferably, the memory controller further includes first nonvolatile memory control means that does not implement power shutdown measures, and second nonvolatile memory control means that implements power shutdown measures, and the nonvolatile memory control selection The means may select the first nonvolatile memory control means or the second nonvolatile memory control means based on the information set by the power shutoff countermeasure information input means.

  The technical means in the present invention is a non-volatile storage device including a non-volatile memory and a memory controller, and the memory controller controls access to the non-volatile storage device including the memory controller and the non-volatile memory. It is characterized by comprising a power shut-off countermeasure information input means for inputting information as to whether or not the access device that performs the above has a mechanism for power shut-off countermeasures.

  The memory controller preferably further includes a nonvolatile memory control selection unit that selects a control method of the nonvolatile memory based on information set by the power shutdown countermeasure information input unit.

  More preferably, the memory controller further includes first nonvolatile memory control means that does not implement power shutdown measures, and second nonvolatile memory control means that implements power shutdown measures, and the nonvolatile memory control selection The means may select the first nonvolatile memory control means or the second nonvolatile memory control means based on the information set by the power shutoff countermeasure information input means.

  The technical means in the present invention is a non-volatile storage system comprising a non-volatile storage device and an access device for controlling access to the non-volatile storage device. The non-volatile storage device performs the writing of data to the non-volatile memory and the reading of data from the non-volatile memory. And a memory controller provided with a power shutdown measure information input means for inputting information on whether or not a mechanism is provided.

  The memory controller preferably further includes a nonvolatile memory control selection unit that selects a control method of the nonvolatile memory based on information set by the power shutdown countermeasure information input unit.

  The memory controller further includes a first nonvolatile memory control unit that does not implement a power shutdown measure and a second nonvolatile memory control unit that implements a power shutdown procedure, and the nonvolatile memory control selection unit includes: Preferably, the first nonvolatile memory control means or the second nonvolatile memory control means is selected based on the information set by the power shutdown countermeasure information input means.

  Moreover, it is preferable that the mechanism for the power-off countermeasure includes a memory card lock unit that fixes the nonvolatile storage device, and a memory card lock instruction unit.

  More preferably, the memory card lock instructing unit may notify the power shutoff countermeasure information input unit that the lock is valid or invalid.

  According to the present invention, the memory controller implements the power shutdown countermeasure based on the necessity of the power shutdown countermeasure notified to the power shutdown countermeasure information input means from the power shutdown countermeasure mechanism provided in the access device. Therefore, data can be written at high speed when no power-off countermeasure is required, and data protection against power-off is possible when power-off countermeasure is necessary. That is, it is possible to take a power shutdown measure with a simple configuration without unnecessarily reducing the speed of the data writing process.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
(Embodiment 1)
FIG. 1 is an external view of a nonvolatile memory system having a mechanism for locking a nonvolatile memory device according to Embodiment 1 of the present invention. And a random access nonvolatile storage device 100 such as a memory card and an access device 101 which is a host device for writing and reading data to and from the nonvolatile storage device 100. The nonvolatile storage device 100 is used by being attached to a memory card slot 102 for storing the nonvolatile storage device 100 in the access device 101. Further, the nonvolatile storage device 100 stored in the memory card slot 102 is locked by the memory card locking means 104 which is a lid for physically removing the nonvolatile storage device 100 from the access device 101, and the nonvolatile storage is performed until the access device 101 permits it. The user cannot remove the device 100. For this reason, while the memory card lock unit 104 is locked, the nonvolatile storage device 100 is not inadvertently shut down.

  FIG. 3 shows a configuration example of a nonvolatile storage system including the nonvolatile storage device and the access device that accesses the nonvolatile storage device according to the present invention.

  The nonvolatile storage device 100 includes a memory controller 110 and a nonvolatile memory 120. The memory controller 110 includes a host interface unit 111 that exchanges commands and data with the access device 101, and a non-volatile memory control unit that reads / writes data designated by a logical address designated by the access device 101 115. The non-volatile memory control unit 115 is a logical-physical conversion table 112 that is a table for converting a logical address designated by the access device 101 into a physical address in the non-volatile memory 120, and an empty block that manages the usage status in the non-volatile memory 120. It includes a management table 113, a read / write control unit 114 that controls the nonvolatile memory 120, and a power shutdown countermeasure information flag 116 that indicates whether or not the access device 101 has a mechanism for power shutdown.

  The nonvolatile memory 120 is a NAND flash memory. In the present embodiment, the nonvolatile memory 120 includes memory cells capable of recording quaternary data according to the threshold distribution shown in FIG. As shown in FIG. 7, the non-volatile memory 120 includes a plurality of (1024) physical blocks of a predetermined size (256 KB for data storage use + 8 KB for management information storage use), which is the minimum unit of data erasure. As shown in FIG. 8, each physical block includes a plurality (128) of physical pages of a predetermined size (2 KB for data storage use + 64 B for management information storage use), which is the minimum unit for data writing.

  The nonvolatile memory 120 has a two-page configuration (first page and second page). The first page and the second page are a set of physical pages sharing a memory cell, and a set of lower 1 bits of each memory cell is a first page, and a set of upper 1 bits of each memory cell is a second page. Shall. Therefore, if power interruption occurs during data writing to the second page after data writing to the first page, data on both the first page and the second page may be destroyed. A combination of the first page and the second page in the present embodiment is shown in FIG. The first page, physical page 0 (PP0), is paired with the second page, physical page 4 (PP4). Similarly, physical page 1 (PP1) is paired with physical page 5 (PP5), and physical page 2 (PP2) is paired with physical page 8 (PP8).

  The nonvolatile memory 120 includes a management data storage area 121 and a data storage area 122. Data that can be accessed by the user, that is, data that can be written to or read from the nonvolatile memory 120 by specifying a logical address from the access device 101 is recorded in the data storage area 122.

  The management data storage area 121 stores information that the user cannot directly access, that is, information that cannot be accessed from the access device 101 by specifying a logical address. Information that cannot be directly accessed by the user includes a part of address management information and system information.

  FIG. 10 is an operation flow of the nonvolatile storage device 100 when the access device 101 transmits an initialization command to the nonvolatile storage device 100. The initialization command is transmitted when the access device 101 is turned on or when the nonvolatile storage device 100 is mounted.

  When the nonvolatile storage device 100 receives the initialization command, the memory controller 110 initializes hardware such as clearing internal memories such as the logical-physical conversion table 112 and the empty block management table 114 and confirming the connection of the nonvolatile memory 120. Processing is performed (S1001). Thereafter, the read / write control unit 114 acquires address management information and the like stored in the management data storage area 121 of the nonvolatile memory 120 (S1002), and based on the acquired information, the logical-physical conversion table 112 and the free block management are acquired. A table 113 is created (S1003), and the power shutdown information flag 116 is initially set to a state in which no power shutdown measures are taken (S1004) to complete the process.

  Hereinafter, in the nonvolatile memory system shown in FIG. 1, the operation of each part of the nonvolatile memory device 100 according to the present invention will be described with reference to FIG. The non-volatile memory control unit 115 selects a non-volatile memory control method based on the information of the power shut-off countermeasure information input means 301 for inputting the presence / absence of a power shut-off countermeasure mechanism to the access device 101 and the power shut-off countermeasure information flag 116 Non-volatile memory control selection means 302, first non-volatile memory control means 303 that records data at high speed without taking measures against power interruption, and second non-volatile memory control means that records data while taking measures against power interruption 304 is included. When the non-volatile storage device 100 is mounted in the memory card slot 102 of the access device 101 and it becomes necessary to write data from the access device 101 to the non-volatile storage device 100, the memory card lock instructing unit 305 transfers to the memory card locking unit 104. An instruction is issued to lock the nonvolatile storage device so that it is not ejected by a user operation. At the same time, the host interface 111 is notified to the power shutdown countermeasure information input means 301 that the nonvolatile storage device 100 is locked and the power shutdown countermeasure of the access device 101 is effective. The power shutdown information input means 301 changes the power shutdown countermeasure information flag 116 to a state where the power shutdown countermeasure is enabled.

  After the power shutdown measure for the access device 101 becomes effective, the data writing means 306 for writing data to the nonvolatile storage device 100 transmits a write command via the host interface 111.

  FIG. 13 is a diagram showing an operation flow of the nonvolatile memory control selection unit 302. When a write command is received from the data writing means 306, it is acquired from the power shutdown countermeasure information flag 116 whether or not the power shutdown countermeasure is valid (S1301). It is determined whether or not the power shutdown countermeasure information flag indicates validity (S1302), and if valid, the write data received from the data writing means 306 is stored in the nonvolatile memory 120 using the first nonvolatile memory control means 303. Write (S1303), if invalid, write data received from the data write unit 306 is written using the second nonvolatile memory control unit 304 (S1304). In the access device shown in FIG. 1, since the power shutdown measure in the access device is effective, in other words, the power shutdown measure on the nonvolatile storage device 100 side is unnecessary, the first nonvolatile memory control means is used. Write data without taking measures to shut down the power.

  FIG. 11 is an operation flow of the first nonvolatile memory control unit 303 when the data writing unit 306 of the access device 101 transmits a write command and write data to the nonvolatile storage device 100. The host interface unit 111 of the memory controller 110 of the nonvolatile storage device 100 acquires the write start logical address designated by the data writing unit 306 (S1101), and notifies the read / write control unit 114 of it.

  The read / write control unit 114 calculates a write start logical block (block unit, that is, 256 kB unit) from a write start logical address (sector unit, that is, 512 B unit), and uses the logical / physical conversion table 112 to write the write start logical block. The physical block corresponding to is determined.

  An example of the logical-physical conversion table 112 in this embodiment is shown in FIG. In this embodiment, there are a maximum of two physical blocks corresponding to the logical block, one block for which writing has been completed (write completion block) and one block for which writing is in progress (block for writing). In addition, a block in the middle of writing can be assigned to a maximum of three logical blocks.

  In FIG. 14, the physical block corresponding to logical block 0 (LB0) is one write completion block (PB202). There are two physical blocks corresponding to the logical block 1 (LB1), one complete block (PB358) and one in-write block (PB38). The physical block corresponding to the logical block 2 (LB2) has not been allocated yet and is zero.

  When there is a writing intermediate block corresponding to the writing start logical block, the reading / writing control unit 114 sets this as a writing physical block. If it does not exist, an empty physical block is acquired using the empty block management table 113 and is set as a writing physical block (S1102).

  FIG. 15 shows an empty block management table 113 in the present embodiment. Information about whether each physical block is “free” or “in use” is held.

  When an empty physical block is used as a writing physical block, the writing physical block is registered as a writing intermediate block in the logical-physical conversion table 112. Further, the address management information stored in the management data storage area 121 is updated in order to record in the nonvolatile memory 120 that the vacant block has been allocated as a writing intermediate block.

  Next, the read / write control unit 114 writes the write data received from the data writing unit 306 to the write physical block in the unwritten physical page in ascending order of the physical page number (S1103), and all the write physical blocks are written. It is determined whether or not writing has been completed on the current page (S1104). If completed, the process proceeds to S1102, and if not completed, the process proceeds to S1103. At this time, writing is performed to both the first page and the second page of the physical block for writing. (Hereinafter referred to as quaternary mode writing). In the 4-level mode writing, when the power interruption occurs during the writing, the written data other than the page being written may be destroyed. However, the nonvolatile storage device 100 has a memory card lock provided in the access device 101. Since it is locked by the means 104, the power is not shut off. Thereafter, the processing is repeated from acquisition of the next writing physical block (S1102).

  As described above, in the present embodiment, when the write data from the access device 101 is recorded, one-step writing by “four-value mode writing” is performed. When power is cut off in the non-volatile storage device, there is a possibility that written data may be destroyed, but data is not destroyed because it is protected from power interruption by the access device. Compared to the second nonvolatile memory control unit 304 described later, since the writing process is performed in one stage, it can be recorded in the memory at a high speed.

(Embodiment 2)
FIG. 2 shows an access device 101 that does not have a mechanism for locking the nonvolatile memory device 100 according to one embodiment of the present invention. In FIG. 2, the same components as those in FIG.

  There is no memory card lock means for physically removing the nonvolatile storage device 100 stored in the memory card slot 102 from the access device 101, and the access device 101 can easily connect the nonvolatile storage device 100 during data writing. Therefore, the nonvolatile memory device 100 cannot know when the power is cut off.

  Hereinafter, the operation of each unit of the nonvolatile memory device 100 according to the present invention in the access device 101 will be described with reference to FIG. In FIG. 5, the same components as those in FIG.

  Data writing for writing data to the nonvolatile storage device 100 when the nonvolatile storage device 100 is mounted in the memory card slot 102 of the access device 101 and data needs to be written from the access device 101 to the nonvolatile storage device 100 The means 306 transmits a write command via the host interface 111. In the operation flow of FIG. 13, the nonvolatile memory control selection unit 302 remains in the initial state when the power shutdown countermeasure information flag 116 is read (S1301), so the flag is in an invalid state. In this case, in step S1302 for determining whether there is a countermeasure for power shutdown, the second nonvolatile memory control unit 304 is used to instruct the nonvolatile memory 120 to record the write data received from the data writing unit 306. (S1304).

  FIG. 12 is an operation flow of the first nonvolatile memory control unit 303 when the data writing unit 306 of the access device 101 transmits a write command and write data to the nonvolatile storage device 100.

  The host interface unit 111 of the memory controller 110 of the nonvolatile storage device 100 acquires the write start logical address designated by the data writing unit 306 (S1201) and notifies the read / write control unit 114 of it.

  The read / write control unit 114 calculates a write start logical block (block unit, that is, 256 kB unit) from a write start logical address (sector unit, that is, 512 B unit), and uses the logical / physical conversion table 112 to write the write start logical block. The physical block corresponding to is determined.

  An example of the logical-physical conversion table 112 in this embodiment is shown in FIG. In this embodiment, there are a maximum of two physical blocks corresponding to the logical block, one block for which writing has been completed (write completion block) and one block for which writing is in progress (block for writing). In addition, a block in the middle of writing can be assigned to a maximum of three logical blocks.

  In FIG. 14, the physical block corresponding to logical block 0 (LB0) is one write completion block (PB202). There are two physical blocks corresponding to the logical block 1 (LB1), one complete block (PB358) and one in-write block (PB38). The physical block corresponding to the logical block 2 (LB2) has not been allocated yet and is zero.

  When there is a writing intermediate block corresponding to the writing start logical block, the reading / writing control unit 114 sets this as a writing physical block. If it does not exist, an empty physical block is acquired using the empty block management table 113 and is set as a writing physical block (S1202). FIG. 15 shows the free block management table 113 in this embodiment. Information about whether each physical block is “free” or “in use” is held.

  When an empty physical block is used as a writing physical block, the writing physical block is registered as a writing intermediate block in the logical-physical conversion table 112. Further, the address management information stored in the management data storage area 121 is updated in order to record in the nonvolatile memory 120 that the vacant block has been allocated as a writing intermediate block. If the number of blocks that are being written exceeds the number that can be registered (three), the registration is performed after completing the writing of an arbitrary writing block by performing an aggregation process described later.

  Next, the read / write control unit 114 writes the write data received from the data writing unit 306 into the unwritten physical page in ascending order of the physical page number in the write physical block (S1203). At this time, writing is performed only on the first page of the physical block for writing, and writing is not performed on the second page (hereinafter referred to as binary mode writing). Binary mode programming is a conventional programming method that uses quaternary memory cells like binary memory cells. Since data is written only to the first page, even if the power is cut off during writing, written data other than the page being written is not destroyed.

  Next, the read / write control unit 114 confirms whether there is unwritten data received from the data writing unit 306 (S1204). If there is no unwritten data, the writing process is terminated.

  If unwritten data remains, it is checked whether or not writing has been completed on all the first pages of the writing physical block (S1205).

  FIG. 16 shows a state example of the physical block for writing after the binary mode writing is performed. In FIG. 16, hatched pages represent written pages. In the present embodiment, it is assumed that logical page (LP) information of data stored in each physical page is also stored in the physical page. FIG. 16A shows a state in which writing has been completed on all the first pages of the physical block for writing, and FIG. 16B shows a state in which the unwritten first page remains.

  If the unwritten first page remains in the writing physical block, the binary mode writing is subsequently performed (S1203).

  When writing to all the first pages of the writing physical block is completed, the area is determined based on the number of the logical block in which writing has been performed (S1206), and the aggregation processing method is determined.

  Aggregation processing is processing in which only valid data out of data stored in two physical blocks corresponding to a logical block is aggregated and written into one physical block, and the two blocks before aggregation are made free blocks. . Here, valid data means the latest data written to the logical address.

  When multiple pieces of data of the same logical page exist in the physical block before aggregation, valid data can be uniquely determined by the following rule. In other words, there are two rules: (Rule 1) data in the physical block for writing is newer than the write completion block, and (Rule 2) data having a larger physical page number in the physical block for writing is new.

  In this embodiment, if it is logical block 0 (LB0), it is determined that the management information of the FAT file system is recorded, and the “binary mode aggregation” process shown below is performed (S1207). If the logical block is other than that, the following “multi-value mode aggregation” processing is performed (S1208).

  Binary mode aggregation is an aggregation method in which writing to an aggregation destination physical block is performed by binary mode writing. FIG. 17 shows an example of aggregation by binary mode aggregation. Valid data of the write completion block and write physical block of the aggregation source are aggregated into one physical block by binary mode writing.

  Multilevel mode aggregation is an aggregation method in which writing to a physical block that is an aggregation destination is performed by multilevel mode writing. Here, the multi-value mode writing is a writing method for writing to all physical pages (both the first page and the second page). FIG. 18 shows an example of aggregation by multi-value mode aggregation. Valid data of the write completion block and the write physical block of the aggregation source are aggregated into one physical block by multi-value mode writing.

  After each aggregation process, the two physical blocks of the aggregation source are updated from “in use” to “free” in the empty block management table 113, and the physical block of the aggregation destination is updated from “free” to “in use”. . Further, in the logical-physical conversion table 112, the physical block of the aggregation completion write completion block is updated to the aggregation destination physical block, and the aggregation source write intermediate block is updated to “unallocated”. Also, the address management information stored in the management data storage area 121 is updated in order to record the change in physical block allocation due to the aggregation processing in the nonvolatile memory 120 (S1209). Thereafter, the processing is repeated from the acquisition of the next writing physical block (S1202).

  If a power interruption occurs during writing in the aggregation processing, the address management information read from the management data storage area 121 in the processing of S1002 at the next initialization becomes the state before the aggregation processing, and the aggregation destination The physical block is “free”. Since the aggregation process is a process for copying valid data, the written data is not destroyed even if the state returns to the state before the aggregation process.

  As described above, in the present embodiment, when the write data from the access device 101 is recorded, two-stage writing is performed by “binary mode writing” and “aggregation processing”. Since the former writing is always performed on a memory cell in which written data is not stored, the written data is not destroyed by power-off. Since the latter writing is a process of copying the written data in the nonvolatile multi-level memory to another location, even if the power is shut down due to the removal of the nonvolatile storage device 100 from the access device 101, etc. By making the data valid, the written data is not destroyed.

It should be noted that implementation changes can be made without departing from the spirit of the present invention. The following cases are also included in the present invention.
(1) In the first embodiment, the example shown in FIG. 1 will be described using the memory card locking means 104, that is, a mechanism for covering the memory card slot in order to prevent the nonvolatile storage device from being ejected from the access device. However, the present invention can also be applied to a method in which a notch or the like is provided in the nonvolatile memory device and locking is performed using the notch.
(2) In the example shown in FIG. 1, a memory card is taken as an example of the nonvolatile storage device 100, but the present invention can also be applied to a nonvolatile storage device such as a magnetic disk device, a magneto-optical disk device, or a hard disk device.
(3) In FIG. 3, the case where the nonvolatile memory control unit 115 is provided with a flag for storing information related to the power shutdown measure of the access device 101 has been described. However, before the write command, the access device 101 It can also be applied when going to obtain power shutdown countermeasure information.

A memory controller, a nonvolatile storage device, and a nonvolatile storage system according to the present invention include:
It can take measures against power interruption with a simple configuration without unnecessarily reducing the speed of data writing processing. Portable AV equipment such as still image recording / playback devices and video recording / playback devices, or portable communications such as mobile phones It can be widely used as a recording medium for equipment.

1 is an external view of a nonvolatile memory system having a mechanism for locking a nonvolatile memory device in Embodiment 1 of the present invention. External view of a non-volatile storage system having no mechanism for locking a non-volatile storage device in Embodiment 2 of the present invention Block diagram showing the configuration of a nonvolatile storage system 1 is a block diagram showing a nonvolatile memory device according to a first embodiment of the present invention. The block diagram which shows the non-volatile memory device in Embodiment 2 of this invention The figure which shows the threshold voltage of data and the distribution of the number of cells in a non-volatile memory The figure which shows the structure by the physical block of the non-volatile memory Diagram showing the configuration of physical blocks by physical pages Table showing a list of physical pages allocated to the first and second pages of the physical block and combinations thereof The flowchart which shows the operation | movement flow after the initialization command reception of the non-volatile memory device 100 A flowchart showing an operation flow after the write command is received by the first nonvolatile memory control means 304. A flowchart showing an operation flow after the write command is received by the second nonvolatile memory control means 304. The flowchart which shows the operation | movement flow after write command reception in the non-volatile memory control selection means 302 The figure which shows the structure of the logical-physical conversion table 112 The figure which shows the structure of the empty block management table 113. (A) is a diagram showing a state example of a physical block for writing after writing in binary mode (writing is completed on all first pages), and (B) is a state example of a physical block for writing after writing in binary mode (not yet completed) Figure showing the first page of writing) The figure which shows the example of a state of the physical block before and behind aggregation in binary mode aggregation. The figure which shows the example of a state of the physical block before and behind aggregation in multi-value mode aggregation

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Nonvolatile memory | storage device 101 Access apparatus 102 Memory card slot 104 Memory card lock means 110 Memory controller 111 Host interface part 112 Logical-physical conversion table 113 Empty block management table 114 Read / write control part 115 Non-volatile memory control part 116 Power supply interruption countermeasure Information flag 120 Non-volatile memory 121 Management data storage area 122 Data storage area 301 Power shutdown countermeasure information input means 302 Non-volatile memory control selection means 303 First non-volatile memory control means 304 Second non-volatile memory control means 305 Memory card Lock instruction means 306 Data writing means

Claims (9)

A memory controller for writing data to a nonvolatile memory and reading data from the nonvolatile memory,
A power shutdown measure information input means for inputting information on whether or not an access device for controlling access to the nonvolatile storage device including the memory controller and the nonvolatile memory has a mechanism for power shutdown measures; A memory controller characterized by that. The memory controller is
2. The memory controller according to claim 1, further comprising nonvolatile memory control selection means for selecting a control method for the nonvolatile memory based on information set by the power shutdown countermeasure information input means. The memory controller is
A first non-volatile memory control means that does not implement power-off measures; and a second non-volatile memory control means that implements power-off measures;
The nonvolatile memory control selection means is
3. The memory controller according to claim 2, wherein the first nonvolatile memory control means or the second nonvolatile memory control means is selected based on information set by the power shutdown measure information input means.   A non-volatile memory device comprising: a non-volatile memory; and the memory controller according to claim 1. A nonvolatile storage system comprising a nonvolatile storage device and an access device that controls access to the nonvolatile storage device,
The access device comprises a mechanism for power shutdown measures,
The nonvolatile memory device is
Non-volatile memory;
Power shutdown countermeasure information input for writing data to the nonvolatile memory and reading data from the nonvolatile memory and inputting information on whether the access device has a mechanism for power shutdown countermeasures A non-volatile storage system comprising: a memory controller comprising: a memory controller; The memory controller is
6. The nonvolatile memory system according to claim 5, further comprising nonvolatile memory control selection means for selecting a control method of the nonvolatile memory based on information set by the power shutdown countermeasure information input means. The memory controller is
A first non-volatile memory control means that does not implement power-off measures; and a second non-volatile memory control means that implements power-off measures;
The nonvolatile memory control selection means is
7. The nonvolatile memory system according to claim 6, wherein the first nonvolatile memory control means or the second nonvolatile memory control means is selected based on information set by the power shutdown countermeasure information input means. . The mechanism for the power shutdown measure is:
Memory card locking means for fixing the nonvolatile storage device;
The nonvolatile memory device system according to claim 5, further comprising a memory card lock instruction unit. The memory card lock instruction means
9. The non-volatile storage device according to claim 8, wherein the power shutdown measure information input means is notified that the lock is valid or invalid.

Images