JP2008172249A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To relax a phase absolute value control accuracy in a mask having a groove shifter structure. <P>SOLUTION: Transfer regions 4C, 4D formed on different planar positions on the same surface of an identical mask 2 are multiply exposed by scanning exposure. In the transfer regions 4C, 4D, the same mask pattern is formed, however, the arrangement of a groove shifter 2d of one is opposite to that of the other. Due to the multiple exposure, the light intensity of the respective patterns is the same even if the phase absolute value in the mask varies, thereby improving the dimensional accuracy of the transferred pattern. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a lithography technique using a phase shift mask in exposure processing.

  For example, in Japanese Patent Laid-Open No. 6-83032 (Patent Document 1), a shifter portion composed of a film in a mask using a resist for electron beam drawing or a silicon oxide film as a phase shifter material of a phase shift mask. As a means to solve this problem, attenuation of exposure light due to the light transmittance of the light is overlapped by exposing the same mask pattern of each of two physically separated masks at the shifter section. A technique for reducing the attenuation of exposure light is disclosed.

  Japanese Patent Application Laid-Open No. 11-233429 (Patent Document 2) discloses an exposure technique in which multiple exposure is performed by changing exposure conditions in accordance with the properties of a pattern to be exposed.

  Japanese Patent Laid-Open No. 11-111601 (Patent Document 3) discloses that if two masks are used in the multiple exposure process, the mask needs to be replaced during the exposure process, and the throughput of the exposure process is reduced. In order to solve problems such as an increase in manufacturing cost, super-resolution double scan exposure in which the same mask pattern is provided at different plane positions of one mask and the mask pattern is subjected to multiple exposure by a scanning exposure process. There is disclosure about technology.

  Japanese Patent Laid-Open No. 5-197126 (Patent Document 4) discloses multiple exposure by arranging shifter patterns intersecting each other at different plane positions on the same mask substrate, and exposing the shifter patterns intersecting each other by a half pitch. However, there has been disclosed an exposure technique for transferring a pattern to the intersecting region.

  Japanese Patent Application Laid-Open No. 10-12543 (Patent Document 5) discloses a double exposure technique in which multiple shifters are exposed by shifting half-pitch shift patterns that cross each other, and the pattern is transferred to the intersecting region. .

Furthermore, Japanese Patent Application Laid-Open No. 11-143085 (Patent Document 6) discloses a multiple exposure technique in which multiple exposure using two light beams and normal light is performed, and a pattern is transferred to the intersection area.
JP-A-6-83032 Japanese Patent Laid-Open No. 11-233429 JP-A-11-111601 JP-A-5-197126 Japanese Patent Laid-Open No. 10-12543 JP 11-143085 A

  In the manufacture of a semiconductor integrated circuit device, a lithography technique is used as a method for transferring a fine pattern onto a semiconductor wafer. In the lithography technique, a projection exposure apparatus is mainly used, and an integrated circuit pattern is formed by transferring a photomask pattern mounted on the projection exposure apparatus onto a semiconductor wafer.

  This projection exposure apparatus includes a stepper that transfers a photomask pattern in a step-and-repeat manner, and a scanner that scans a photomask and a semiconductor wafer in opposite directions and continuously transfers slit-like exposure areas. There is. The biggest difference between a stepper and a scanner is that a stepper transfers the pattern using the entire surface of the projection lens, whereas a scanner transfers the pattern using only the slit-shaped part extending in the diameter direction of the projection lens. It is.

  Incidentally, the miniaturization of the pattern constituting the semiconductor integrated circuit device is achieved by improving the performance of the reduction projection exposure apparatus mainly used in the lithography process in the manufacturing process of the semiconductor integrated circuit device. However, in order to further improve the fine processability of the pattern, it is necessary to increase the numerical aperture NA of the reduction projection exposure apparatus. In particular, in order to obtain high resolution in a fine hole pattern arranged at high density, it is necessary to shorten the wavelength of exposure light and increase the NA, but this requires enormous capital investment, and semiconductor integrated circuits As the level of microfabrication of equipment accelerates year by year, it is not realistic to make new capital investments without ending depreciation of semiconductor manufacturing equipment. Therefore, in recent years, in the lithography technique, application of a photomask including phase information of light transmitted through a photomask such as a phase shift mask has been advanced. Phase shift mask technology is a technology that improves the resolution and depth of focus by manipulating the phase of light that has passed through a photomask (including a reticle). For example, a phase shifter is placed in one of the light transmission regions adjacent to each other. There is a Levenson type phase shift mask technique for reversing the phases of light transmitted through both light transmission regions.

  The groove shifter is formed by forming a recess in a transparent film or a transparent mask substrate below the light shielding film on the mask. For example, a phase shifter is formed by digging a transparent film or transparent mask substrate exposed from one of the light transmission patterns adjacent to each other in the mask so that the phase of the light transmitted through the adjacent light transmission pattern is inverted by 180 degrees. ing.

  However, the present inventor has found that the phase shift mask technology having the groove shifter structure has the following problems.

  That is, the first is that high precision is required for the control of the phase difference as the pattern becomes finer. For example, when the KrF excimer laser beam is used as the exposure light, the depth of the groove shifter is about 245 nm. If the required allowable amount of phase error is 2 degrees, the accuracy of about ± 3 nm is required for the digging amount of the mask substrate. Since the mask substrate is made of a glass substrate such as quartz and the digging depth cannot be adjusted by temperature control or the like, digging in that range (accuracy) is extremely difficult by the dry etching process for digging the groove. Therefore, in the phase shift mask having the groove shifter structure, the absolute value control of the phase is a big problem.

  Second, the phase shift mask has a problem that the dimensional accuracy of the transfer pattern is lowered due to the mask structure for providing the phase difference. For example, in the groove shifter structure, the amount of transmitted light is reduced due to the influence of the side surface of the mask digging portion. As a result, the light transmitted through the location where the groove shifter is arranged and the location where the adjacent groove shifter is not arranged Due to this, a difference occurs in the size of each pattern transferred. Therefore, the transparent film or the transparent mask substrate is overhanged in the groove width direction in the groove shifter portion, and the end portion of the light-shielding pattern protrudes in a groove shape in the groove shifter portion (fine groove groove shifter structure). However, with the miniaturization of the transfer pattern, there is a problem that the dimensional difference of the transfer pattern cannot be eliminated even as a fine saddle groove shifter.

  Third, it is difficult to manufacture a mask due to the high-precision absolute value control of the phase and the formation of a fine saddle groove shifter. Further, with the miniaturization of the transfer pattern, high accuracy is required for mask defect inspection and correction. As a result, the mask manufacturing yield is a problem.

  An object of the present invention is to provide a technique capable of relaxing the absolute value control accuracy of a phase in a mask having a groove shifter structure.

  Another object of the present invention is to provide a technique capable of improving the dimensional accuracy of a pattern transferred using a mask having a groove shifter structure.

  Another object of the present invention is to provide a technique capable of reducing the detection size of inspection of a mask having a groove shifter structure.

  Another object of the present invention is to provide a technique capable of improving the ease of manufacturing a mask having a groove shifter structure.

  Another object of the present invention is to provide a technique capable of improving the yield of a mask having a groove shifter structure.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, according to the present invention, when a transfer area formed on a mask is exposed on a wafer by an exposure process, the same transfer pattern of the wafer has the same mask pattern on the mask and is overlapped. The method includes a step of transferring a predetermined integrated circuit pattern onto the wafer by exposing a plurality of different transfer regions in which the arrangement of the groove shifters is opposite to each other.

  The present invention also includes a step of reducing projection exposure of the first phase shift mask pattern including the substrate groove shifter to the first region of the first main surface of the wafer with ultraviolet light, and the first step of the wafer. A second phase shift mask pattern including a substrate groove shifter and having the phase of the first phase shift mask pattern inverted with respect to the first region of one main surface is reduced and projected with ultraviolet light. It has the process to expose.

  The present invention also includes a step of subjecting the first region of the first main surface of the wafer to reduced projection exposure with ultraviolet light to a first phase shift mask pattern including a thin film groove shifter on a substrate, and the wafer. A second phase shift mask pattern including an on-substrate thin film groove shifter with respect to the first region of the first main surface, wherein the phase of the first phase shift mask pattern is reversed. And reduction projection exposure with ultraviolet light.

  According to another aspect of the present invention, there is provided a step of subjecting the first region of the first main surface of the wafer to reduced projection exposure of the first phase shift mask pattern with ultraviolet light, and the first main surface of the wafer. A second phase shift mask pattern formed on the same main surface on the same mask substrate as the first phase shift mask pattern with respect to the first region, wherein the first phase shift The method includes a step of performing reduced projection exposure using ultraviolet light on the mask pattern having a reversed phase.

  According to another aspect of the present invention, there is provided a step of subjecting the first region of the first main surface of the wafer to reduction projection exposure of the first phase shift mask pattern including the fine groove-shaped groove shifter with ultraviolet light, A second phase shift mask pattern including a fine saddle-shaped groove shifter and having the phase of the first phase shift mask pattern inverted with respect to the first region of the first main surface is ultraviolet. And reducing projection exposure with light.

  The present invention also includes a step of reducing and projecting a first phase shift mask pattern with ultraviolet light onto the first region of the first main surface of the wafer, and the first main surface of the wafer. Reducing projection exposure with ultraviolet light of the first region of the second phase shift mask pattern having the phase of the first phase shift mask pattern reversed; and The step of exposing the first phase shift mask pattern to the first region of the first main surface by reduced projection again with ultraviolet light, and the first region of the first main surface of the wafer. And a step of subjecting the second phase shift mask pattern to reduced projection exposure with ultraviolet light again for the region.

  In the present invention, the second phase shift mask pattern is formed on the same main surface on the same mask substrate as the first phase shift mask pattern.

  In the present invention, the exposure in the steps (c) and (d) is performed by scanning exposure.

  In the present invention, the first and second phase shift mask patterns are based on the Levenson method.

  In the present invention, the mask pattern by the Levenson method is for transferring a line and space pattern.

  In the present invention, the mask pattern by the Levenson method is for transferring a plurality of hole patterns.

  The present invention also includes a step of subjecting the first region of the first main surface of the wafer to reduced projection exposure with ultraviolet light to a first phase shift mask pattern including an auxiliary pattern, and the first of the wafer. A second phase shift mask pattern including an auxiliary pattern, which is obtained by inverting the phase of the first phase shift mask pattern, is subjected to reduced projection exposure with ultraviolet light with respect to the first region of the main surface of It has a process.

  The present invention also scans the first region of the first main surface of the wafer by reducing and projecting a first phase shift mask pattern including a groove shifter using ultraviolet light as exposure light. And a phase of the first phase shift mask pattern including a groove shifter with respect to the first region of the first main surface of the wafer. And a step of performing scanning exposure by reducing and projecting the inverted one using ultraviolet light as exposure light.

  According to another aspect of the present invention, a scanning exposure process is performed by reducing and projecting the first phase shift mask pattern using ultraviolet light as exposure light on the first region of the first main surface of the wafer. And a second phase shift mask pattern that is the phase of the first phase shift mask pattern inverted with respect to the first region of the first main surface of the wafer. Scanning exposure by reducing projection using the exposure light as exposure light.

  Furthermore, the outline of another representative one of the inventions disclosed in the present application will be briefly described as follows.

  1. The present invention includes a step of transferring a predetermined integrated circuit pattern onto a wafer by exposing a plurality of transfer regions arranged at different planar positions on the same surface of the same mask to the same region of the wafer. A plurality of transfer regions in which the same mask pattern is disposed in the overlay exposure, and the groove shifters are disposed so that the phases of the light transmitted through the same plane position when the overlay are reversed are mutually reversed. Are overexposed.

  2. The present invention transfers a predetermined integrated circuit pattern onto a wafer by performing scanning exposure by superimposing a plurality of transfer regions arranged at different plane positions on the same surface of the same mask on the same region of the wafer. A plurality of groove shifters arranged in such a manner that the same mask pattern is arranged at the time of the superposition exposure, and the phases of the light transmitted through the same plane position are superposed at the time of superposition. The transfer area is over-exposed.

  3. The present invention transfers a predetermined integrated circuit pattern onto a wafer by performing scanning exposure by superimposing a plurality of transfer regions arranged at different plane positions on the same surface of the same mask on the same region of the wafer. A plurality of groove shifters arranged in such a manner that the same mask pattern is arranged at the time of the superposition exposure, and the phases of the light transmitted through the same plane position are superposed at the time of superposition. The method includes a step of performing overexposure of the transfer area, and a plurality of transfer areas to be overlapped in the overexposure are arranged in a mask along the scanning direction of the exposure area of the scanning exposure.

  4). The present invention includes a step of transferring a predetermined integrated circuit pattern onto a wafer by exposing a plurality of transfer regions arranged at different planar positions on the same surface of the same mask to the same region of the wafer. A plurality of transfer regions in which the same mask pattern is disposed in the overlay exposure, and the groove shifters are disposed so that the phases of the light transmitted through the same plane position when the overlay are reversed are mutually reversed. The mask pattern is a main light transmission pattern transferred to the wafer and a light transmission pattern arranged in the vicinity thereof, and is formed with dimensions that are not transferred onto the wafer. So that the phase of the light transmitted through the main light transmission pattern and the auxiliary mask pattern is reversed in each of the transfer regions to be overlapped with each other. It is intended to place the shifter.

  5. In the present invention, the groove shifter according to any one of Items 1 to 4 includes a substrate groove shifter formed by a groove dug in the mask substrate itself constituting the mask.

  6). According to the present invention, the groove shifter according to any one of Items 1 to 4 is dug so that a surface of the mask substrate is exposed to a shifter film interposed between the mask substrate constituting the mask and the light shielding pattern. It consists of a thin film groove shifter formed by the groove formed.

  7. The present invention provides the groove shifter according to any one of Items 1 to 4, wherein the groove constituting the groove shifts into a position below the end of the light shielding pattern and the end of the light shielding pattern projects. It will be.

  8). According to the present invention, the length of the fine groove-shaped groove shifter according to Item 7 is set to 70% or less of the wavelength of exposure light.

  9. According to the present invention, the length of the fine groove-shaped groove shifter according to Item 7 is set to 40% or less of the wavelength of the exposure light.

  10. According to the present invention, in each of the plurality of transfer regions according to any one of Items 1 to 9, the mask pattern has a plurality of light transmission patterns adjacent to each other in parallel, and any of the light transmission patterns adjacent to each other. A groove shifter is arranged on either side.

  11. According to the present invention, the manufacturing process of the mask according to any one of Items 1 to 10 includes: (a) forming a resist pattern for groove formation on the mask substrate on which the light shielding pattern and the light transmission pattern are formed; b) using the resist pattern as a mask to form a groove shifter in a mask exposed therefrom, and (c) removing the resist pattern and then inspecting the phase.

  12 According to the present invention, in the step of forming a mask groove shifter according to any one of items 1 to 11, (a) a resist pattern for groove formation is formed on a mask substrate on which a light shielding pattern and a light transmission pattern are formed. (B) a step of digging a groove in the mask exposed from the resist pattern as a mask to form a groove shifter, (c) a step of inspecting the phase after removing the resist pattern, (d) the step (c) It has the process of etching away the surface of a mask by performing an isotropic wet etching process with respect to a mask after a process.

  The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.

  (1) According to the present invention, the pattern having the same pattern on the mask, but the pattern in which the phase of the transmitted light is inverted is superimposed and exposed on the same area of the wafer, so that the absolute phase of the mask is obtained in the mask having the groove shifter structure. The value control accuracy can be relaxed.

  (2) According to the present invention, the same pattern of the mask, but the pattern in which the phase of the transmitted light is reversed is superimposed and exposed on the same area of the wafer, and transferred using the mask having the groove shifter structure. It is possible to improve the dimensional accuracy of the formed pattern.

  (3) According to the present invention, it is possible to relax the defect detection size in the inspection of the mask having the groove shifter structure by overlaying and exposing the same pattern of the mask on the same area of the wafer.

  (4) According to the present invention, according to the above (1) or (3), it is possible to improve the ease of manufacturing a mask having a groove shifter structure.

  (5) According to the present invention, according to the above (1), (2) or (3), it is possible to improve the manufacturing yield of a mask having a groove shifter structure.

  (6) According to the present invention, the yield of the semiconductor integrated circuit device can be improved by the above (1), (2) or (3).

  (7) According to the present invention, the reliability of the semiconductor integrated circuit device can be improved by the above (1), (2) or (3).

  (8) According to the present invention, the performance of the semiconductor integrated circuit device can be improved by the above (1), (2) or (3).

  (9) According to the present invention, according to the above (1), (2) or (3), it is possible to improve the degree of integration of elements and wirings of the semiconductor integrated circuit device.

  In describing embodiments of the present invention, the basic meaning of terms in the present application will be described as follows.

1. Ultraviolet light: In the semiconductor field, it refers to electromagnetic waves from around 450 nm to a short wavelength of about 50 nm or less. The longer wavelength than 300 nm is called the near ultraviolet region, and the shorter wavelength region is called the far ultraviolet region, and 200 nm or less is particularly vacuum ultraviolet. Say area. Examples of the light source include i-line (wavelength 365 nm) and g-line (wavelength 436 nm) such as mercury arc lamp, KrF excimer laser (wavelength 248 nm), ArF and F ₂ excimer laser.

  2. Scanning exposure: A narrow slit-shaped exposure band is formed in a direction perpendicular to the longitudinal direction of the slit (obliquely with respect to a wafer and a mask (or a reticle, which indicates a broad concept including a reticle in this application)). An exposure method in which the circuit pattern on the mask is transferred to a desired portion on the wafer by relatively continuous movement (scanning).

  3. Step-and-scan exposure: A method in which the entire portion to be exposed on the wafer is exposed by combining the scanning exposure and the stepping exposure, and is a subordinate concept of the scanning exposure.

  4). Substrate groove shifter: A phase shifter in which concave portions are formed on the surface of a transparent mask substrate itself such as quartz. The surface of the substrate itself includes the surface of the substrate formed with a film similar in material to the substrate.

  5. Thin-film groove shifter on substrate: A groove type formed by forming a shifter film with a thickness suitable for the purpose of acting as a shifter under the shielding film on the substrate and using the etching rate difference with the underlying substrate, etc. Shifter.

  6). Groove shifter: A general concept including the substrate groove shifter and the thin film groove shifter on the substrate, and generally refers to a shifter in which concave portions are formed in a transparent film, a transparent substrate or the like below the light shielding film. On the other hand, a system in which the shifter film is arranged in a shielding film shape is called a shifter film top-positioning system or a top-shifting shifter.

  7. Fine vertical groove shifter: The length of the protruding portion of the light shielding film in the overhang shape (or in the shape of a bowl) from the upper end of the recess side wall of the quartz substrate or the like to the inside of the recess in the periphery of the groove shifter (narrow cross-sectional direction) This is a case where P is 40% or less (P / λ = 40% is referred to as “庇 length”) with reference to the wavelength λ of the monochromatic exposure light.

  8). Phase shift mask pattern: A circuit pattern on a mask including a mask opening pattern having at least one phase shifter. For example, a circuit pattern group on a mask corresponding to a single shot area of stepping exposure (range to be exposed in one step) or an area exposed by single scanning in scanning exposure, for example, a unit chip area on a wafer Or a mask pattern (circuit pattern) on the mask substrate corresponding to an integral multiple of the mask pattern.

  9. Auxiliary mask pattern: An aperture pattern on a mask that generally does not form an independent image corresponding to the aperture pattern when projected onto a wafer.

  10. Levenson type phase shift mask: Also called a spatial frequency modulation type phase shift mask, it is generally composed of a group of apertures that are separated from each other by a light shielding region in a light shielding film, are provided with a plurality of apertures close to each other, and their phases are alternately inverted. Phase shift mask. Roughly classified, there are a line and space pattern and an alternating inversion hole pattern (also called a Levenson pattern for contact holes).

  11. Auxiliary pattern type phase shift mask: Roughly classified, it is classified into isolated line pattern and hole pattern, the former representative is the actual opening pattern and auxiliary shifter patterns provided on both sides (this phase inversion pattern is also equivalent) The representative of the latter is an outrigger type hole pattern (consisting of a central real opening and a plurality of auxiliary openings provided around it). However, since an auxiliary opening and an auxiliary shifter are provided at the edge or the periphery of the mask pattern of the Levenson type phase shift mask, both types are often mixed in an actual pattern.

  12 Shifter edge phase shift mask: Roughly categorized, one-edge method that forms a pattern with the edge of a transparent shifter, double-edge method that forms a pattern with both edges of a fine or minute transparent shifter, an edge with a shifter edge in the opening It is classified into an emphasis method and a halftone method in which these shifters are made translucent.

  13. Phase shift mask: When simply referred to as a phase shift mask in the present application, these are collectively referred to.

  14 A wafer (semiconductor wafer, semiconductor substrate) is a silicon single crystal substrate (generally a substantially planar circular shape) used in the manufacture of semiconductor integrated circuits, a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, and their composites. Say the target board. In addition, in the present application, the term “semiconductor integrated circuit device” refers to a TFT (Tin-Film-Transistor), unless otherwise specified, in addition to those manufactured on a semiconductor or insulator substrate such as a silicon wafer or a sapphire substrate. ) And STN (Super-Twisted-Nematic) liquid crystal or the like made on other insulating substrates such as glass.

  15. “Light shielding region”, “light shielding pattern”, “light shielding film”, or “light shielding” means that the exposure light irradiated to the region has an optical characteristic that transmits less than 40%. Generally, several to less than 30% are used. On the other hand, when “light transmissive region”, “light transmissive pattern”, “transparent region”, “transparent film” or “transparent” is referred to, optical characteristics that transmit 60% or more of the exposure light applied to the region. It has shown that. Generally 90% or more is used.

  16. “Photoresist pattern” refers to a film pattern obtained by patterning a photosensitive organic film by a photolithography technique. This pattern includes a simple resist film having no opening at all for the portion.

  17. Normal illumination refers to non-deformed illumination, and refers to illumination with a relatively uniform light intensity distribution.

  18. Deformation illumination is illumination with reduced illuminance at the center, and super-resolution technology using oblique illumination, annular illumination, quadrupole illumination, multipole illumination such as quadrupole illumination, or an equivalent pupil filter. including.

19. Resolution: The pattern dimension can be expressed by normalizing the numerical aperture NA (Numerical Aperture) of the projection lens and the exposure wavelength λ. In the present embodiment, KrF excimer laser light having an exposure wavelength of 248 nm is mainly used, and the NA of the projection lens is mainly 0.65. Therefore, when using a different wavelength or a different lens NA, the resolution R is expressed by R = K1 · λ / NA, and may be converted (for example, normally K1 = 0.6). However, since the depth of focus D is also expressed by D = K 2 · λ / (NA) ² , the depth of focus is different.

  20. Shifter depth: The substrate digging depth of the shifter portion depends on the exposure wavelength, and the depth Z at which the phase is inverted by 180 degrees is expressed by Z = λ / (2 (n−1)). Here, n is the refractive index of the substrate with respect to exposure light having a predetermined exposure wavelength, and λ is the exposure wavelength.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  21. Transfer pattern: A pattern transferred onto a wafer by a mask, specifically, the photoresist pattern and a pattern on the wafer actually formed using the photoresist pattern as a mask.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  Further, even in the drawings used for the description of the present embodiment, even if it is a plan view of a mask, the light shielding pattern and the groove shifter are hatched in order to make the drawings easy to see.

(Embodiment 1)
FIG. 1 shows a schematic manufacturing process of the manufacturing method of the semiconductor integrated circuit device according to the first embodiment.

  First, a mask and a wafer are set in an exposure apparatus, and the relative planar positions of both are aligned. In the first embodiment, a phase shift mask having a groove shifter is used as a mask. A film to be processed and a photoresist film have already been deposited in order from the lower layer on the wafer (step 101). Subsequently, the mask pattern of the mask is exposed on the photoresist film on the wafer. At this time, in the first embodiment, the mask pattern in the mask transfer region is exposed twice or more in one region on the wafer. Here, the mask patterns of the transfer regions formed at different positions in the same mask or the mask patterns of the transfer regions of different physically separated masks are overlapped and exposed at least twice. In this case, each mask pattern of each transfer region is the same, and each transfer region passes through each of the corresponding positions of the respective transfer regions (positions that overlap in plan view during exposure). The groove shifters are arranged so that the phases of the light beams are inverted by 180 degrees (step 102). Thereafter, a photoresist pattern is formed by performing development processing on the photoresist film (step 103), and then the processing target film is etched using the photoresist pattern as a mask. Is patterned (step 104). Thereafter, by removing the photoresist pattern, a predetermined pattern made of a film to be processed is formed on the wafer (step 105). The technical idea of the present invention can also be applied to the case where impurities or the like are selectively introduced into a predetermined plane position of a semiconductor substrate using a photoresist pattern as a mask.

  Next, an example of an exposure apparatus used for the multiple exposure process will be described with reference to FIGS.

  An exposure apparatus 1 shown in FIG. 2 is, for example, a scanning reduction projection exposure apparatus (hereinafter referred to as a scanner) having a reduction ratio of 4: 1. The exposure conditions of the exposure apparatus 1 are as follows, for example. That is, for example, KrF excimer laser light having an exposure wavelength of about 248 nm is used as the exposure light EXL, the numerical aperture NA of the optical lens is 0.65, the illumination shape is circular, and the coherency (σ: sigma) value = 0. 3. As the mask 2, for example, a Levenson type phase shift mask is used. However, the present invention is not limited to this, and various modifications can be made. For example, an ArF excimer laser having a wavelength of about 193 nm may be used.

  The light emitted from the exposure light source 1a illuminates the mask (reticle) 2 through the fly-eye lens 1b, the aperture 1c, the condenser lenses 1d1, 1d2, and the mirror 1e. Of the optical conditions, the coherency was adjusted by changing the size of the opening of the aperture 1f. On the mask 2, a pellicle 2p for preventing pattern transfer failure due to adhesion of foreign matter is provided. The mask pattern drawn on the mask 2 is projected onto the wafer 3 which is a sample substrate via the projection lens 1g. The mask 2 is placed on the mask stage 1i2 controlled by the mask position control means 1h and the mirror 1i1, and the center of the mask 2 and the optical axis of the projection lens 1g are accurately aligned.

  The wafer 3 is vacuum-sucked on the sample stage 1j. The sample stage 1j is placed on the Z stage 1k that can move in the optical axis direction of the projection lens 1g, that is, the direction perpendicular to the wafer placement surface of the sample stage 1j (Z direction), and further the wafer of the sample stage 1j. It is mounted on an XY stage 1m that can move in a direction parallel to the mounting surface. Since the Z stage 1k and the XY stage 1m are driven by the driving means 1p and 1q in accordance with a control command from the main control system 1n, they can be moved to desired exposure positions. The position is accurately monitored by the laser length measuring instrument 1s as the position of the mirror 1r fixed to the Z stage 1k. Further, the surface position of the wafer 3 is measured by a focus position detecting means provided in a normal exposure apparatus. By driving the Z stage 1k according to the measurement result, the surface of the wafer 3 can always coincide with the imaging plane of the projection lens 1g.

  The mask 2 and the wafer 3 are driven in synchronization according to the reduction ratio, and the mask pattern is reduced and transferred onto the wafer 3 while the exposure area scans over the mask 2. At this time, the surface position of the wafer 3 is also dynamically driven and controlled with respect to the scanning of the wafer by the above-described means. When the circuit pattern on the mask 2 is superimposed and exposed on the circuit pattern formed on the wafer 3, the position of the mark pattern formed on the wafer 3 is detected using the alignment detection optical system 1t, and the detection is performed. From the result, the wafer 3 is positioned and superimposed and transferred. The main control system 1n is electrically connected to the network apparatus 1u, and remote monitoring of the state of the exposure apparatus 1 is possible.

  FIG. 3 is a diagram schematically showing the scanning exposure operation of the exposure apparatus 1. Since the mask 2 and the wafer 3 have a mirror-symmetrical relationship, the scanning direction of the mask 2 and the scanning direction of the wafer 3 are as indicated by the arrow direction of the stage scan in FIG. Reverse. When the reduction ratio is 4: 1, the movement distance of the wafer 3 is 1 with respect to the movement distance 4 of the mask 2. At this time, the exposure light EXL is irradiated onto the mask 2 through the slit 1fs to form a slit-shaped exposure region (exposure band), and the slit-shaped exposure region is formed on the mask 2 in the width direction of the slit 1fs, that is, The wafer 3 is continuously moved (scanned) in a direction orthogonal to or obliquely intersecting with the longitudinal direction of the slit 1fs, and further irradiated onto the wafer 3 via the imaging optical system (projection lens 1g). Thereby, the mask pattern in the transfer area of the mask 2 is transferred to each of the plurality of chip formation areas CA of the wafer 3. Each chip formation area CA is an area for forming one semiconductor chip.

A planar rectangular slit 1fs is opened in the aperture 1f, and the exposure light EXL is irradiated to the mask 2 through the slit 1fs. That is, in the exposure apparatus 1, as shown in FIGS. 3 and 4, slit-shaped exposure areas included in the effective exposure area 1 ga of the projection lens 1 g (in order to make the drawing easy to see, hatching is applied in FIG. 4). ) SA1 is used as an effective exposure area. Therefore, the exposure apparatus (scanner) 1 exposes the slit-shaped exposure area SA1. Although not particularly limited, the width of the slit 1fs is usually about 4 to 7 mm on the wafer 3, for example. For comparison, the exposure area in the stepper is shown in FIG. In the stepper, a planar square exposure area (indicated by hatching in FIG. 5 for easy viewing) SA2 is used as an effective exposure area in which four corners are inscribed in the effective exposure area 1ga of the projection lens. . In the stepper, the pattern in the mask 2 is collectively exposed. The technical idea of the present invention can also be applied to a stepper. 2 to 5 show only the portions necessary for explaining the functions of the exposure apparatus, but the portions necessary for other ordinary exposure apparatuses (scanners and steppers) are the same in the ordinary range. is there.

  Next, an example of the mask 2 used in the first embodiment will be described with reference to FIGS. 6A is an overall plan view of the mask 2, and FIGS. 6B and 6C are cross-sectional views taken along lines AA and BB in FIG. 6A, respectively. 7 and 8 are examples of enlarged cross-sectional views of the main part of the mask of FIG. Although FIG. 6A is a plan view, hatching is added to make the drawing easy to see.

  Here, a case where, for example, two transfer regions 4A and 4B are arranged on the main surface (same surface) of one mask 2 is illustrated. Each of the transfer regions 4A and 4B is formed in a planar rectangular shape, for example, and is arranged at a predetermined distance so that the long sides thereof are parallel to each other. Each of the transfer areas 4A and 4B corresponds to an area where, for example, one semiconductor chip (the chip formation area) is transferred. The number of transfer regions arranged on one mask 2 is not limited to the above and can be variously changed.

  A mask substrate 2a constituting the mask 2 is made of, for example, a transparent synthetic quartz glass having a square planar shape, and a mask pattern is formed in each of the transfer regions 4A and 4B on the main surface. This mask pattern is a pattern for transferring a predetermined integrated circuit pattern. For example, the light-shielding pattern 2b made of chromium, chromium oxide, or a laminated film of these, and the light transmission formed by partially exposing the mask substrate 2a. It consists of a pattern 2c. Further, the groove shifter 2d is disposed in one of the light transmission patterns 2c adjacent to each other in each of the transfer regions 4A and 4B. In the first embodiment, the shapes and dimensions of the mask patterns of the transfer regions 4A and 4B are the same. However, in the transfer areas 4A and 4B, the arrangement of the groove shifters 2d is opposite to each other. That is, when the transfer areas 4A and 4B are overlaid on one area (chip formation area) of the wafer and exposed, the light transmitted through the predetermined light transmission pattern 2c in the transfer area 4A and the predetermined light in the transfer area 4A The groove shifter 2d is arranged so that the phase of the transmitted light is inverted by 180 degrees with respect to the light transmitted through the predetermined light transmission pattern 2c in the transfer region 4B that overlaps the transmission pattern 2c in a plane.

  The depth Z of the groove shifter 2d is formed so as to satisfy Z = λ / (2 (n−1)) in order to invert the phase of transmitted light by 180 degrees. Here, n is the refractive index of the substrate with respect to exposure light having a predetermined exposure wavelength, and λ is the exposure wavelength. In the above example, for example, KrF having an exposure wavelength of 248 nm is used, so the depth Z is, for example, about 245 nm. When the multiple exposure process as described above is not performed, the range of the depth error of the groove shifter 2d is, for example, about ± 3 nm (2 degrees in phase angle) and is extremely narrow. Therefore, it is very difficult to manufacture the mask 2, which causes a reduction in the yield of the mask 2. On the other hand, in the first embodiment, the depth error range of the groove shifter 2d can be relaxed to about ± 4 nm to 8 nm (3 to 6 degrees in phase angle), for example. Therefore, it is possible to greatly improve the ease of manufacturing the mask 2. In addition, the manufacturing yield of the mask 2 can be greatly improved. This will be described in detail later.

  In addition, in the transfer regions 4A and 4B, in addition to a pattern that substantially constitutes an integrated circuit, for example, a mark pattern used for overlay, a mark pattern used for overlay inspection, or a mark used when inspecting electrical characteristics A pattern that does not substantially constitute an integrated circuit, such as a pattern, is also included. In addition, a part of the mask substrate 2a is exposed in the light shielding area on the outer periphery of the transfer areas 4A and 4B, and another light transmission pattern 2e such as a mask alignment mark or a measurement mark is formed.

  7 and FIG. 8 show a pair of light transmission patterns 2c, 2c (light transmission patterns 2c, 2c adjacent to each other of the mask 2 of FIG. 6 and the groove shifter 2d is disposed on one of them. An example of an enlarged sectional view of a pair) portion is shown.

  7A to 7C show a case where the groove shifter 2d is the substrate groove shifter. That is, the groove shifter 2d is formed by digging a groove having a concave cross section on the surface of the mask substrate 2 itself. FIG. 7A shows a case where there is no ridge structure. That is, the side wall surface of the groove shifter 2d and the side wall surface of the opening portion (light transmission pattern 2c) of the light shielding pattern 2b substantially coincide with each other, and no ridge is formed at the opening side end portion of the light shielding pattern 2b. Shows the case. In this case, the depth Z of the groove shifter 2d is a length from the height of the pattern forming flat surface of the mask 2 to the flat surface at the bottom of the groove shifter 2d. In the first embodiment, it is possible to improve the dimensional accuracy of the pattern transferred onto the wafer by performing the multiple exposure process even with the mask 2 shown in FIG. It has become.

  FIGS. 7B and 7C show the case where the groove shifter 2d is the fine saddle groove shifter. That is, the mask substrate 2a is overhanged in the width direction of the groove shifter 2d in the periphery of the groove shifter 2d (in the narrow cross-sectional direction), and as a result, the end of the light shielding pattern 2b facing the groove shifter 2d protrudes in a bowl shape. It has a structure. Here, for example, the length P of the protruding portion of the light shielding pattern 2b is 40% (P / λ = 40%) or less when the wavelength λ of the monochromatic exposure light is used as a reference. However, the present invention itself can also be applied to those having a ridge length of 70% or less (for example, when the wavelength of exposure light is 248 nm, the ridge length is about 150 nm). By using such a saddle structure, the optical waveguide phenomenon can be suppressed. That is, it is possible to suppress the attenuation of the light intensity of the transmitted light due to the influence from the side wall of the groove shifter 2d. Therefore, in the first embodiment, the dimensional accuracy of the pattern transferred onto the wafer can be further improved by using the mask 2 shown in FIGS. 7B and 7C in the multiple exposure process. .

  In FIG. 7B, even in the light transmission pattern 2c where the groove shifter 2d is not disposed, the mask substrate 2a is dug to form the groove 2f, but the light transmission pattern 2c where the groove shifter 2d is disposed; A phase difference of 180 degrees is generated in each light transmitted through the light transmission pattern 2c in which the groove 2f is disposed. The groove 2f has a saddle structure. When the groove shifter 2d is formed, if the light transmission pattern 2c that does not require the formation of a groove is covered with a photoresist film, the steps of applying and patterning the photoresist film increase. Therefore, in the mask 2 of FIG. 7B, the photoresist film is not formed when the ridge structure is formed in the groove shifter 2d, and the surface (pattern forming surface) of the mask substrate 2a is formed using the light shielding pattern 2b as an etching mask. Wet etching. The groove 2f is formed at that time. According to this method, the photoresist film coating and patterning steps can be eliminated, so that the manufacturing process of the mask 2 can be simplified. The depth Z of the groove shifter 2d in the case of this mask 2 is the length from the height of the pattern forming flat surface of the mask 2 at the bottom of the groove 2f to the flat surface at the bottom of the groove shifter 2d. FIG. 7C shows a case where the groove 2f of FIG. 7B is not formed. The depth of the groove shifter 2d in this case is the same as in the case of FIG. The manufacturing method of the mask 2 shown in FIGS. 7A to 7C will be described in detail later.

8A to 8C show the case where the groove shifter 2d is the above-described thin film groove shifter on the substrate. That is, the shifter film 2g is formed on the surface of the mask substrate 2a, and the light shielding pattern 2b is further formed thereon. The shifter film 2g is formed with a thickness suitable for the purpose of acting as a phase shifter (= the above formula of Z). For example, the SOG (Spin On) with light transmittance and refractive index equivalent to or similar to those of the mask substrate 2a. Glass). The groove shifter 2d is formed by removing the shifter film 2g of the predetermined light transmission pattern 2c until the surface of the mask substrate 2a is exposed. In this case, when the groove shifter 2d is formed, the etching selection ratio between the mask substrate 2a and the shifter film 2g is increased so that the etching rate of the shifter film 2g is higher than the etching rate of the mask substrate 2a. That is, the groove shifter 2d is formed using the mask substrate 2a as an etching stopper. Thereby, the depth of the groove shifter 2d (that is, the thickness of the shifter film 2g) and the flatness of the bottom surface of the groove shifter 2d can be formed with extremely high accuracy. Therefore, the phase error of the transmitted light can be greatly reduced or eliminated, so that the dimensional accuracy of the pattern transferred onto the wafer can be greatly improved. 8A to 8C correspond to FIGS. 7A to 7C, respectively. 8A shows a structure without a ridge structure, FIG. 8B shows a structure in which a ridge and a groove 2f are formed, and FIG. 8C shows a structure with only a ridge and no groove 2f.

  Next, an example of the multiple exposure method of the first embodiment will be described with reference to FIG. FIG. 9 is an overall plan view of the wafer 3 and uses the mask 2 (see FIG. 6) and the scanner 1 (see FIG. 1) on the main surface of the wafer 3 (a photoresist film is applied). A step-and-scan exposure process for transferring a predetermined integrated circuit pattern is illustrated.

The exposure conditions are the same as those described in the description of the exposure apparatus 1. On the main surface of the wafer 3, for example, an insulating film (silicon oxide film or the like) having a thickness of about 200 nm is formed. On the insulating film, a positive photoresist film having a thickness of, for example, about 500 nm is deposited. The exposure amount to this photoresist film was adjusted to, for example, 25 mJ / cm ² and, for example, 50 mJ / cm ² by double exposure. The minimum pattern in the mask 2 is, for example, 150 nm line and space in terms of the wafer 3.

  First, the transfer areas 4A and 4B of the mask 2 are transferred to the area 5A on the wafer 3 by the scanning exposure process. That is, the mask 2 and the wafer 3 are moved in the opposite directions (vertical and vertical directions in FIG. 9) while keeping their main surfaces parallel to move the slit-shaped exposure region on the main surface of the wafer 3. As a result, the mask pattern (integrated circuit pattern) in the transfer regions 4A and 4B of the mask 2 is transferred to the region 5A on the main surface of the wafer 3. The transfer areas 5A1 and 5A2 of the area 5A on the wafer 3 are areas to which the transfer areas 4A and 4B of the mask 2 have been transferred, and correspond to the chip formation area here.

  Subsequently, the wafer 3 is horizontally moved in the right direction in FIG. 9, and the regions 5B and 5C are sequentially exposed in the same manner as described above. The exposure amount in these areas 5A, 5B, and 5C is about ½ of the required amount. The transfer areas 5B1 and 5C1 in the areas 5B and 5C are the same as the transfer area 5A1, and the transfer areas 5B2 and 5C2 are the same as the transfer area 5A2.

  Subsequently, for example, after the wafer 3 is moved upward in FIG. 9 by one transfer area 5A1, 5A2, the area 5D is exposed in the same manner as described above. At this time, in the first embodiment, the transfer area 5D1 in the area 5D and the transfer area 5C2 in the previously transferred area 5C are planarly overlapped. That is, the transfer region 4A in the same mask 2 is transferred in a planar manner to the transfer region 5C2 to which the transfer region 4B in the mask 2 is transferred. As described above, the phases of the lights transmitted through the same planar positions of the transfer regions 4A and 4B of the mask 2 are inverted by 180 degrees.

  Subsequently, the wafer 3 is moved horizontally in the left direction of FIG. 9, and the region 5E is sequentially exposed in the same manner as described above. Here, the transfer area 5E1 in the area 5E and the transfer area 5B2 in the previously transferred area 5B are overlapped in a plane. That is, the transfer region 4A in the same mask 2 is transferred in a planar manner to the transfer region 5C2 to which the transfer region 4B in the mask 2 is transferred. Here, as described above, the phases of the light beams transmitted through the same planar positions of the transfer regions 4A and 4B of the mask 2 are inverted by 180 degrees.

  The exposure amount in these areas 5D and 5E is about ½ of the required amount. Accordingly, when the areas 5A to 5E overlap (transfer areas 5B2, 5E1, transfer areas 5C2, 5D1, etc.), the exposure amount becomes a necessary amount. The transfer areas 5D1 and 5E1 in the areas 5D and 5E are the same as the transfer area 5A1, and the transfer areas 5D2 and 5E2 are the same as the transfer area 5A2.

  By repeating such multiple exposure processing operation on the entire surface of the wafer 3, the integrated circuit patterns in a plurality of chip formation regions are transferred onto the wafer 3. Here, the transfer area 4A and the transfer area 4B of the mask 2 are overlapped. That is, although the mask patterns are the same, the transfer regions 4A and 4B in which the groove shifters 2d are arranged so that the phases of the transmitted light are reversed are overlapped and exposed. By such an exposure process, the dimensional accuracy of the pattern transferred onto the wafer 3 can be improved.

  In the above description, the transfer areas 5A1, 5B1, and 5C1 of the outermost transfer areas 5A, 5B, and 5C are not double-exposed, but the transfer area 4A of the mask 2 is, for example, masked by the masking blade. Double exposure was performed by transferring light so that the transfer area of the transfer area 4B of the mask 2 overlaps the transfer area 5A1 of the wafer 3 in FIG. The same applies to the transfer areas 5B1 and 5C1.

  Next, the operation of the multiple exposure processing according to the first embodiment will be described with the problems of the technique studied by the inventors for carrying out the present invention.

  First, the problem of the technique examined by the present inventors will be described with reference to FIG. FIG. 10A shows the cross-sectional shape of the phase shift mask 50. The phase shift mask 50 includes a mask substrate 50a, a light shielding pattern 50b formed on the main surface, and a light transmission pattern 50c. The light shielding pattern 50b is made of, for example, chromium. In one of the light transmission patterns 50c and 50c adjacent to each other, a mask shifter 50d is formed by digging the mask substrate 50a to a predetermined depth in order to give a phase difference of 180 degrees to each transmitted light. Here, a case where the substrate groove shifter is not a fine saddle groove shifter is illustrated. Further, the planar shapes and dimensions of the light transmission patterns 50c, 50c adjacent to each other are the same.

  When projection exposure is performed using this phase shift mask 50, the light intensity obtained on the projection substrate is the intensity of the light transmitted through the light transmission pattern 50c in which the groove shifter 50d is disposed, as shown in FIG. 51a becomes smaller than the intensity 51b of light transmitted through the light transmission pattern 50c in which the groove shifter 50d is not disposed. This is because the intensity of transmitted light is attenuated by the influence of the side wall of the groove shifter 5d in which the mask substrate 50a is dug. Therefore, when the pattern is transferred to the photoresist film by a normal method (one-time exposure), as shown in the exposure plane of FIG. The dimension w50 in the width direction of the pattern 52a is smaller than the dimension w51 in the width direction of the photoresist pattern 52b to which the light transmission pattern 50c in which the groove shifter 50d is not disposed is transferred. That is, the planar dimensions of the photoresist patterns 52a and 52b that should be transferred with the same planar dimension differ depending on the presence or absence of the groove shifter 50d.

  In order to prevent this, as shown in FIG. 11A, it is adopted that the groove shifter 50d has the fine saddle type groove shifter structure. That is, the side wall of the groove shifter 50d of the mask substrate 50a is adjusted so as to be hidden under the light shielding pattern 50b, and the end portion of the light shielding pattern 50b protrudes in a bowl shape by the collar length P. By adopting this structure, as shown in FIG. 11B, the intensity 53a of the light transmitted through the light transmission pattern 50c in which the groove shifter 50d is disposed is equal to the light transmission pattern 50c in which the groove shifter 50d is not disposed. Although it is almost the same as the intensity 53b of the transmitted light, it is not completely equal at present. Therefore, as shown in the exposure plane of FIG. 11C, the width w52 of the photoresist pattern 55a to which the light transmission pattern 50c having the groove shifter 50d is transferred and the groove shifter 50d are not arranged. The dimension w53 in the width direction of the photoresist pattern 55b to which the light transmission pattern 50c is transferred is substantially equal, but is not completely equal.

  Here, the present inventors investigated and studied in more detail. FIG. 12 shows the results of the survey and research. The horizontal axis indicates the dimension of the line and space (pattern), and the vertical axis indicates the dimension difference (w52−w53) between the photoresist patterns 55a and 55b in each dimension. The pattern transfer conditions here are, for example, as follows. That is, the heel length P is set to 100 nm, for example, and the dimension of the resolution pattern is changed from 0.12 to 0.18 μm, for example. The exposure conditions are the same as those described in the description of the exposure apparatus 1. As a result, it became clear that the difference between the dimensions w52 and w53 of the photoresist patterns 55a and 55b differs depending on the dimension value of the pattern to be formed on the wafer. Therefore, it has been found that it is difficult to eliminate the dimensional difference of the pattern transferred onto the wafer by simply forming the groove shifter with a ridge structure.

  Therefore, in the first embodiment, the mask pattern of the mask 2 is transferred to the wafer 3 by multiple exposure processing as described above. At this time, the groove shifters 2d of the mask pattern to be subjected to multiple exposure are arranged so as to be reversed with respect to each other. As a result, in the pattern transferred onto the wafer 3, due to the difference in dimension of the transfer pattern due to an error in absolute value of the phase, the difference in dimension of the transfer pattern due to the presence or absence of the groove shifter 2d, and the difference in dimension of the pattern to be formed on the wafer. Since the dimensional difference between the transfer patterns can be reduced or eliminated, the dimensional accuracy of the transfer pattern can be improved, and the dimensions of the transfer pattern can be made uniform.

  FIG. 13 shows the result of examining the effect of the multiple exposure of the first embodiment described above by simulation. For comparison, the result of single exposure is shown in FIG. Both show the light intensity distribution obtained on the wafer. In any of the exposure processes, a phase shift mask having a normal groove shifter (not a fine saddle groove shifter) structure was used.

  As shown in FIG. 13, according to the first embodiment, since the transfer regions 4A and 4B arranged so that the groove shifter 2d is inverted are exposed twice, the light intensity peaks adjacent to each other are exposed. It can be seen that uniform light intensity is obtained at 6a and 6b. On the other hand, in the case of a single exposure, as shown in FIG. 14, the intensity 56a of the light transmitted through the light transmission pattern in which the groove shifter is disposed is the intensity of the light transmitted through the light transmission pattern without the groove shifter. It can be seen that it is smaller than 56b.

  FIG. 15 schematically shows a simplified operation of the multiple exposure process of the first embodiment. FIG. 15A shows two transfer regions 4C and 4D to be overlaid on the mask 2, and FIG. 15B shows a cross-sectional view taken along the lines AA and BB in FIG. In each of the transfer regions 4C and 4D, adjacent strip-like light transmission patterns 2c and 2c are formed. The planar shapes and dimensions of the light transmission patterns 2c and 2c in the transfer regions 4C and 4D are the same. In each of the transfer regions 4C and 4D, the groove shifter 2d is arranged in one of the light transmission patterns 2c and 2c adjacent to each other, but the arrangement becomes opposite when the transfer region 4C and the transfer region 4D are overlapped. In other words, the phase of the transmitted light is inverted by 180 degrees. FIG. 15C shows the intensity distribution of light transmitted through the transfer regions 4C and 4D. In the intensity distribution of the light transmitted through each of the transfer regions 4C and 4D, the intensity of the light transmitted through the light transmission pattern 2c in which the groove shifter 2d is disposed is attenuated. On the other hand, FIG. 15D shows the intensity distribution of transmitted light when the transfer regions 4C and 4D are exposed in an overlapping manner. In this case, the light transmitted through the light transmission pattern 2c in which the groove shifter 2d is disposed and the light transmitted through the light transmission pattern 2c without the groove shifter 2d are exposed to overlap with each other, so that both lights Since the intensity can be averaged and the light intensity imbalance can be canceled, the light intensity distribution can be made uniform.

  Therefore, according to the multiple exposure processing of the first embodiment, even if the absolute value accuracy (error accuracy) of the phase is somewhat poor, it is possible to obtain the same resolution characteristics as when the phase difference is 180 degrees. That is, the allowable amount of phase error (the absolute value accuracy of the phase) can be relaxed to, for example, about 3 degrees to 6 degrees (± 4 nm to ± 8 nm as the depth of the groove shifter 2d). Therefore, it is possible to greatly improve the ease of manufacturing the mask 2. In addition, the manufacturing yield of the mask 2 can be greatly improved. In particular, in the first embodiment in which the transfer regions 4A and 4B to be overlapped are formed at different plane positions within the same plane of the same mask 2, the grooves are compared with the case where the transfer regions to be overlapped are formed on separate masks. Since the depth of the shifter 2d and the error amount thereof can be made substantially uniform in the plane of the mask 2, the absolute value accuracy of the phase is relatively higher than when the overlapping transfer regions are formed on separate masks. The mask 2 can be easily manufactured while ensuring.

  In addition, according to the multiple exposure process of the first embodiment, it is possible to suppress or prevent the adjacent transfer pattern from fluctuating depending on the presence or absence of the groove shifter 2. For this reason, it becomes possible to greatly improve the dimensional accuracy of the transferred pattern. Further, since the dimensional variation of the adjacent transfer pattern due to the presence or absence of the groove shifter 2 can be reduced or prevented, the necessity for a fine saddle-shaped groove shifter structure is eliminated. For this reason, it becomes possible to improve the ease of manufacture of the mask 2 significantly. The longer the ridge length is, the more effective the ridge structure is. However, since the light shielding pattern 2b on the mask 2 is also miniaturized in accordance with the demand for pattern miniaturization on the wafer, there is a limit to the increase of the ridge length. . The technique of the first embodiment is a technique suitable for pattern miniaturization because the pattern dimension accuracy can be improved without adopting a saddle structure.

  Furthermore, according to the multiple exposure process of the first embodiment, it is possible to suppress or prevent the dimensional difference between adjacent patterns from fluctuating according to the dimension of the pattern to be transferred onto the wafer 3. Therefore, the dimensional accuracy of the pattern transferred to the wafer 3 can be improved in the entire transfer region.

  As a result of actually transferring the pattern, for example, a 150 nm pattern was successfully formed with an accuracy of 150 nm ± 10 nm on the entire surface of the chip. In addition, no special tendency was observed in the resolution dimension of adjacent patterns. The occurrence of a pattern short circuit due to a defect in the mask 2 was not observed. On the other hand, with the technique in which double exposure is not performed under the same conditions, a 150 nm pattern was formed with an accuracy of 150 nm ± 22 nm on the entire chip surface. Further, the resolution dimension difference between the pattern in which the groove shifter is disposed and the pattern in which the groove shifter is not disposed is 8 nm, and the pattern in which the groove shifter is disposed is formed thinner.

  Next, other problems studied by the present inventors will be described. That is, in pattern transfer using a projection optical system, a projection image is distorted by various aberrations of the projection lens. This phenomenon varies depending on the position of the projection plane. A typical aberration is, for example, distortion of a transferred image. This is a misalignment of the projection pattern. For example, a pattern arranged in an absolute lattice is distorted and transferred in a pincushion shape or a barrel shape. That is, normally, since the projection lens has various aberrations, it is difficult to form a pattern as designed.

  Here, in pattern transfer using a stepper, if multiple integrated circuit patterns are transferred in one shot and multiple exposure is performed by shift exposure, an overlay error occurs due to the effect of pattern position distortion, and resolution characteristics are greatly improved. It is difficult to put it to practical use. FIG. 16 schematically shows such a state. Here, a description will be given taking a pattern transfer with a stepper as an example. Reference numeral 60 denotes a design pattern on an ideal lattice, which is a square pattern without distortion. Reference numerals 61 and 62 are transfer patterns actually transferred. The transfer pattern 61 is transferred while being displaced in a pincushion shape with respect to the ideal lattice, and the transfer pattern 62 is transferred while being displaced in a barrel shape with respect to the ideal lattice. As described above, the aberration of the projection lens causes a pattern displacement, and the behavior varies depending on the transfer position.

  FIGS. 17A and 17B schematically show a state in which transfer regions of different plane position coordinates on the mask are transferred using a stepper. Reference numerals 63a and 63b in FIGS. 17 (a) and 17 (b) indicate the state of the overall displacement of the transfer area when the transfer area constituted by the same pattern at different plane positions on the mask is actually transferred. It is shown schematically. As shown in FIG. 17A, the transfer regions 63a and 63b are formed (transferred) in different shapes. Therefore, when they are overlapped as shown in FIG. Therefore, it is difficult to form (transfer) a good pattern.

  Therefore, in the first embodiment, as described above, when the mask pattern of the mask 2 is transferred onto the wafer 3 using a scanner, the same pattern of the mask 2 is subjected to multiple exposure on the same area of the wafer 3. In the exposure process using a scanner, the pattern on the mask 2 is transferred onto the wafer 3 through a slit. In this case, the aberration distribution is uniform in the scanning direction. That is, even if overlay exposure is performed in the scan direction, an overlay error due to aberration does not occur. Therefore, it is possible to perform overexposure.

  FIG. 18 shows a pattern transfer state when a scanner is used. Reference numeral 7 denotes a design pattern on an ideal lattice, which is a square pattern without distortion. Reference numeral 7 a indicates a side parallel to the scanning direction (vertical and vertical direction in FIG. 18) in the design pattern 7, and reference numeral 7 b indicates a side orthogonal to the scanning direction in the design pattern 1. Here, the scanning direction is the scanning direction of the projection lens, and the substrate to be exposed such as the wafer 3 is moved in the opposite direction. Reference numeral 8 indicates a transfer pattern actually transferred. Reference numeral 8 a indicates a side parallel to the scanning direction in the transfer pattern 8, and reference numeral 8 b indicates a side orthogonal to the scanning direction in the transfer pattern 8. Reference numerals 9a and 9b schematically show the overall state of the transfer area where the transfer areas 4A and 4B composed of the same pattern at different plane positions on the mask 2 are actually transferred.

  In the exposure processing using a scanner, a positional shift caused by lens aberration occurs in a direction orthogonal to the scan direction (the horizontal direction in FIG. 18), but the same shape is maintained because the lens aberration is the same in the scan direction. It is. For example, the side 8a parallel to the scanning direction in the transfer pattern 8 can be misaligned with respect to the side 7a parallel to the scanning direction in the design pattern 7, but the amount of deviation is the same in the scanning direction. Further, the side 8b perpendicular to the scanning direction in the transfer pattern 8 substantially overlaps the side 7b perpendicular to the scanning direction in the design pattern 7, and no positional deviation is observed. That is, in the exposure process using the scanner, the patterns of the transfer areas 9a and 9b have substantially the same deformation in the direction orthogonal to the scanning direction, and are formed in the same shape in the scanning direction. Therefore, even if the transfer regions 9a and 9b are double-exposed on the same region on the substrate to be exposed such as the wafer 3, it can be formed with high overlay accuracy. The present invention utilizes this characteristic.

  Next, still another problem studied by the present inventors will be described. FIG. 19A is a plan view of an essential part of the mask 64 in which the groove shifter 2d is formed, and FIG. 19B is a sectional view taken along line AA in FIG.

  In the transfer region 65, for example, a line and space of 150 nm is arranged. A groove shifter 67 is disposed on one of the light transmission patterns 66 adjacent to each other. Defects 68a and 68b exist in the transfer region 65. The planar dimension of the defect 68b is relatively larger than that of the defect 68a.

  FIG. 19C shows the result of scanning exposure of such a transfer region 65 without performing double exposure processing (ie, single exposure). In this case, in addition to the normal photoresist pattern 69, the remaining photoresists 70a and 70b resulting from the defects 68a and 68b of the mask 64 were transferred. Among these, the remaining photoresist 70b was a cause of short-circuit failure between patterns. The broken line in FIG. 19C indicates the light transmission pattern 66 so that the relative positional relationship between the photoresist pattern 69 and the remaining photoresist 70b and the light transmission pattern 66 and the defects 68a and 68b of the mask 64 can be understood. In addition, the defects 68a and 68b are shown.

In contrast, in the double exposure method according to the first embodiment, the result shown in FIG. 20 was obtained. 20A is a plan view of transfer regions 4A1 and 4B2 formed at different planar positions on the same plane of the same mask 2, and FIG. 20B is a cross-sectional view taken along lines AA and BB in FIG. Is shown. In the transfer areas 4A1 and 4B1, the same mask pattern is arranged, but the arrangement of the groove shifter 2d is opposite (the phase is inverted by 180 degrees) as described above. The defects 68a and 68b are present in the transfer area 4A1. The dimensions of the line and space are the same as the mask of FIG. By the way, in the exposure process of the first embodiment, since the transfer regions 4A1 and 4B1 as described above are overexposed with a 1/2 exposure amount, a defective portion and a portion where no defect exists are subjected to multiple exposure. It will be. As a result, it is possible to reduce or completely eliminate the transfer of defects on the mask 2. The transfer result is shown in FIG.

  In the position S1 corresponding to the defect 68a in the transfer area 4A1 of the mask 2, no deformation of the photoresist pattern 10a was confirmed. On the other hand, at the position S2 corresponding to the defect 68b in the transfer region 4A1 of the mask 2, deformation of the photoresist pattern 10a (resist remaining 11) was observed, but it was found that no short-circuit defect between the patterns was reached. . Such a pattern defect can be corrected by a correction process using an energy beam such as FIB (Focused Ion Beam) if necessary as a result of the inspection. In this case, since the amount of pattern deformation can be made relatively small, the correction can be facilitated. The broken line in FIG. 20C indicates the light transmission pattern so that the relative positional relationship between the photoresist pattern 10a and the remaining resist 11 and the light transmission pattern 2c and the defects 68a and 68b of the photomask 4A1 can be understood. 2c and defects 68a and 68b are shown.

  As described above, according to the multiple exposure processing of the first embodiment, it is possible to average or remove defects randomly present in the transfer region of the mask 2, thereby suppressing or preventing transfer of the defects of the mask 2. Even if a defect is transferred, the transfer limit of the defect can be expanded. For example, in the stepper, a defect of 0.2 μm or more on the photomask is transferred, but in the first embodiment, a larger defect of 0.4 μm or more on the photomask 4 is transferred. That is, since the defects of less than 0.4 μm on the mask 2 can be ignored, the size limit of the defect inspection can be relaxed. That is, the defect inspection and defect correction of the mask 2 can be facilitated. Therefore, the ease of manufacturing the mask 2 can be improved.

  Further, the inventors investigated the influence of defects on the mask 2 on the size of the transfer pattern when the number of multiple exposures in the exposure process of the first embodiment was increased. The exposure conditions in this case are the same as those described in the description of the exposure apparatus 1. FIG. 21 shows a plan view of the main part of the transfer regions 4A2 and 4B2 of the mask 2 used at this time. FIG. 21A shows a plan view of the main part of the transfer area 4A2 where the defect exists, and FIG. 21B shows a plan view of the main part of the transfer area 4B2 where the defect does not exist. In the transfer regions 4A2 and 4B2 in FIGS. 21A and 21B, a plurality of planar rectangular light transmission patterns 2c1 and 2c2 arranged so that their long sides are parallel to each other are arranged. Yes. The width b of the light transmission patterns 2c1 and 2c2 and the space dimension c between adjacent ones are, for example, about 0.25 μm. However, FIG. 21A shows, for example, the following three types of defects. That is, for example, a planar square-shaped transparent defect 68c having a side dimension smaller than the space dimension, a planar rectangular transparent defect 68d having a long side dimension equal to the space dimension, and a side dimension smaller than the width. It is a light-shielding defect 68e having a planar square shape. The size of the defect is indicated by the variable a. In the exposure process, the pattern of FIG. 21A in which defects exist and the pattern of FIG. 21B in which defects do not exist are overlapped and exposed multiple times. Then, the dimensions of the transfer pattern with respect to the dimensions b1 to b3 of the light transmission patterns 2c1 and 2c2 were evaluated. The evaluation results are shown in FIG.

  22A to 22C show the measurement results of the dimensions b1 to b3, respectively. 22A to 22C, when the single exposure is performed only in the defective transfer area 4A2 in FIG. 21A, the double is the same as the defective transfer area 4A2 in FIG. When the transfer area 4B2 having no defect of (b) is overlaid and exposed, the triple is exposed to the above double exposure and the transfer area 4B2 of FIG. FIG. 21B shows a case where the transfer area 4B2 having no defect is further exposed for exposure. It can be seen that in any defect, the influence of the defect decreases as the number of times of overlapping the defect-free pattern increases. In addition, although the case where the evaluation was made by paying attention to the dimension of the pattern is described here, as a result of the evaluation of the pattern disconnection, the short-circuit, etc., the occurrence of the disconnection, the short-circuit occurs regardless of the size of the defect in the triple exposure or more. We were able to prevent. In the first embodiment, since the phase shift mask is used, the number of overlays is preferably an even number in consideration of the occurrence of phase inversion.

  Further, according to the multiple exposure method of the first embodiment, the dimensional distribution accuracy of the pattern transferred onto the wafer can be improved. This will be described with reference to FIGS. FIG. 23 shows the result of exposure with a scanner (ie, one exposure) without performing double exposure processing. The positions S1 to S4 are one chip, and the positions S5 to S8 are another chip. The dimensional distribution is affected by the dimensional distribution of the mask, and the central portion of the chip is thinly formed. The difference between the maximum dimension and the minimum dimension is, for example, about 0.063 μm. On the other hand, in the multiple exposure method of the first embodiment, as shown in FIG. 24, the positions S1 to S4 and the positions S5 to S8 in FIG. The dimensional distribution accuracy of the pattern could be improved. Here, the difference between the maximum dimension and the minimum dimension was, for example, 0.036 μm. That is, the dimensional variation could be reduced to about half.

  In the first embodiment in which multiple exposure processing is performed under the above exposure conditions, for example, a pattern of 0.25 μm can be satisfactorily formed with an accuracy of 0.25 ± 0.02 μm on the entire surface of the chip. In addition, the occurrence of short-circuit defects between patterns due to defects in the mask 2 was not recognized.

  Next, the manufacturing method of the mask 2 of this Embodiment 1 is demonstrated. First, prior to the manufacturing method of the mask 2 according to the first embodiment, problems in mask manufacturing studied by the present inventors will be described.

  FIG. 25 shows a cross-sectional view of the main part in the mask manufacturing process studied by the present inventors. In this technique, first, as shown in FIG. 25A, a light shielding pattern 81 and a light transmission pattern 82 are formed on a mask substrate 80 by a normal method. The light shielding pattern 82 is made of chromium (Cr) or the like. Subsequently, as shown in FIG. 25B, after a shifter forming resist pattern 83 is formed on the mask substrate 80 by a normal method, the mask substrate 80 exposed from the resist pattern 83 is dug by dry etching. Then, the phase shifter forming groove 84 is formed. Here, when it is difficult to control the phase difference to 180 degrees with high accuracy, the resist pattern 83 is removed as shown in FIG. 25C, and then the phase difference is measured to determine the next target etching amount. decide. Thereafter, as shown in FIG. 25D, a resist pattern 85 for forming a shifter is formed again on the mask substrate 80 by a normal method, and a wet etching process is performed on the mask substrate 80 with a target etching amount. At this time, the lower portion of the light shielding pattern 81 is also etched by isotropic etching such as wet etching. Thus, the fine saddle-shaped groove shifter 86 is formed. Finally, by removing the resist pattern 85, a mask structure having a desired mask pattern and a groove shifter 86 is completed as shown in FIG.

  As described above, in a mask having a groove shifter, high accuracy is required for phase control (that is, groove depth). Since the depth of the groove shifter depends on the exposure wavelength, it tends to become shallower because the exposure wavelength is shortened due to the demand for pattern miniaturization. Therefore, although it seems to be easy to dig a groove, in reality, the error range allowed for the groove is determined and constant with respect to the depth of the groove, so the depth accuracy of the groove shifter itself remains severe. For this reason, it is difficult to manufacture a mask. In addition, the mask manufacturing process is complicated in order to realize the highly accurate phase control and the formation of the ridge shape. As a result, an increase in the number of mask manufacturing processes and a decrease in yield are serious problems.

  Next, an example of a method for manufacturing the mask 2 of the first embodiment will be described with reference to FIGS. 27 and 28 along the process of FIG.

  First, in the mask pattern forming step, as shown in FIG. 27A, a light shielding film made of, for example, chromium is deposited on the entire main surface of the mask substrate 2a by a sputtering method or the like (step 201). Subsequently, a photoresist film is applied on the light shielding film and then patterned to form a predetermined photoresist pattern (step 202). Thereafter, the light shielding film portion exposed from the photoresist pattern is removed by an etching method or the like, thereby forming the light shielding pattern 2b and the light transmission pattern 2c (step 203). Subsequently, after removing the photoresist pattern (step 204), the pattern is inspected for defects (step 205). Thereafter, those that can be corrected based on the inspection result are corrected (step 206). The steps up to here are the same as the mask manufacturing technique studied by the inventors.

  Next, in the phase shifter forming step, a photoresist film is applied on the formation surface of the light shielding pattern 2b on the mask substrate 2a, and then the photoresist film is patterned as shown in FIG. A photoresist pattern 12 is formed so that the predetermined light transmission pattern is exposed and the others are covered (step 207). Subsequently, using the photoresist pattern 11 as an etching mask, the mask substrate 2a exposed therefrom is etched by an anisotropic dry etching method, thereby forming a groove shifter 2d (step 208). Then, after removing the photoresist pattern 12 as shown in FIG. 27C (step 209), the phase of the transmitted light of the mask 2 is inspected (step 210), and the mask 2 is manufactured.

  As described above, in the first embodiment, since the accuracy of the absolute value control (allowable error) of the phase difference of the mask can be relaxed as described above, the phase difference is measured during the manufacturing process of the mask 2. Therefore, the step of forming the photoresist pattern for forming the groove shifter can be performed only once. Further, in the first embodiment, the difference in light intensity with and without the groove shifter can be canceled by multiple exposure, so there is no need to form a ridge in the light shielding pattern. Therefore, in the first embodiment, the manufacturing process of the mask 2 can be simplified as compared with the technique studied by the inventors. That is, since the number of manufacturing steps of the mask 2 can be reduced, the manufacturing time of the mask 2 can be shortened. In addition, the yield of the mask 2 can be improved.

  If the difference in light intensity adversely affects the resolution characteristics due to the presence or absence of an extreme shifter, isotropic wet etching is performed on the entire surface of the mask 2 after the inspection step 210 as shown in FIG. Is effective. That is, by performing wet etching on both the groove shifter 2d and the portion where the groove shifter 2d is not disposed, a ridge structure is formed (step 211a). This is a method of manufacturing the mask 2 having the structure shown in FIG. In this case, the difference in light intensity with and without the groove shifter 2d can be reduced, and degradation of the resolution characteristics can be prevented.

  Further, in the first embodiment, since the absolute value control accuracy of the phase can be relaxed as described above, after the groove forming step 208, the photoresist pattern 12 used as a mask when processing the groove shifter 2d (FIG. 27 ( An eaves structure may be formed by performing an isotropic wet etching process on the mask 2 using (see b)) as a mask (step 211b). This is a method for manufacturing the mask 2 having the structure shown in FIG. Although the structure is the same as that shown in FIG. 25 (e) studied by the present inventors, in the first embodiment, the photoresist film application and patterning steps can be performed once. In addition, the manufacturing process of the mask 2 can be simplified.

  Next, FIG. 29 and FIG. 30 show an example in which the technical idea of the present invention is applied to the case where each pattern of a DRAM (Dynamic Random Access Memory) is transferred by exposure processing. 30 is a cross-sectional view taken along line AA of FIG. By applying the exposure method of the present embodiment to the DRAM manufacturing technique, in particular, the number of defects in the chip can be reduced, so that the number of bit relief chips can be reduced.

  The semiconductor substrate 3S is a portion constituting a planar square chip of a DRAM cut out from the wafer 3 having a substantially circular plane, for example, and is made of, for example, p-type single crystal silicon. A p-type well 21 is formed on the main surface of the semiconductor substrate 3S, and a DRAM memory cell is formed in the p-type well 21. Note that the p-type well 21 in the region (memory array) in which the memory cells are formed is formed in the lower portion thereof in order to prevent noise from entering from an input / output circuit or the like formed in another region of the semiconductor substrate 3S. The n-type semiconductor region 22 is electrically isolated from the semiconductor substrate 3S.

  The memory cell has a stacked structure in which an information storage capacitive element C is arranged above the memory cell selection MISFETQs. The memory cell selection MISFET Qs is composed of an n-channel type MISFET and is formed in the active region L of the p-type well 21. The active region L is configured by an elongated island pattern that extends straight along the X direction in FIG. 29, and one of the source and drain (n-type semiconductor region) is connected to each active region L. Two shared memory cell selection MISFETs Qs are formed adjacent to each other in the X direction.

  The element isolation region surrounding the active region L is constituted by a groove type element isolation portion (trench isolation) 23 formed by embedding an insulating film made of a silicon oxide film or the like in a shallow groove opened in the p-type well 21. Yes. The insulating film embedded in the groove type element isolation portion 23 is flattened so that the surface thereof is almost the same height as the surface of the active region L. The element isolation region constituted by such a trench type element isolation part 23 is formed by a LOCOS (Local Oxidization of Silicon) method because a bird's beak cannot be formed at the end of the active region L. The effective area of the active region L is larger than that of the element isolation region (field oxide film) having the same size.

  The memory cell selecting MISFET Qs is mainly composed of a gate insulating film 24, a gate electrode 25, and a pair of n-type semiconductor regions 26 and 26 constituting a source and a drain. The gate electrode 25 is configured integrally with the word line WL, and extends linearly along the Y direction with the same width and the same space. The gate electrode 25 (word line WL) is a barrier metal made of a low resistance polycrystalline silicon film doped with an n-type impurity such as P (phosphorus), and a WN (tungsten nitride) film formed thereon. It has a polymetal structure composed of a layer and a refractory metal film such as a W (tungsten) film formed thereon. Since the gate electrode 25 (word line WL) having a polymetal structure has a lower electrical resistance than a gate electrode made of a polycrystalline silicon film or a polycide film, the signal delay of the word line can be reduced. However, the gate electrode 25 may be composed of a single film of a polycrystalline silicon film, or may have the polycide structure in which a silicide film such as tungsten silicide is stacked on the polycrystalline silicon film.

  A cap insulating film 27 made of a silicon nitride film or the like is formed on the gate electrode 25 (word line WL) of the memory cell selecting MISFET Qs. The upper and side walls of the cap insulating film 27 and the gate electrode 25 (word line) are formed. An insulating film 28 made of, for example, a silicon nitride film is formed on the sidewall of (WL). The cap insulating film 27 and the insulating film 28 of the memory array are etching stoppers for forming contact holes by self-alignment (self-alignment) above the source and drain (n-type semiconductor regions 26, 26) of the memory cell selection MISFET Qs. Used as.

  An SOG (Spin On Glass) film 29a is formed on the memory cell selection MISFETQs. Further, insulating films 29b and 29c made of two layers of silicon oxide or the like are formed further above the SOG film 29a, and the surface of the upper insulating film 29c has almost the same height throughout the semiconductor substrate 3S. It has been flattened.

  Contact holes 30a and 30b penetrating the insulating films 29c and 29b and the SOG film 29a are formed above the pair of n-type semiconductor regions 26 and 26 constituting the source and drain of the memory cell selection MISFET Qs. Embedded in these contact holes 30a and 30b are plugs 31 made of a low-resistance polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)). The diameters in the X direction at the bottoms of the contact holes 30a and 30b are defined by the space between the insulating film 28 on one side wall and the insulating film 28 on the other side wall of the two opposing gate electrodes 25 (word lines WL). Yes. That is, the contact holes 30a and 30b are formed by self-alignment with respect to the gate electrode 25 (word line WL).

  As shown in FIG. 29, the diameter of one contact hole 30b in the Y direction (vertical direction in FIG. 29) of the pair of contact holes 30a and 30b is substantially the same as the dimension of the active region L in the Y direction. On the other hand, the diameter in the Y direction of the other contact hole 30a (the contact hole on the n-type semiconductor region 26 shared by the two memory cell selection MISFETs Qs) is larger than the dimension of the active region L in the Y direction. Is also big. That is, the contact hole 30b has a substantially rectangular plane pattern in which the diameter in the Y direction is larger than the diameter in the X direction (left and right direction in FIG. 29). It extends planarly on the element isolation part 23. By configuring the contact hole 30a with such a pattern, when the bit line BL and the n-type semiconductor region 26 are electrically connected via the contact hole 30a, the width of the bit line BL is partially increased. Therefore, it is not necessary to extend to the upper part of the active region L or to extend a part of the active region L in the bit line BL direction, so that the memory cell size can be reduced.

  An insulating film 32a is formed on the insulating film 29c. A through hole 33 is formed in the insulating film 32a on the contact hole 30a, and a plug made of a conductive film in which a Ti (titanium) film, a TiN (titanium nitride) film, and a W film are stacked in that order from the lower layer is formed therein. Embedded. The through hole 33 is disposed above the trench type element isolation portion 23 that is out of the active region L.

  A bit line BL is formed on the insulating film 29c. The bit line BL is disposed above the groove type element isolation portion 23 and extends linearly along the X direction with the same width and the same space. The bit line BL is made of, for example, a tungsten film, and for selecting a memory cell through the through hole 33 and the contact holes 30a formed in the insulating films 32a, 29c and 29b, the SOG film 29a and the gate insulating film 24 therebelow. The MISFET Qs is electrically connected to one of the source and the drain (the n-type semiconductor region 26 shared by the two memory cell selection MISFETs Qs). By forming the bit line BL with metal (tungsten), the sheet resistance can be reduced, so that reading and writing of information can be performed at high speed. In addition, since the bit line BL and the wiring of the peripheral circuit can be formed at the same time in the same process, the manufacturing process of the DRAM can be simplified. In addition, by forming the bit line BL from a metal (tungsten) having high heat resistance and high electromigration resistance, disconnection can be reliably prevented even when the width of the bit line BL is reduced.

On the bit line BL, insulating films 32b and 32c made of, for example, silicon oxide are formed. The upper insulating film 32c is planarized so that the surface thereof has substantially the same height over the entire area of the semiconductor substrate 3S. An insulating film 34 made of silicon nitride or the like is formed on the insulating film 32c of the memory cell array, and an information storage capacitor element C is formed on the insulating film 34. The information storage capacitive element C includes a lower electrode (storage electrode) 35a, an upper electrode (plate electrode) 35b, and a capacitive insulating film (dielectric film) made of Ta ₂ O ₅ (tantalum oxide) or the like provided therebetween. 35c. The lower electrode 35a is made of, for example, a low resistance polycrystalline silicon film doped with P (phosphorus), and the upper electrode 35b is made of, for example, a TiN film. The lower electrode 35a of the information storage capacitive element C is electrically connected to the plug 31 in the contact hole 30b through the plug 37 embedded in the through hole 36 penetrating the insulating film 34 and the underlying insulating films 32c, 32b, 32a. And is further electrically connected to the other of the source and drain (n-type semiconductor region 26) of the memory cell selection MISFET Qs through the plug 31.

  An insulating film 38 made of two layers of silicon oxide or the like is formed on the information storage capacitor C, and a second-layer wiring 39L2 is formed on the insulating film 38. Insulating films 40a and 40b made of two layers of silicon oxide or the like are formed on the second-layer wiring 39L2. Among these, the lower insulating film 40a is formed by a high density plasma (CVD) method excellent in the gap fill property of the wiring 39L2. Further, the insulating film 40b thereon is flattened so that the surface thereof is almost the same height over the entire area of the semiconductor substrate 3S. A third layer wiring 39L3 is formed on the insulating film 40b. The second and third-layer wirings 39L2 and 39L3 are made of a conductive film mainly composed of, for example, an Al (aluminum) alloy.

  As described above, according to the first embodiment, the following effects can be obtained.

  (1). The same pattern of the mask 2 but the pattern in which the phase of the transmitted light is inverted by 180 degrees is overlaid and exposed on the same area of the wafer 3, thereby allowing the phase error of the mask 2 having the groove shifter 2d. Capacitance (accuracy control accuracy of phase difference) can be relaxed.

  (2). By superposing and exposing the same pattern of the mask 2 on the same area of the wafer 3, the critical dimension for defect inspection of the mask 2 having the groove shifter 2d can be relaxed.

  (3). The same pattern of the mask 2 but the pattern in which the phase of the transmitted light is inverted by 180 degrees is overlaid and exposed on the same area of the wafer 3 so that the adjacent transfer pattern depending on the presence or absence of the groove shifter 2d is formed. It becomes possible to suppress or prevent dimensional variation.

  (4) By the above (3), the groove shifter 2d of the mask 2 does not need to have a ridge structure.

  (Five). With the above (1), (2) or (4), it is possible to improve the ease of manufacturing the mask 2.

  (6) The manufacturing yield of the mask 2 can be improved by the above (1), (2), (3), (4) or (5).

  (7) By superimposing and exposing the same pattern of the mask 2 on the same area of the wafer 3, the mask pattern dimension distribution in the mask 2 can be averaged. It becomes possible to suppress or prevent dimensional variation.

  (8). During the scanning exposure, the same pattern of the mask 2 is repeatedly exposed along the scanning direction, whereby the lens aberration of the optical system of the exposure apparatus 1 can be averaged.

  (9) By the above (1), (7), (8), etc., it becomes possible to improve the dimensional accuracy of the transfer pattern.

  (10) With the above (1), (7), (8), (9), etc., the yield of the semiconductor integrated circuit device can be improved.

  (11) The reliability of the semiconductor integrated circuit device can be improved by the above (1), (7), (8), (9) and the like.

  (12) The performance of the semiconductor integrated circuit device can be improved by the above (1), (7), (8), (9) and the like.

  (13) With the above (1), (7), (8), (9), etc., it becomes possible to improve the degree of integration of elements and wirings of the semiconductor integrated circuit device.

(Embodiment 2)
According to the investigation results of the present inventors, in the phase shift mask in which the auxiliary mask pattern is arranged around the main light transmission pattern, the groove shifter is arranged, specifically, the groove shifter is used as the main light transmission pattern. It was newly found that the resolution dimension of the transferred pattern differs depending on whether it is arranged in the pattern or in the auxiliary pattern. As described above, the auxiliary mask pattern is an opening pattern for improving the resolution characteristics of the main light transmission pattern, and does not form an independent image on the wafer when projected onto the wafer. The light transmission pattern opened in the mask.

  The main part of such a phase shift mask is shown in FIGS.

  FIG. 31A shows a plan view of the main part of the mask 2, and FIG. 31B shows a cross-sectional view taken along line AA of FIG. The light transmission pattern 2c formed in a flat belt shape is formed by opening a light shielding film on the mask substrate 2a. The light transmission pattern 2c is a main pattern transferred onto the wafer by exposure processing. In the vicinity of both long sides of the light transmission pattern 2c, a planar belt-like auxiliary mask pattern 2cs is arranged in parallel to the light transmission pattern 2c with a light shielding pattern 2b having a predetermined plane length therebetween. The auxiliary mask pattern 2cs is formed by opening a light shielding film on the mask substrate 2a in order to improve the resolution characteristics of the light transmission pattern 2c. The length in the longitudinal direction of the auxiliary mask pattern 2cs is the same as the length in the longitudinal direction of the light transmission pattern 2c, but its width is designed to be narrower than that of the light transmission pattern 2c so as not to be transferred onto the wafer. . In FIG. 31, the groove shifter 2d is arranged in the auxiliary mask pattern 2cs so that the phase is inverted by 180 degrees between the light transmitted through the light transmission pattern 2c and the light transmitted through the auxiliary mask pattern 2cs.

  On the other hand, FIG. 32A shows a plan view of the main part at different plane positions in the same plane of the mask 2 of FIG. 31, and FIG. The shapes, dimensions, functions, and the like of the light transmission pattern 2c and the auxiliary mask pattern 2cs are the same as those in FIG. However, in FIG. 32, the groove shifter 2d is arranged in the light transmission pattern 2c so that the phase is inverted by 180 degrees between the light transmitted through the light transmission pattern 2c and the light transmitted through the auxiliary mask pattern 2c. That is, in FIGS. 31 and 32, when the phases of transmitted light at the same plane position of the mask 2 are compared, the phases of the respective lights are inverted by 180 degrees.

  According to the investigation results of the present inventors, it has been newly found that the size of the transfer pattern differs between FIG. 31 and FIG. 32 when the exposure process is performed once using such a mask 2. Therefore, in the second embodiment, as in the first embodiment, the mask pattern shown in FIG. 31 and the mask pattern shown in FIG. 32 are over-exposed (multiple exposure) on the same area of the wafer. Therefore, the dimensional accuracy of the pattern transferred to the wafer can be greatly improved for the same reason as described in the first embodiment.

(Embodiment 3)
In the third embodiment, an application example to a hole pattern will be described. The hole pattern is a hole pattern that is drilled in an insulating film in order to electrically connect different layers such as contact holes and through holes.

  FIG. 33 (a) shows a plan view of the main part of the mask 2, and FIGS. 33 (b) and (c) show cross-sectional views taken along lines AA and BB in FIG. The mask 2 shows two transfer areas 4E and 4F to be overlaid during the exposure process. The transfer areas 4E and 4F are arranged at different plane positions on the same plane of the same mask 2. In the transfer regions 4E and 4F, for example, a planar square light transmission pattern 2c3, an auxiliary mask pattern 2cs surrounding the four circumferences, and a plurality of planar square light transmission patterns 2c4 are arranged.

  The light transmission pattern 2c3 is a pattern for transferring the isolated hole pattern, and is formed by opening a light shielding film on the mask substrate 2a. The auxiliary pattern 2cs is a pattern for the purpose of improving the resolution of the light transmission pattern 2c3, and is formed with a pattern width equal to or smaller than the resolution limit. In the light transmission pattern 2c3 and the auxiliary mask pattern 2cs, the groove shifter 2d is arranged on either side so that the phase of the light transmitted through each pattern is inverted by 180 degrees. In this case, in the transfer region 4E, the groove shifter 2d is disposed in the auxiliary mask pattern 2cs, and in the transfer region 4F, the groove shifter 2d is disposed in the light transmission pattern 2c3. That is, in the transfer region 4E and the transfer region 4F in the formation region of the light transmission pattern 2c3 and the auxiliary mask pattern 2cs, when the phases of the transmitted light at the same plane position are compared, the phases of the respective lights are inverted by 180 degrees. It is like that.

  Further, the light transmission pattern 2c4 is a pattern for transferring the densely arranged hole pattern, and a plurality of the light transmission patterns 2c4 are regularly arranged at predetermined intervals in the vertical and horizontal directions of FIG. In the plurality of light transmission patterns 2c4, the groove shifter 2d is arranged so that the phase of the light transmitted through each of the light transmission patterns 2c4 adjacent to each other is inverted by 180 degrees. In this case, in the group of the plurality of light transmission patterns 2c4, when the phase of the transmitted light at the same plane position is compared between the transfer region 4E and the transfer region 4F, the phase of each light is inverted by 180 degrees. It has become.

  By exposing the transfer areas 4E and 4F to the same area on the wafer (multiple exposure), a fine hole pattern can be formed on the wafer with high dimensional accuracy for the same reason as described in the first embodiment. It becomes possible to transfer it upward.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the first to third embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to third embodiments, the case where the same mask pattern in the same plane of the same mask and the same mask pattern at different plane positions are overexposed has been described. However, the present invention is not limited to this. The same mask pattern formed on the mask may be overexposed.

  The exposure conditions are not limited to those described in the first to third embodiments, and can be variously changed. For example, i-line having an exposure wavelength of 365 nm may be used as exposure light. As illumination, modified illumination such as oblique illumination and annular illumination may be used.

  In the above description, the case where the invention made by the present inventor is applied to the DRAM which is the field of use behind the present invention has been described. However, the present invention is not limited to this. For example, SRAM (Static Random Access Memory) or flash A semiconductor integrated circuit device having a memory circuit such as an EEPROM (Electric Erasable Programmable Read Only Memory), a semiconductor integrated circuit device having a logic circuit such as a microprocessor or the like, or the memory circuit and the logic circuit on the same semiconductor substrate The present invention can also be applied to a mixed type semiconductor integrated circuit device provided in the above. In particular, this technique is effective when applied to a lithography technique using a phase shift mask in a state-of-the-art product with a minimum processing dimension of 0.15 μm or less.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is explanatory drawing which showed the schematic manufacturing process of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. FIG. 2 is an explanatory view showing an example of an exposure apparatus used in the method for manufacturing the semiconductor integrated circuit device of FIG. 1. It is explanatory drawing which extracted and showed the principal part of the exposure apparatus of FIG. It is the top view which showed typically the exposure area | region of the exposure apparatus of FIG. 2 and FIG. It is the top view which showed typically the exposure area | region of a stepper. (A) is a whole top view of an example of the mask used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention, (b) and (c) are the AA line and B of (a), respectively. It is sectional drawing of a -B line. (A)-(c) is principal part sectional drawing of the various masks of FIG. (A)-(c) is principal part sectional drawing of the various masks of FIG. It is explanatory drawing for demonstrating the exposure process process in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. (A) is a partial sectional view of the phase shift mask studied by the present inventor, (b) is a graph showing the intensity distribution of transmitted light of the phase shift mask of (a), and (c) is the phase shift of (a). It is a top view of the pattern transcribe | transferred with the mask. (A) is a partial sectional view of another phase shift mask examined by the present inventors, (b) is a graph showing the intensity distribution of transmitted light of the phase shift mask of (a), and (c) is a graph of (a). It is a top view of the pattern transcribe | transferred by the phase shift mask. In the exposure process using the phase shift mask which the present inventors examined, it is a graph which shows the relationship between the dimension of a line and space (pattern) and the dimension difference of the transfer pattern in each dimension. It is the graph obtained by simulating the light intensity distribution of the exposure process in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of the present invention. It is the graph obtained by simulating the light intensity distribution of the exposure process which the present inventors examined. (A) is a plan view of two transfer regions on which masks used in the exposure process in the manufacturing method of a semiconductor integrated circuit device according to one embodiment of the present invention are superimposed, and (b) is an AA line in (a). And (B) is a graph showing the intensity distribution of the light transmitted through each transfer region in (a), and (d) is a case where each transfer region in (a) is overexposed. It is a graph which shows the light intensity distribution obtained in [3]. FIG. 5 is an explanatory view schematically showing that a positional deviation occurs in a transfer pattern when exposure processing is performed using a stepper, which is a technique studied by the present inventors. (A), (b) is the technique which this inventor examined, and is explanatory drawing which shows typically a mode that the transcription | transfer area | region of a different plane position coordinate on a photomask was transcribe | transferred using the stepper. FIG. 5 is an explanatory diagram schematically showing a state in which a transfer area having different plane position coordinates on a photomask is transferred using a scanner, which is the technical idea of the present invention. (A) is a plan view of the main part of the transfer area of the mask, (b) is a cross-sectional view taken along line AA of (a), and (c) is a photomask of (a) once during the exposure process using a scanner. It is a top view of the photoresist pattern at the time of exposing. (A) is a plan view of an essential part of two transfer regions of the mask, (b) is a cross-sectional view taken along the lines AA and BB in (a), and (c) is a 2 in (a) using a scanner. It is a top view of the photoresist pattern at the time of overlapping and exposing the transfer area | region of a location. (A) is a principal part top view of the transfer area | region where a defect exists in a mask, (b) is a principal part top view of the transfer area | region where a defect does not exist in a mask. (A) to (c) in the case of using only the mask of FIG. 21 (a) and exposing the masks of FIGS. 21 (a) and (b) twice or more in the exposure process by the scanner. It is a graph which shows the evaluation result of the dimension of the transferred pattern. It is a graph which shows the pattern dimension distribution precision at the time of exposing a photomask once in the exposure process using a scanner. It is a graph which shows the pattern dimension distribution precision at the time of carrying out multiple exposure at the time of the exposure process using a scanner. (A)-(e) is the fragmentary sectional view in the manufacturing process of the mask which the present inventors examined. It is a flowchart of the manufacturing process of the mask used with the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. (A)-(c) is principal part sectional drawing in the manufacturing process of the mask of FIG. FIG. 27 is an essential part cross sectional view of the mask of FIG. 26 during a manufacturing step. It is a principal part top view of the semiconductor integrated circuit device manufactured by applying the exposure method in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is sectional drawing of the AA line of FIG. (A) is a principal part top view of the mask used with the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention, (b) is sectional drawing of the AA of (a). (A) is a principal part top view of the other plane position in the mask of FIG. 31, (b) is sectional drawing of the AA of (a). (A) is a principal part top view of the mask used with the manufacturing method of the semiconductor integrated circuit device which is further another embodiment of this invention, (b) and (c) are the AA line and B of (a). It is sectional drawing of a -B line.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Exposure apparatus 1a Exposure light source 1b Fly eye lens 1c Aperture 1d1, 1d2 Condenser lens 1e Mirror 1f Aperture 1fs Slit 1g Projection lens 1ga Effective exposure area 1h Mask position control means 1i1 Mirror 1i2 Mask stage 1j X stage 1k Z stage 1m Z stage Main control system 1p, 1q Driving means 1r Mirror 1s Laser length measuring device 1t Alignment detection optical system 1u Network device 2 Mask 2a Mask substrate 2b Light shielding pattern 2c Light transmission pattern 2c1, 2c2 Light transmission pattern 2c3, 2c4 Light transmission pattern 2cs Auxiliary mask Pattern 2d Groove shifter 2e Light transmission pattern 2f Groove 2g Shifter film 2p Pellicle 3 Wafer 3S Semiconductor substrate 4A, 4B Transfer area 4A1, 4B1 Transfer area 4A2 , 4B2 transcription region 4C, 4D transcription region 5A-5E region 5A1, 5A2 transcription region 5B1, 5B2 transcription region 5C1, 5C2 transcription region 5D1, 5D2 transcription region 5E1, 5E2 transcription region 6a, 6b light intensity peak 7 design pattern 7a, 7b Side 8 Transfer pattern 8a, 8b Side 9a, 9b Transfer region 10a Photoresist pattern 11 Photoresist remaining 12 Photoresist pattern 21 P-type well 22 N-type semiconductor region 23 Element isolation portion 24 Gate insulating film 25 Gate electrode 26 N-type semiconductor region 27 Cap insulating film 28 Insulating film 29a SOG film 29b, 29c Insulating film 30a, 30b Contact hole 31 Plug 32a-32c Insulating film 33 Through hole 34 Insulating film 35a Lower electrode 35b Upper electrode 35c Capacitive insulating film 36 S -Hole 37 plug 38 insulating film 39L2 wiring 50 phase shift mask 50a mask substrate 50b light shielding pattern 50c light transmission pattern 50d groove shifter 60 design pattern 61, 62 transfer pattern 63a, 63b transfer region 64 mask 65 transfer region 66 light transmission pattern 67 groove shifter 68a, 68b Defect 68c, 68d Transparent defect 68e Light shielding defect 69 Photoresist pattern 70a, 70b Photoresist residue 80 Mask substrate 81 Light shielding pattern 82 Light transmission pattern 83 Resist pattern 84 Groove 85 Resist pattern 86 Groove shifter EXL Exposure light CA Chip formation region SA1, SA2 Exposure area Z depth Qs MISFET for memory cell selection
C Information storage capacitor BL Bit line WL Word line

Claims (4)

A method for manufacturing a semiconductor integrated circuit device comprising the following steps:
(A) forming a photoresist film on the first main surface of the wafer;
(B) installing the wafer on which the photoresist film is formed on a wafer stage of an exposure apparatus;
(C) a step of subjecting the first region of the first main surface of the wafer placed on the wafer stage to reduced projection exposure with ultraviolet light to the first phase shift mask pattern;
(D) After the step, a second phase shift mask pattern and the first phase shift with respect to the first region of the first main surface of the wafer placed on the wafer stage. A step of reducing and exposing a mask pattern having a reversed phase with ultraviolet light;
(E) After the step (c), the first phase shift mask pattern is again applied to the first region of the first main surface of the wafer placed on the wafer stage. Reducing projection exposure with light;
(F) After the step (d), the second phase shift mask pattern is again applied to the first region of the first main surface of the wafer placed on the wafer stage with an ultraviolet ray. A process of reducing projection exposure with light. A method for manufacturing a semiconductor integrated circuit device comprising the following steps:
(A) forming a photoresist film on the first main surface of the wafer;
(B) installing the wafer on which the photoresist film is formed on a wafer stage of an exposure apparatus;
(C) A step of subjecting the first region of the first main surface of the wafer placed on the wafer stage to reduced projection exposure with ultraviolet light of a first phase shift mask pattern including an auxiliary pattern;
(D) After the step, a second phase shift mask pattern including an auxiliary pattern with respect to the first region of the first main surface of the wafer placed on the wafer stage. A step of reducing projection exposure of the phase-inverted phase of the phase shift mask pattern of 1 with ultraviolet light. A method for manufacturing a semiconductor integrated circuit device comprising the following steps:
(A) forming a photoresist film on the first main surface of the wafer;
(B) installing the wafer on which the photoresist film is formed on a wafer stage of an exposure apparatus;
(C) For the first region of the first main surface of the wafer placed on the wafer stage, using a first phase shift mask pattern including a groove shifter, using ultraviolet light as exposure light, Scanning exposure by reducing projection;
(D) after the step, a second phase shift mask pattern including a groove shifter for the first region of the first main surface of the wafer placed on the wafer stage, A step of performing scanning exposure by subjecting the phase of the phase shift mask pattern of 1 that has been inverted in phase to reduce projection using ultraviolet light as exposure light. A method for manufacturing a semiconductor integrated circuit device comprising the following steps:
(A) forming a photoresist film on the first main surface of the wafer;
(B) installing the wafer on which the photoresist film is formed on a wafer stage of an exposure apparatus;
(C) reducing and projecting the first phase shift mask pattern on the first region of the first main surface of the wafer placed on the wafer stage using ultraviolet light as exposure light; Scanning exposure by:
(D) After the step, a second phase shift mask pattern and the first phase shift with respect to the first region of the first main surface of the wafer placed on the wafer stage. Scanning exposure by reducing and projecting a mask pattern with the phase inverted, using ultraviolet light as exposure light.

Images