JP2008160804A - Data transfer device and transfer control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain time reduction in device information obtaining process. <P>SOLUTION: A transmitter 102, a controller 103 for controlling the transmitter 102, and a plurality of memory elements 114, 115 are provided. The transmitter 102 comprises a video/audio transmitter 105 for transmitting a video/audio signal to a receiving device 106 outside and a device information obtaining unit 112 for receiving from the receiving device 106 device information, including information relating to a receiving function of the receiving device 106 and transmitting the received information to the controller 103. The plurality of memory elements 114, 115 temporarily stores therein the device information; and the controller 103 performs parallel processing of writing the device information in at least one of the plurality of memory elements 114, 115 and reading the device information from at least one of the rest of the memory elements and controls the transmitter 102, based on the device information sequentially read from the plurality of memory elements 114, 115 in the parallel processing. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data transfer apparatus and a transfer control method, and more particularly, to an apparatus for performing acquisition transfer processing of receiving device information.

  In recent years, HDMI (High-Definition Multimedia Interface) communication has been used to transmit video and audio data from a transmission device such as a DVD player or DVD recorder to a reception device such as a digital TV or an amplifier. When the transmission device detects that the reception device is connected via an HDMI cable, it is called EDID (Extended Display Identification Data) in which the performance (including reception function information) and characteristic data of each reception device are recorded. The data structure is taken out from the counterpart device (reception device) by DDC (Display Data Channel) communication and the performance of the counterpart device is confirmed, and then the video data and audio data suitable for the counterpart connection device are transmitted.

  FIG. 2 shows a flow of transfer of EDID sent from a conventional receiving apparatus to a transmitting apparatus. The transmission apparatus 201 includes a system computer 203 and an HDMI transmission LSI 202 that controls video / audio transmission. The HDMI transmission LSI 202 includes a video / audio transmission unit 205 that performs video / audio transmission, and a DDC buffer 204 that is an area for storing information acquired by DDC communication.

  The system computer 203 is connected to a DDC buffer 204 and a video / audio transmission unit 205 via an I2C (Inter-Integrated Circuit) bus 211. The I2C bus 211 is an interface that enables communication between a plurality of devices using only two signal lines of a serial clock and serial data. Since the I2C bus 211 has a simple structure, it is widely used for internal control of TVs and DVD players.

  The receiving device 206 includes an EDID area 207 that stores EDID, a device information transmission unit 208 that controls EDID transmission, and a video / audio processing unit 209 that performs video / audio processing.

  The transmission device 201 and the reception device 206 are connected via the HDMI cable 210. In the reception device 206, the EDID is read from the EDID area 207 and transmitted to the transmission device 201 via a DDC (Display Data Channel) bus 220 included in a part of the HDMI cable. In the transmission device 201, the received EDID is stored in the DDC buffer 204 inside the HDMI transmission LSI 202. The EDID stored in the DDC buffer 204 is transferred to the system computer 203 via the I 2 C bus 211. The system computer 203 analyzes the transferred EDID. Furthermore, the system computer 203 generates video / audio data suitable for the reception device 206 based on the analysis result, and transmits the video / audio data from the video / audio transmission unit 205 to the reception device 206 via the HDMI cable. The receiving device 206 processes the transmitted video / audio data by the video / audio processing unit 209 and outputs the video / audio.

  When transmitting the audio / video data, the transmitting apparatus 201 performs an EDID information acquisition process of the receiving apparatus 206 before transmitting the content in order to acquire the video / audio information that can be received by the receiving apparatus 206. The EDID acquisition process is performed by DDC communication. The transmission apparatus 201 makes a read request for EDID information to an address specified by the EDID standard (VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA STANDARD). The EDID information is composed of 128-byte blocks, and represents information on the receiving device by combining a plurality of blocks.

  However, the DDC communication used for acquiring device information of the receiving device has a low transfer rate. Therefore, in a system configuration in which a plurality of blocks need to be read, if the reception buffer size for storing DDC information secured in the system is small, the information acquisition process cannot be performed efficiently and the process takes a long time. .

  Furthermore, the EDID information is read from the DDC buffer and analyzed. Therefore, in a system configuration in which EDID information needs to be transferred to the RAM area inside the system using the I2C bus 211, the transfer time by I2C is further added to the processing time.

  For the above reasons, in the system configuration described above, the time required for the EDID information acquisition process becomes long, and the output and audio output are delayed as a whole system.

As a prior art intended to eliminate such inconvenience, there is one described in Patent Document 1. This solves the above inconvenience by holding and managing a plurality of buffers in the system.
JP-A-2005-130520

  However, since the EDID information is distributed and arranged in a plurality of blocks, reading out all the EDID information and analyzing the device information of the receiving apparatus after obtaining all the information results in a heavy processing load. There is a delay in image output and audio output. If the DDC buffer 204 cannot be sufficiently secured in the system shown in FIG. 2, a plurality of EDID information must be read out several times. Then, it is necessary to acquire the EDID while transferring the EDID information acquired in the DDC buffer 204 to another area of the system, and it takes time to acquire the EDID information.

  Therefore, the main object of the present invention is to realize time reduction of the device information acquisition process.

  In order to solve the above problems, in the present invention, after preparing two buffers for storing device information (EDID) transferred from the receiving device, data transfer from the receiving device to the transmitting unit, and from the transmitting unit to the control unit By performing parallel processing with data transfer to (system computer), the device information acquisition processing time can be shortened.

  In order to read out device information from the receiving device via the DDC bus, a slave address and an offset address storing device information to be acquired are transmitted, and a plurality of pieces of device information sent from the receiving device are prepared. A process of sorting and storing the elements (buffers) is performed. In addition, a control register capable of performing processing for writing device information in the storage element by hardware is provided, and device information acquired by setting bits from the control unit to the control register is distributed to and stored in a plurality of storage elements.

  In order to perform parallel processing in the above configuration, when data stored in at least one of the plurality of storage elements is read and transferred to the control unit, the device information acquired from the receiving device is stored in at least one other When writing to the storage element and reading the data stored in the at least one other storage element and transferring it to the control unit, the device information acquired from the receiving device is written to the device information in the at least one storage element. In addition, the processing order is controlled. By controlling the processing order, data transfer from the receiving device to the transmission unit and data transfer from the transmission unit to the control unit can be performed in parallel.

  Further, in the process of device information acquisition processing, when a receiving apparatus accesses a region where data is not mounted by DDC communication and a DDC communication error occurs, the cause of the error is investigated, so that the DDC communication It is determined whether the error is caused by accessing the data unimplemented area (address error). Based on this determination, appropriate processing is selected as a system so that error processing can be continued if it is an error in DDC communication, and normal processing can be continued if it is an address error.

  Further, in order to avoid a DDC communication error due to access to the unmounted area of the receiving apparatus, in the present invention, device information that can recognize the presence / absence of the data unmounted area and its position is acquired from the receiving apparatus in advance. Then, based on the acquired device information for recognizing the unmounted data area, the control unit controls the device information acquiring device so that the device information acquiring operation is not performed on the unmounted data area.

  The present invention has the above-described configuration and can perform high-speed and accurate device information acquisition processing while analyzing errors that occur during DDC communication between transmitting and receiving apparatuses.

  Hereinafter, embodiments of a data transfer apparatus and a transfer control method according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram illustrating a state in which a video / audio transmission device 101 such as a DVD player or a DVD recorder and a reception device 106 such as a digital TV or an AV amplifier are connected via a first interface 110 (HDMI).

  The video / audio transmission apparatus includes a control unit (such as a microcomputer) 103 that controls the system and a transmission unit 102 that controls video / audio to be transmitted. The transmission unit 102 includes a video / audio transmitter 105, a device information acquisition unit 112, and a control register 113.

  The video / audio transmitter 105 plays a role of a TMDS transmitter that starts / stops transmission of video / audio data using a transmission method called TMDS (Transition Minimized Differential Signaling). The device information acquisition unit 112 is a DDC input / output control unit that acquires device information (including reception function information) of a partner device such as EDID via a DDC (Display Data Channel) bus that is a part of the first interface 110. To play a role. The control register 113 controls the device information acquisition unit 112.

  The device information acquisition unit 112 includes a first storage element 114 and a second storage element 115. These storage elements 114 and 115 are buffers for storing data acquired from the DDC bus. Note that two first memory elements 114 and two second memory elements 115 are required as a minimum configuration, but two or more may be provided. Furthermore, these storage elements 114 and 115 do not necessarily have to be provided inside the transmission unit as long as the device information acquisition unit 112 can store data and the system can also be accessed. Furthermore, although it is not necessary to fix the size of each storage element 114,115, if it is 128 bytes which is the minimum unit of an EDID structure, handling of the acquired data becomes easy.

  The control unit 103 is connected to the video / audio transmitter 105 and the control register 113 via the I2C bus as the second interface 111, and controls each of them. The control unit 103 is connected to the first memory element 114 and the second memory element 115, and exchanges data with these memory elements 114 and 115. The receiving apparatus 106 includes a device information storage unit 107 that stores device information such as EDID, a device information transmitter 108 that controls transmission of device information, and a video / audio processor 109 that performs video / audio processing.

  A segment pointer is used for EDID access. In other words, if the value (0 to 127) of the segment to be read (data unit of 256 bytes separated by EDID) is written to the DDC address 60h, the data ADCh A0h and A1h are equivalent to the segment and data can be read. become. This readout structure is defined in ENHANCED DISPLAY DATA CHANNEL STANDARD based on VESA (Video Electronics Standards Association). The control unit 103 sets the following information in the control register 113. That is, the control unit 103 accesses the value of the segment to be read (example: 0x00 if the first segment), the size of the data to be read (example: 0x7F if 128 bytes), and address A0h or A1h Information for determining whether to store data acquired by DDC communication in the first memory element 114 or the second memory element 115 (for example, when storing address A0h in the first memory element 114) 0x00, 0x80 when storing address A0h in the second memory element 115, 0x08 when storing address A1h in the first memory element 114, and 0x88 when storing address A1h in the second memory element 115 Set in the register 113.

  After performing the above setting, the control unit 103 issues a command for executing the set content. Hereinafter, the process of setting information in the control register 113 and issuing a command to acquire the device information (EDID) of the receiving device 106 is referred to as EDID read command issue. Note that the same processing can be performed even in a configuration in which the address where the device information of the counterpart apparatus is stored is directly specified without using the segment pointer described above.

  When the above setting is applied to the control register 113, the device information acquisition unit 112 transmits a clock signal for reading the device information to the device information transmitter 108 in the reception device 106 via the DDC bus. This signal conforms to the I2C standard and includes the slave address and offset address of the device information (EDID) to be read. The device information transmitter 108 transmits device information (EDID) in the device information storage unit 107 to the device information acquisition unit 112 in accordance with the request for this signal. The device information acquisition unit 112 stores the transmitted EDID in the first storage element 114 or the second storage element 115 according to the setting of the control register 113. The control unit 103 reads out the EDID stored in the first memory element 114 or the second memory element 115 via the I 2 C bus 111. By repeating the above series of processing, the device information of the receiving device 106 is sent to the control unit 103 of the video / audio transmitting device 101.

  Next, a processing procedure for shortening the EDID reading time from the receiving apparatus 106 to the control unit 103 by alternately using the two storage elements 114 and 115 will be described with reference to the drawings. FIG. 3 illustrates the procedure of the EDID reading process with numbered arrows. FIG. 4 is a flowchart showing the order of data transfer processing in the control unit. The process numbers 1 to 12 described in FIG. 4 correspond to the process numbers in FIG.

  The control unit 103 issues an EDID read command for reading EDID data 1 (3071), which is one piece of device information, from the first storage element 11 to the control register 113 via the I2C bus 111 (processing number 1). At this time, the size of the device information read at a time is set to 128 bytes, which is the minimum unit of the data configuration of EDID.

  When the EDID read command is issued to the control register 113, the device information acquisition unit 112 immediately transmits a signal for reading the EDID data 1 (3071) to the receiving device 106 via the DDC bus (processing number 2). The receiving apparatus that has received this signal starts a process of transmitting EDID data 1 (3071) from the device information transmitter 108 to the video / audio transmitting apparatus 101. The device information acquisition unit 112 stores the sent EDID data 1 (3071) in the first storage element 114 (processing number 3).

  When the process of storing the EDID data 1 (3071) in the first storage element 114 is completed, the control unit 103 issues an EDID read command related to EDID data 2 (3072), which is device information to be read next, to the control register 113 ( Process number 4). When an EDID read command instructing acquisition of EDID data 2 (3072) is issued, a process of reading EDID data 1 (3071) stored in the first storage element 114 and sending it to the control unit 103 is immediately started. (Processing number 7). In addition, when an EDID read command relating to EDID data 2 (3072) is issued to the control register 113, the device information acquisition unit 112 receives a read signal of EDID data 2 (3072) in parallel with the processing of number 7. (Process number 5). Receiving device 106 receiving this signal starts processing for transmitting EDID data 2 (3072) to transmitting device 101 via device information transmitter 108. In response to this, the transmitting apparatus 101 stores the sent EDID data 2 (3072) in the second memory element 115 (processing number 6).

  When both the processing of the processing number 7 and the processing of the processing numbers 5 and 6 are finished, the processing of reading out the EDID data 2 (3072) from the second storage element 115 and sending it to the control unit 103 is immediately executed (processing number). 8). When the process of process number 8 is completed, all the EDIDs stored in the first memory element 114 and the second memory element 115 are read by the control unit 103.

  The control unit 103 performs processing for confirming the presence / absence of device information (EDID data) that needs to be read next (processing number 9: details will be described later). If there is no device information that needs to be read as a result of the confirmation, the device information acquisition process is completed at this point. On the other hand, if there is device information that needs to be read, the control unit 103 sends an EDID read command (indicating an instruction to read EDID data 3 (3073), which is device information) from the first storage element 11 to the control register 113. Issue (process number 10).

  When the process of issuing the EDID read command to the control register 113 is completed, a process (process number 11) is performed in which the device information acquisition unit 112 transmits a read signal of the EDID data 3 (3073) to the receiving device 106. Upon receiving the read signal, the receiving device 106 performs processing (processing number 12) for transmitting the EDID data 3 (3073) to the transmitter device 101.

  Here, the presence / absence of device information (EDID data) that needs to be read again is checked (process number 9). If there is no device information (EDID data), EDID data 3 (3073) that is device information stored in the first storage element 114 is controlled. The device information acquisition processing is completed by executing the processing (processing number 7) read to the unit 103.

On the other hand, if there is further device information that needs to be read, the control unit 103 issues an EDID read command indicating an instruction to read EDID data 4 (3074) that is device information from the second storage element 115 to the control register 113. (Processing number 4). Here, the control unit 103 controls the process of writing the EDID data 4 (3074) to the second memory element 115 (process numbers 5 and 6) and the EDID data 3 (3073) stored in the first memory element 114. The processing (processing number 7) read to the unit 103 is performed in parallel. Thereafter, until it is determined that it is not necessary to read out the device information by the determination of the processing number 9,
A process of issuing an EDID read command using the first storage element 114 when storing odd-numbered device information (EDID data);
A process of issuing an EDID read command using the second storage element 115 when storing even-numbered device information (EDID data);
Alternately.

  Therefore, a process of reading EDID from the receiving device 106 to the transmitting device 101 and a process of reading EDID from the two storage elements 114 and 115 to the control unit 103 while using the two storage elements 114 and 115 alternately are performed in parallel. Will be done. Thereby, the time required to transfer the EDID from the receiving apparatus 106 to the control unit 103 of the transmitting apparatus 101 can be shortened.

  Next, the specific process of process number 9 will be further described while explaining the structure of EDID. FIG. 5 shows a simplified structure of the device information (EDID) divided into three patterns, and the structure of the device information (EDID) belongs to one of these three patterns. Case 1 has a structure having an extension block only in the base block 501. Case 2 has a structure having one Base Block 502 and one Extension Block 503. Case 3 is a case having Base Block 504, Map Block 505, and Extension Block 506, and Case 3 has a structure in which Case 2 is extended.

  When processing up to the processing number 8 in the order described in FIG. 3 is performed on the device having the EDID structure having the structure of Case 2, the Base Block 502 corresponding to the EDID data 1 (3071) is stored in the first storage element 114. The storage element stores an extension block 503 corresponding to EDID data 2 (3072), and the control unit 103 is in a state where the data of the base block 502 and the data of the extension block 503 are read. Here, by examining the first byte of the extension block 503 as the process of process number 9, it is found that this block is the extension block. This is based on the equipment information (EDID) standard (VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA STANDARD), and the first byte of the block has a tag (“T” in FIG. 5) indicating what block the block is. It is because it is arranged. When it is determined that the second block is an extension block, it is determined that the EDID structure of this apparatus has a Case 2 structure. Therefore, the reading of the device information is completed without performing the process of issuing the EDID read command for reading the next EDID to the control register 113 (the process of process number 10).

  When processing up to the processing number 8 is performed on an apparatus in which EDID having the structure of Case 3 is set, the data of the Base Block 504 and the data of the Map Block 505 are read by the control unit 103. When the first 1 byte of the Map Block 505 is examined as the process of process number 9, it is found that this block is a Map Block. Based on the EDID standard (VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA STANDARD), data indicating the location where the extension block 506 is arranged is written in the map block (“E” in FIG. 5). Therefore, in the process of process number 9, after it is determined that the block is a map block, the storage location of the extension block can be specified by examining the data in the map block. If the storage location and the number of extension blocks are known, the two storage elements 114 and 115 are alternately used according to the above-described procedure until the necessary extension blocks are read out as many times as necessary. And data transfer between the two storage elements 114 and 115 and the control unit 103 can be performed in parallel (loop processing via A in FIG. 4).

  When processing up to the processing number 4 is performed in the device having the device information having the structure of Case 1, a signal instructing to acquire the EDID data 2 at the processing number 5 is sent to the receiving device 106. In this case, the receiving device 106 does not have an EDID corresponding to the EDID data 2 (3072). Therefore, the process number 6 which is a response from the receiving device 106 is returned as an error (see FIG. 6 below).

  When an EDID read command is issued to read out an extension block to a receiving apparatus that has an EDID that does not have an extension block (process number 4 in FIG. 6), DDC communication is performed to an offset address that does not exist. . According to the standard, DDC communication is performed using the same protocol as I2C communication, and when the communication ends normally, an acknowledgment of communication end is returned from the communication destination. Therefore, when an offset address area that does not exist is accessed, an acknowledge is not returned and DDC communication results in an error (process number 6 in FIG. 6). At that time, the transmitting apparatus 101 performs in parallel the process of reading the Base Block 501 stored in the first storage element 114 to the control unit 103 (process number 7 in FIG. 6). Whether the DDC communication error returned from the receiving device 106 at this point is an accidental DDC communication error as seen from the transmitting device 101 (control unit 103) or an error caused by accessing a nonexistent EDID. Cannot be judged.

  Therefore, when the process of reading the Base Block 501 is completed, the control unit 103 checks 1-byte data (“F” in FIG. 5) of the 127th byte of the Base Block 501. This 1-byte data is called an extension flag, and information indicating the presence or absence of an extension block and map block is written here. According to the EDID standard (VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA STANDARD), when the Extension Block and Map Block exist, the value of 0x01 is written in the Extension Flag, and when it does not exist, the value of 0x00 is written. It is. Therefore, if the extension flag is 0x01, it indicates that a response indicating a DDC error has been returned as a response, although the extension block and the map block exist, and the control unit 103 that has detected this has returned Is an accidental DDC communication error (process number 9 in FIG. 6). In this case, the system shifts to error processing and communication is performed again (processing number 13 in FIG. 6).

  On the other hand, if the Extension Flag is a value of 0x00, it indicates that there is no Extension Block and Map Block, and it is a DDC error due to access to a non-existing EDID area. It is determined that the receiving device has an EDID structure of Case 1 having only a Base Block, and error processing is not performed, and the processing up to processing number 7 in FIG.

  Next, a configuration for avoiding a DDC error due to the absence of an extension block and a map block will be described (see FIG. 7). First, the control unit 103 reads 1 byte of the extension flag (process number 15 in FIG. 7) and grasps the presence or absence of the extension block and the map block (process number 16 in FIG. 7). When determining that there is an extension block and a map block, the control unit 103 issues the EDID read command continuously (processing numbers 1 to 4 in FIG. 7), thereby reading the base block and the extension block all at once. On the other hand, when determining that there is no extension block, the control unit 103 changes the command issuance method so that only the base block is read (process number 1′2′3′7 in FIG. 7). As a result, the extension block and map block that do not exist are not accessed.

  By branching the command issuance process as described above, it is possible to avoid a DDC communication error caused by access to a nonexistent EDID. Furthermore, when an extension block and a map block exist, parallel processing by continuous issuance of EDID read commands can be performed as shown in process numbers 5, 6, and 7, so that acquisition of device information (EDID) is efficient. Can be done.

  As described above, if processing is performed in the order described above according to the three EDID structure patterns, data transfer between the receiving device 106 and the transmitting device 101, and the two storage elements 114 and 115 and the control unit 103 are performed. The data transfer between them can be performed in parallel, and the time required to transmit the device information (EDID) to the control unit 103 can be shortened. The time that can be shortened depends on the structure of the device information (EDID) of the partner connection device, but in parallel with the data transfer between the storage elements 114 and 115 and the control unit 103, the reception device 106 and the transmission device 101. Therefore, the time can be shortened by a time of [128 Byte data transfer time between the receiving device 106 and the transmitting device 101] × [number of blocks to be read].

  Further, if the extension flag is read first and the size of one storage element is 256 bytes, the number of EDID read commands issued can be reduced, and the processing speed can be increased. Further, when the Extension Flag is 0x01, there is necessarily an Extension Block. Therefore, if the size of the storage elements 114 and 115 is 256 bytes, the base block, the extension block, and the map block can be easily obtained by setting the data size to be read to 256 bytes and the EDID read command to be issued once. be able to. In addition, even when there are multiple extension blocks, data can be acquired up to 256 bytes at a time, so the number of command issues is one-half that of the case where the size of the storage elements 114 and 115 is 128 bytes. Data of the same size can be acquired. In this case, if the detected Extension Flag is 0x00, change the data size to be read to 128 bytes and execute the EDID read command so as not to perform useless access to the data area where the Extension Block and Map Block do not exist. Only Base Block may be acquired by issuing.

  In addition, when the memory element area that can be prepared is limited (for example, when only a single 128-byte buffer is available), if the data acquired at one time is halved, there are two 128-byte memory elements. By performing the same control as the above-described control in FIG. 5, the data transfer between the receiving device 106 and the storage elements 3131 and 4315 and the data transfer between the storage elements 114 and 115 and the control unit 103 are processed in parallel. can do. In this case, if the acquired data can be managed finely, the size that can be acquired at one time may be set to 1 byte, and data transfer for each byte may be executed in parallel.

  Further, the device information acquisition unit 112, the first storage element 114, the second storage element 115, and the control register 113 are not necessarily provided inside the transmission unit 102. As illustrated in FIG. The acquisition device 812, the control register 813, and the first and second storage elements 814 and 815 may constitute a control device (device information acquisition device 830).

  In addition, the first memory element 114 and the second memory element 115 are not necessarily physically separated from each other, so that an address for accessing one memory element is divided so as to virtually have two memory elements. It may be configured. In this case, since the division ratio and the number of divisions can be changed, the data area stored in the storage element can be changed in accordance with the data size of the device information (EDID) to be acquired. The storage element area can be used with an optimal size.

Further, as shown in FIG. 9, the configuration of the video / audio transmission device (see FIG. 1) receives a video / audio data from a CD / DVD playback unit 921 for reading data from a medium such as a CD or DVD. A tuner unit 922 and a video / audio encoding unit 920 that encodes video / audio data may be added. Then, based on the device information of the counterpart device obtained by the device information acquisition unit, the control unit 903 can transmit the data of the CD or DVD or the data of terrestrial digital broadcasting with a signal suitable for the performance of the connected counterpart device. it can. (See Figure 9)
As described above, according to the present embodiment, the device information reading speed of the partner connection device is improved, and the video / audio data output time from the power-on of the video / audio transmission device such as a DVD player or DVD recorder is increased. This speeds up the process and shortens the time required for video / audio output on the connection device side.

  A data transfer apparatus and a transfer control method according to the present invention transfer device information from a receiving apparatus to a control unit in the transmitting apparatus in a system such as a DVD player or a DVD recorder that transmits video / audio to the receiving apparatus using HDMI. This is useful for improving the processing speed.

It is a block diagram of the system which performs the data transfer of embodiment of this invention. It is a block diagram of the system which performs the conventional data transfer. It is the figure which showed the order of the data transfer control of this invention. FIG. 4 is a normal system flowchart showing data transfer control in the control unit of the present invention. It is the figure which simplified and showed three structure patterns of EDID. It is an error type | system | group flowchart in the apparatus which has only Base block. It is a flowchart which performs time reduction by unimplemented EDID access avoidance and parallel processing. It is the figure which showed the minimum component of this invention as a device. It is the figure which added the component for acquiring the video / audio data transmitted to this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Video / audio transmitter 102 Transmitter 103 Control unit 105 Video / audio transmitter 106 Receiver 110 First interface (HDMI)
111 Second interface (I2C)
112 device information acquisition unit 113 control register 114 first storage element 115 second storage element 201 DVD player / recorder 202 HDMI transmission LSI
DESCRIPTION OF SYMBOLS 203 System microcomputer 204 DDC buffer 206 TV / AV amplifier 210 HDMI cable 211 I2C bus 220 DDC bus 301 Transmitting device 303 Control unit 306 Receiving device 307 Device information storage unit 308 Device information transmitter 312 Device information acquisition unit 313 Control register 314 First Memory element 315 Second memory element

Claims (17)

A transmission unit;
A control unit for controlling the transmission unit;
A plurality of storage elements;
With
The transmitter is
A video / audio transmitter for transmitting a video / audio signal to an external receiving device;
A device information acquisition unit that receives device information including reception function information of the reception device from the reception device and transfers the device information to the control unit;
With
The plurality of storage elements temporarily store the device information,
The control unit performs a parallel process of a control process for writing the device information to at least one of the plurality of storage elements and a control process for reading the device information from at least one of the other storage elements. Controlling the transmitter based on the device information sequentially read from the storage element,
Video / audio transmitter. The interface for connecting the receiving device and the video / audio transmitter and the interface for connecting the device information acquisition unit and the control unit are different from each other.
The video / audio transmission apparatus according to claim 1. A control register for storing a control bit used when the control unit controls the device information acquirer;
The control unit selects the device information to be received by operating a control bit of the control register;
The video / audio transmission apparatus according to claim 1. The control unit selects the storage element in which the device information is written by operating the control bit.
The video / audio transmission apparatus according to claim 2. The control unit alternately performs a control process for writing the device information in at least one of the plurality of storage elements and a control process for reading the device information from at least one other among the plurality of storage elements. In addition, the transmitter is controlled based on the device information sequentially read from the plurality of storage elements by the alternating control process.
The video / audio transmission apparatus according to claim 1. If an error occurs during reception of the device information, the control unit determines the content of the error from the device information acquired until the error occurs, and continues normal processing or error processing based on the determination result. To judge,
The video / audio transmission apparatus according to claim 5. The control unit reads a data part that can confirm a desired data mounting range in the device information from the received device information, confirms the desired data mounting range based on the read data part, and confirms the data A desired data mounting range is selectively read from the storage element and transferred to the control unit;
The video / audio transmission apparatus according to claim 5. A control unit for controlling an external transmission device;
A device information acquisition unit that receives device information including reception function information of the reception device from an external reception device and transfers the device information to the control unit;
With
The device information acquisition device includes a plurality of storage elements for temporarily storing the device information,
The control unit performs a parallel process of a control process for writing the device information to at least one of the plurality of storage elements and a control process for reading the device information from at least one of the other storage elements. Controlling the transmitter based on the device information sequentially read from the storage element,
Device information acquisition device. A control register for storing a control bit used when the control unit controls the device information acquirer;
The control unit selects the device information to be received by operating a control bit of the control register;
The device information acquisition apparatus according to claim 8. The control unit alternately performs a control process for writing the device information in at least one of the plurality of storage elements and a control process for reading the device information from at least one other among the plurality of storage elements. Then, based on the device information obtained by this alternate control process, to control the transmission unit,
The device information acquisition apparatus according to claim 8. If an error occurs during reception of the device information, the control unit determines the content of the error from the device information acquired until the error occurs, and continues normal processing or error processing based on the determination result. To judge,
The device information acquisition apparatus according to claim 10. The control unit reads a data part that can confirm a desired data mounting range in the device information from the received device information, confirms the desired data mounting range based on the read data part, and confirms the data A desired data mounting range is selectively read from the storage element and transferred to the control unit;
The device information acquisition apparatus according to claim 10. The device information acquisition device according to claim 8,
A recording medium playback unit for reading video / audio data from the recording medium;
A tuner for receiving video and audio data;
A video / audio encoding unit that encodes the data read by the recording medium playback unit and the video / audio data received by the tuner unit;
With
Based on the device information read from the device information acquisition device, the video and audio data read from the recording medium is transmitted to an external receiving device.
Video / audio transmitter. The storage element is formed by virtually dividing one storage element into a plurality of storage elements.
The video / audio transmission apparatus according to claim 1. The plurality of storage elements virtually divided can change the division ratio.
The video / audio transmission apparatus according to claim 14. The storage element is formed by virtually dividing one storage element into a plurality of storage elements.
The device information acquisition apparatus according to claim 8. The plurality of storage elements virtually divided can change the division ratio.
The apparatus information acquisition apparatus of Claim 16.

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