JP2008160500A - Data transferring device and data transferring method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transferring device and data transferring method capable of suppressing a decrease in a data transferring speed without using redundant data and suppressing an expansion of a mounting area as much as possible. <P>SOLUTION: The data transferring device 1 for performing data transfer between two semiconductor elements 2 and 3 is provided with a data transmitting part 10 having: a random number generator 11 for sequentially generating and outputting binary natural random numbers Sig2; a scrambler 12 for sequentially receiving data for transmission and scrambling the data for transmission by the natural random numbers Sig2; first transmitters 14-1 to n for sequentially transmitting scrambled data signals Sig3-1 to n to first transmission lines 17-1 to n; and a second transmitter 16 for sequentially transmitting the natural random numbers Sig2 outputted from the random number generator 11 to a second transmission line 18. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data transfer technique, and more particularly to a data transfer technique between two or more different semiconductor elements.

  Conventionally, data transfer technology has been used for communication connection between semiconductor elements such as IC chips. Data transfer can be roughly divided into two. One is serial transfer and the other is parallel transfer.

  In general, the feature of serial transfer is that it is used in long-distance transmission, and the number of transmission lines is small and the data rate is high. On the other hand, the feature of parallel transfer is used in short-distance transmission, and transmission lines The number of data is large and the data rate is low.

  In recent years, the parallel transfer technology has become deadlocked, and in order to realize transfer at a higher data rate, the technology developed in serial transfer has been extended to the distance that parallel transfer technology has covered so far. Came to be used. For example, there is PCI Express formulated by PCI-SIG (Special Interest Group).

  By the way, a transmission line such as a data line or a clock line generally has a problem that a high frequency component is attenuated due to a skin effect of a conductor or a dielectric loss. For example, in a data rate region where the data transfer rate exceeds 5 Gbps, the attenuation of high frequency components cannot be ignored even if it is a short distance, and the data “0” and “1” are clearly defined by intersymbol interference. It becomes difficult to distinguish. Therefore, even in the case of data transfer at a short distance, a technique for recovering the attenuated high-frequency component by using an adaptive equalizer for a transmission path and ensuring data transfer is becoming common. (For example, VLSI sympo 2006, C-9.5 Power / Performance / Channel Length Tradeoffs in 1.6 to 9.6Gbps I / O Links in 90nm CMOS for Server, Desktop, and Mobile Applications)

  This adaptive equalizer has parameters inside, and it is desirable to always optimize the parameters according to changes in temperature and the like. In order for this automatic adjustment of parameters to work properly, it is necessary to input “0” and “1” randomly to some extent. If “0” continues for a long time, adjust the parameters. I can't.

Therefore, as a method of appropriately adjusting the parameters, (1) a method of encoding with redundant data (for example, 8B10B encoding, etc.), (2) sometimes the original data transfer is stopped, and the parameters of the transmission path are changed. A method for providing a readjustment period (for example, refer to Patent Document 1), (3) To perform N-bit transfer, N + 1 data lines are secured and one of the data lines is sequentially selected. There is known a method (for example, see Patent Document 2) in which parameter adjustment is performed and data transfer is performed using the remaining N data lines.
US Pat. No. 7,076,377 US Pat. No. 7,072,355

  However, in the method of encoding with redundant data, for example, to transfer 8-bit actual data, 10-bit data must be transferred, and about 20% of the transferred data cannot be used. As a result, the transfer efficiency decreases.

  In the method described in Patent Document 1, when data is transferred continuously for a long time, it is necessary to forcibly interrupt the data transfer and readjust the parameters, resulting in a decrease in the data transfer speed. Resulting in.

  In addition, in the method described in Patent Document 2, it is necessary to secure an extra data line, and it is necessary to add a circuit that distributes N bits to N + 1 and further restores the original, which increases the mounting area. End up.

  Accordingly, an object of the present invention is to provide a data transfer apparatus and a data transfer method capable of suppressing a decrease in data transfer speed without using redundant data and suppressing an increase in mounting area as much as possible. To do.

  To achieve the above object, according to a first aspect of the present invention, in a data transfer apparatus for transferring data between two or more semiconductor elements, the data transfer device includes a data transmission unit and a data reception unit, and the data transmission The unit sequentially generates and outputs binary natural random numbers and the transmission data, and sequentially scrambles the transmission data by logically calculating the transmission data using the natural random numbers. A scrambler that outputs the data, a first transmitter that sequentially transmits the logically calculated transmission data to one or more first transmission lines, and a natural random number output from the random number generator to the second transmission line sequentially. A second transmitter for transmitting, and the data receiving unit receives the logically-transmitted transmission data through the first transmission line, and the second transmission line through the second transmission line. Natural random number And a descramble for restoring the transmission data by performing a logical operation on the logically calculated transmission data received by the first receiver using a natural random number received by the second receiver. And a vessel.

  According to a second aspect of the present invention, in the first aspect of the present invention, the data transmission unit generates a reference clock that defines transmission timings of the first transmitter and the second transmitter. And an encoder that sequentially encodes the reference clock with the natural random number, and the second transmitter encodes transmission of the natural random number to the second transmission line by the encoder. The data reception unit includes a clock extractor that extracts the reference clock from a signal received through the second transmission line, and transmits the reference clock to the second transmission line. The receiver receives the data for transmission subjected to the logical operation based on the reference clock extracted by the clock extractor.

  According to a third aspect of the present invention, in the first aspect of the present invention, the data transmission unit generates a reference clock that defines transmission timings of the first transmitter and the second transmitter. And a third transmitter that sequentially transmits the reference clock to a third transmission line, and the data receiving unit includes a third receiver that receives the reference clock via the third transmission line, The first receiver receives the transmission data that is logically calculated based on a reference clock received by the third receiver.

  The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the random number generator is based on noise generated inside a semiconductor element having the data transmission unit. The natural random number sequence is generated.

  The invention according to claim 5 is the invention according to any one of claims 1 to 3, wherein the random number generator includes a plurality of ring oscillators having different prime numbers and different number of stages. And an exclusive OR circuit for calculating an exclusive OR of the output signals of the plurality of ring oscillators, and the output of the exclusive OR circuit is the natural random number.

  The invention described in claim 6 is characterized in that, in the invention described in any one of claims 1 to 5, the first transmission line has a capacitive element connected in series in the middle thereof. To do.

  Further, in the invention according to claim 7, in the invention according to any one of claims 1 to 6, the first receiver controls the timing of receiving and fetching the logically calculated transmission data. A timing adjuster that adjusts automatically, and the timing adjuster adjusts the timing for fetching the logically calculated transmission data based on the rising or falling timing of the logically calculated transmission data. It is characterized by.

  The invention according to claim 8 is the invention according to any one of claims 1 to 7, wherein the first receiver determines signal degradation in the first transmission line based on a predetermined parameter. An adaptive equalizer to be recovered is provided, wherein the adaptive equalizer dynamically adjusts the predetermined parameter based on a state transition of the logically calculated transmission data.

  The invention according to claim 9 is the invention according to any one of claims 1 to 8, wherein the random number generator is configured such that the logically calculated transmission data is m bits from the first transmitter. Each time it is transmitted, one natural random number is generated, and the scrambler has a random number storage unit for storing a sequence of the latest m bits of natural random numbers sequentially output from the random number generator, The transmission data is scrambled by performing a logical operation based on a sequence of m-bit natural random numbers stored in the random-number storage unit in units of m bits.

  According to a tenth aspect of the present invention, in the data transfer method for transferring data between two or more semiconductor elements, a step of sequentially generating and outputting binary natural random numbers and a step of sequentially inputting transmission data A step of sequentially performing a logical operation on the transmission data using the natural random number to scramble and output the transmission data, and sequentially transmitting the logically operated transmission data to one or more first transmission lines. A step of sequentially transmitting the natural random number to the second transmission line, a step of receiving the logically-transmitted data through the first transmission line, and the natural transmission line through the second transmission line. Receiving a random number; and restoring the transmission data by performing a logical operation on the received transmission data subjected to the logical operation with the received natural random number. And having a flop.

  According to the present invention, since the transmission data is scrambled using random numbers, the output balance of “0” and “1” can be achieved in the data transmitted to the data line as the transmission line. In addition, the random number used for scrambling is not a pseudo-random number having regularity, front-to-back correlation, periodicity, or the like, but a natural random number close to a true random number that does not cause a difference in random value probability and appearance rate. As a result, regardless of the value of the transmission data, the scrambled data may have a characteristic of a natural random number sequence (a characteristic that “0” and “1” occur at the same frequency). it can. Therefore, for example, when an adaptive equalizer is provided in the receiver, automatic adjustment of internal parameters can be normally operated in this adaptive equalizer without using a redundant code. Further, even when the power supply voltages of the data transmission unit and the data reception unit are different, it is possible to use a transmission line in which the middle part is capacitively coupled without using a redundant code. In addition, since the natural random number used for scrambling is transmitted from the data receiving unit to the data receiving unit, the data receiving unit can restore the transmission data using the natural random number received from the data transmitting unit.

  The data transfer device according to the present embodiment is a data transfer device for transferring data between two or more semiconductor elements, and includes a data transmission unit and a data reception unit.

  The data transmission unit scrambles the transmission data by sequentially inputting the transmission data and the random number generator that sequentially generates and outputs binary natural random numbers, and sequentially performing a logical operation on the transmission data using the natural random numbers. Scrambler that outputs the data, a first transmitter that sequentially transmits the logically calculated transmission data to one or more first transmission lines, and a natural random number that is output from the random number generator is sequentially transmitted to the second transmission line. And a second transmitter.

  Further, the data receiving unit includes a first receiver that receives transmission data logically operated through the first transmission line, a second receiver that receives natural random numbers through the second transmission line, and a first receiver A descrambler that restores the transmission data by performing a logical operation on the logically calculated transmission data received by the receiver using a natural random number received by the second receiver.

In this way, since the transmission data is scrambled using random numbers, the output balance of “0” and “1” can be achieved in the data transmitted to the data line as the transmission line. Moreover, the random number used for scrambling is not a pseudo-random number having regularity, front-rear correlation, periodicity, or the like, but a natural random number close to a true random number that does not cause a difference in random value probability and appearance rate. As a result, unlike the pseudo-random number, it can be always unpredictable whether the random number is “0” or “1”. For example, the probability that 100 bits of the same data are continuous is 2 ⁻¹⁰⁰ (2 to the −100 power), and is approximately 7.9 × 10 ⁻³¹ (the value obtained by multiplying the −10 power to the −31 power by 7.9). . Therefore, even if data is continuously sent for 10 years at a data transfer rate of 10 Gbps, considering that it is 3.2 × 10 ¹⁸ (the value obtained by multiplying 10 to the 18th power by 3.2) bits, it is actually 100 bits. It is thought that the same data will not continue. Therefore, regardless of the value of the transmission data, the scrambled data can have the characteristics of the natural random number sequence (characteristics where “0” and “1” occur at the same frequency). . Therefore, when an adaptive equalizer is provided in the receiver, automatic adjustment of internal parameters can be normally operated in this adaptive equalizer without using a redundant code.

  In addition, since the natural random number used for scrambling is transmitted from the data transmission unit to the data reception unit, the data reception unit can restore the transmission data using the natural random number received from the data transmission unit.

  The data transmitter includes a clock source that generates a reference clock that defines transmission timings of the first transmitter and the second transmitter, and an encoder that sequentially encodes the reference clock with natural random numbers. The second transmitter transmits a natural random number to the second transmission line by transmitting a reference clock encoded by the encoder to the second transmission line. The data receiver includes a clock extractor that extracts a reference clock from a signal received via the second transmission line, and the first receiver performs a logical operation based on the reference clock extracted by the clock extractor. Receive data for transmission. Note that the encoding by the encoder encodes a natural random number by a method such as Manchester encoding.

  Since the reference clock and the natural random number are transmitted through one transmission line in this way, the wiring between the semiconductor elements can be simplified.

  A special transmission path for transmitting a sequence of natural random numbers may be prepared. For example, the data transmitter is provided with a third transmitter that sequentially transmits a reference clock to the third transmission line, while the data receiver is provided with a third receiver that receives the reference clock via the third transmission line. The first receiver receives the transmission data logically calculated based on the reference clock received by the third receiver. With this configuration, there is no need to provide an encoder or a clock extractor, and the mounting area of the data transfer device can be reduced.

  Some random number generators use noise inside a semiconductor element and others use a ring oscillator. For example, a random number generator that generates a sequence of natural random numbers based on noise generated inside a semiconductor element having a data transmission unit can be used. Noise generated inside the semiconductor element includes weak radiation, noise generated by natural phenomena such as resistance and diode thermal noise, flicker noise, and shot noise. A ring oscillator uses a plurality of ring oscillators with different numbers of stages and different numbers of stages, and an exclusive OR circuit that calculates the exclusive OR of the output signals of the plurality of ring oscillators. There is a random number generator that uses natural random numbers as the output of a logical OR.

  In this way, natural random numbers can be easily generated by using the internal noise of the semiconductor element and the ring oscillator.

  Moreover, since the occurrence frequency of “0” and “1” can be made equal as described above, the first transmission line can be connected in series with capacitive elements in the middle.

As described above, AC coupling of the middle portion of the first transmission line with the capacitive element enables operation even when the signal potentials of the data transmission unit and the data reception unit are different. For example, the probability that the average value of a sequence of natural random numbers having a length of 10,000 deviates from 1/2 to 0.05 or more is 1.6 × 10 ⁻²³ (10 −23 to the power of 1.6 is multiplied by 1.6) This is because such a deviation is at a level that does not cause a problem in operation if the capacitance is normally used for AC coupling (for example, 100 nF).

  The first receiver has a timing adjuster that dynamically adjusts the timing for receiving and fetching the logically calculated transmission data, and the timing adjuster transmits the logically calculated transmission data. Based on the rising or falling timing, the timing for fetching the logically calculated transmission data is adjusted.

  The first receiver has an adaptive equalizer that recovers signal degradation in the first transmission line based on a predetermined parameter, and the adaptive equalizer has a logical operation of transmission data. A predetermined parameter is dynamically adjusted based on the state transition.

  By providing an adaptive equalizer in the data receiving unit in this way, it is possible to flexibly cope with the attenuation characteristic of the transmission line without interrupting data transfer. Also, unlike other analog filters, noise amplification can be suppressed.

  The random number generator generates a natural random number each time m-bit transmission data subjected to logical operation is transmitted from the first transmitter, and the scrambler outputs the latest data sequentially output from the random number generator. A random number storage unit that stores a sequence of m-bit natural random numbers, and scrambles the transmission data based on the m-bit sequence of natural random numbers stored in the random number storage unit in units of m bits. .

  As a result, it is not necessary to match the natural random number generation speed of the random number generator with the data transfer speed, and the circuit design is facilitated. In addition, since the transfer frequency of natural random numbers can be reduced, it is possible to suppress external influences such as unnecessary radiation.

  A step of sequentially generating and outputting binary natural random numbers; a step of sequentially inputting transmission data; and a step of scrambling transmission data by sequentially performing logical operations on the transmission data with natural random numbers; A step of sequentially transmitting logically operated transmission data to one or more first transmission lines, a step of sequentially transmitting natural random numbers to the second transmission line, and a logical operation of the transmission data via the first transmission line. Receiving data, receiving a natural random number via the second transmission line, restoring the transmission data by performing a logical operation on the received logically operated transmission data with the received natural random number, and If it is a data transfer method which has this, it will not be restricted to the structure of the said data transfer apparatus.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram of the data transfer apparatus 1 of the first embodiment, and FIG. 2 is an operation explanatory diagram of the data transfer apparatus 1 of the first embodiment.

  As shown in FIG. 1, the data transfer device 1 is a data transfer device for transferring data between two or more semiconductor elements, and is also called a Chip-to-Chip interface. The data transfer apparatus 1 includes a data transmission unit 10 built in the first semiconductor element 2 and a data reception unit 20 built in the second semiconductor element 3.

  The data transmitting unit 10 sequentially generates and outputs a natural random number Sig2 that is close to a binary random number (“0”, “1”) true random number that does not cause a difference in random value probability and appearance rate; Data to be transmitted from the first semiconductor element 2 to the second semiconductor element 3 (hereinafter referred to as “transmission data”) is sequentially input, and the transmission data is input by the natural random number Sig2 output from the random number generator 11. A scrambler 12 that scrambles and outputs transmission data by sequentially performing logical operations, a clock source 13 that generates a reference clock Sig1, and n transmission data logically operated by the scrambler 12 (n is a natural number) The first transmitters 14-1 to 14-n that sequentially transmit to the first transmission lines 17-1 to 17-n, which are the data lines, and the reference clock Sig1 sequentially with natural random numbers Sig2 The encoder 15 for outputting a Goka signal Sig4, and a second transmitter 16 sequentially transmits the signal Sig4 is outputted from the encoder 15 to the second transmission line 18. The reference clock Sig1 is a clock that defines the transmission timing of the first transmitter 14 and the second transmitter 16. The second transmission line 18 is a transmission line in which the clock line and the random number transmission line are shared. In other words, the reference clock Sig1 and the natural random number Sig2 are simultaneously transmitted through one second transmission line 18 by sequentially encoding the reference clock Sig1 with the natural random number Sig2.

  Here, it is assumed that the transmission data input to the data transmission unit 10 is p-bit parallel data. The scrambler 12 has a parallel-serial converter that converts p-bit transmission data into n serial data. For example, p = 24 and n = 4. In the scrambler 12, n serial data generated by parallel-serial conversion of the transmission data (hereinafter referred to as “transmission serial data”) are sequentially transmitted by logical operation using natural random numbers Sig2. Scramble credit data.

  The data receiving unit 20 is connected to the first transmission lines 17-1 to 17-n, and transferred data Sig10-1 to 1 transmitted from the data transmitting unit 10 via the first transmission lines 17-1 to 17-n. First receivers 21-1 to 21-n that are data receivers that receive and binarize Sig10-n and output binarized signals Sig21-1 to Sig21-n, respectively, and a reference clock A signal Sig11 obtained by encoding Sig1 with a natural random number Sig2 is received via the second transmission line 18 and binarized, and the binarized signal is output from the binarized signal Sig22. A function as a clock extractor that extracts the reference clock Sig1 from the Sig22 and outputs it as the reference clock Sig23, and a natural random number Sig2 by extracting the natural random number Sig2 from the binarized signal Sig22 A CDR (Clock Data Recovery) device 23 having a function of outputting as 4 and a descrambler 24 for restoring transmission data by performing a logical operation on the binarized signals Sig21-1 to Sig21-n with natural random numbers Sig24. I have. The first receivers 21-1 to 21-n receive the transfer data Sig10-1 to Sig10-n based on the reference clock Sig23. Further, the transmission data restored by the descrambler 24 is output to other circuits in the second semiconductor element 3 as return data.

  Here, the descrambler 24 converts the data (hereinafter referred to as “recovered serial data”) after descrambling the n serial data with the natural random number Sig 24 into return data that is p-bit parallel data. A serial-parallel converter is included. For example, p = 24 and n = 4.

  FIG. 2 shows the state of data and natural random numbers that are transferred by the data transfer apparatus 1. Hereinafter, the data transfer operation by the data transfer apparatus 1 will be described with reference to FIGS. For ease of understanding, an operation related to the first transmission line 17-1 among the n first transmission lines 17-1 to 17-17 in the data transfer apparatus 1 will be mainly described here. The operation related to the first transmission line is the same.

FIG. 2A shows the state transition of each signal in the data transmission unit 10, and one transmission data among a plurality of transmission serial data output from the parallel-serial converter of the scrambler 12 in the upper stage. Serial data [d _k-1 ], [d _k ], [d _{k + 1} ] (k is an arbitrary natural number) are sequentially output, and the middle stage is output from the random number generator 11. The natural random number Sig2 is output in the order of [r _k-1 ], [r _k ], [r _{k + 1} ], and the lower stage shows signals Sig3-1 to Sig3- output from the scrambler 12. among signals Sig3-1 n is _{[d k-1 ^ r k} -1], which indicates that it is outputted in the order of _{[d k ^ r k],} [d k + 1 ^ r k + 1] . [D _k-1 ^ r _k-1 ] is scrambled data obtained by performing a logical operation on the transmission serial data [d _k-1 ] using a natural random number [r _k-1 ]. Similarly, [d _k ^ r _k ] Is scrambled data obtained by logically operating [d _k ] by [r _k ] and [d _{k + 1} ^ r _{k + 1} ] by [d _{k + 1} ] by [r _{k + 1} ].

  The signals Sig3-1 to Sig3-n are output as signals Sig10-1 to Sig10-n to the first transmission lines 17-1 to 17-n by the first transmitters 14-1 to 14-n. The reference clock Sig1 is sequentially encoded by the natural random number Sig2 output from the random number generator 11, and is output as the signal Sig4. The signal Sig4 is sequentially transmitted to the second transmission line 18 as the signal Sig11 by the second transmitter 16.

FIG. 2B shows the state transition of the first transmission line 17-1 and the second transmission line 18, and the upper part of FIG. 2B shows that the signal Sig 10-1 is [d _{k− 1} ^ r _k-1 ], [d _k ^ r _k ], and [d _{k + 1} ^ r _{k + 1} ] in this order, and the lower stage shows the signal Sig 11 on the second transmission line 18. It is shown that the natural random number Sig2 included by the encoding is output in the order of [r _k-1 ], [r _k ], [r _{k + 1} ].

The data receiving unit 20 receives the signal Sig11 on the second transmission line 18 via the second receiver 22, and uses the CDR unit 23 to reproduce the reference clock Sig1 and the natural random number Sig2 as Sig23 and Sig24, respectively. The first receivers 21-1 to 21-n receive the signals Sig10-1 to Sig10-n of the first transmission lines 17-1 to 17-n using the reference clock Sig23, and Sig21-1 to Sig21. Output as -n. The Sig 21-1 to Sig 21 -n output from the first receivers 21-1 to 21 -n are exclusively ORed with the natural random number Sig 24 in the descrambler 24. At this time, the natural random number [r _k ] used for scrambling the data [d _k ] in the data transmitting unit 10 has arrived in the data receiving unit 20 using the clock line. If exclusive OR is performed on the scrambled data [d _k ^ r _k ] again with [r _k ], the original data is restored because [d _k ^ r _k ] ^ [r _k ] = [d _k ]. can do.

FIG. 2C shows the state transition of each signal in the data receiving unit 20, and the received signal Sig 21-1 from the first receiver 21-1 is [d _k-2 ^ r _k-2 ], [d _k-1 ^ r _k-1 ], [d _k ^ r _k ], [d _{k + 1} ^ r _{k + 1} ] are sequentially output, and the middle stage outputs from the CDR unit 23. Are output in the order of [r _k−2 ], [r _k−1 ], [r _k ], [r _{k + 1} ], and the lower stage is output by the descrambler 24. [D _k-2 ２１r _k-2 ], [d _k-1 ｒr _k-1 ], [d _k ｒr _k ], [d _{k + 1} ｒr _{k + 1} ], which are the received signals Sig21-1. Is a natural random number Sig24 [r _k-2 ], [r _k-1 ], [r _k ], [r _{k + 1} ], and the return serial data descrambled by logical operation is [d _k-2 ]. , [D _k-1 ], [d _k ], [d _{k + 1} ] The restored serial data is output from the descrambler 24 as restored data by serial-parallel conversion of the descrambler 24 together with other restored serial data.

As described above, according to the data transfer apparatus 1 of the present embodiment, the scrambler 12 uses the transmission serial data sequence {..., D _k−1 , d _k , d _{k + 1} ,. _{{..., r k-1,} r k, r k + 1, ...} when there is, the exclusive OR of the transmission serial data [d _k] a natural random number _{[r k] [d k ^} r k] Are calculated for each data. The value of [r _k ] is determined by the probability, and the occurrence probabilities of “0” and “1” are both ½, so that [d _k ] is either “0” or “1”. , [D _k ^ r _k ], the occurrence probabilities of “0” and “1” are both halved. Therefore, it is possible to balance the output of “0” and “1” for the data transmitted to the data line as the transmission line, and it is not necessary to use a redundant code. In addition, since the natural random number used for scrambling is transmitted from the data transmission unit 10 to the data reception unit 20, the data reception unit 20 restores the transmission data using the natural random number received from the data transmission unit 10. be able to.

  Further, according to the data transfer apparatus 1 of the present embodiment, “0” and “1” are balanced in the data signals transmitted through the first transmission lines 17-1 to 17-n, and therefore, as shown in FIG. Thus, the capacitive elements C1-1 to C1-n can be connected in series in the middle of the first transmission lines 17-1 to 17-n. At this time, in the data transmitter 10, the outputs of the first transmitters 14-1 to 14-n are pulled up to the power supply voltage Vcc1 of the first semiconductor element 2 by the resistors R1-1 to R1-n. In the data receiving unit 20, the inputs of the first receivers 21-1 to 21-n are pulled up to the power supply voltage Vcc2 of the second semiconductor element 3 by resistors R2-1 to R2-n.

  In this way, AC coupling of the middle portion of the first transmission line with the capacitive element enables operation even when the power supply voltage Vcc1 of the first semiconductor element 2 and the power supply voltage Vcc2 of the second semiconductor element 3 are different. it can.

  Here, a specific configuration of the random number generator 11 will be described. FIG. 4 shows a configuration of the random number generator 11 using noise inside the first semiconductor element 2.

  As shown in FIG. 4, the random number generator 11 is an amplifier 31 that amplifies the thermal noise in the first semiconductor element 2 and a register that operates in synchronization with the reference clock Sig1, and holds an output from the amplifier 31. A register 32 that outputs as a natural random number Sig2 and a filter circuit 33 that inverts the natural random number Sig2 output from the register 32 and inputs it to an amplifier 31 are provided. In this random number generator 11, a minute voltage signal is generated at the input of the amplifier 31 due to thermal noise. This minute voltage signal is amplified using an amplifier 31. The register 32 holds and outputs the signal amplified by the amplifier 31 in synchronization with the reference clock Sig1, and outputs “0” and “1” at random. Note that the filter circuit 33 performs inverting feedback so that the occurrence frequencies of “0” and “1” are both halved.

  Further, a random number generator using a ring oscillator may be used instead of the random number generator 11 using noise inside the first semiconductor element 2. FIG. 5 shows a configuration of a random number generator 11 'using a ring oscillator.

As shown in FIG. 5, a ring oscillator 34 having N ₁ stages (N ₁ is prime and smaller than N ₂ ), and a ring oscillator 35 having N ₂ stages (N ₂ is prime and smaller than N ₃ ), A ring oscillator 36 having N ₃ stages (N ₃ is prime), and an exclusive OR 37 for calculating the exclusive OR of the output signals of these ring oscillators 34 to 36 in synchronization with the reference clock Sig 1 The output of the exclusive OR 37 is a natural random number Sig2 ′.

  Next, the configuration of the scrambler 12 will be specifically described. FIG. 6 is a diagram showing the configuration of the scrambler 12.

  As shown in FIG. 6, the scrambler 12 includes a parallel-serial converter 40 that converts transmission data Da_0 to Da_p-1 which is p-bit parallel data into n transmission serial data Db_0 to Db_n-1. And a logical operation unit 41 that scrambles and outputs n pieces of serial data for transmission Db_0 to Db_n-1 by sequentially performing logical operations on natural random numbers Sig2.

  The logical operation unit 41 includes exclusive ORs 43-1 to 43-n that exclusive-OR each transmission serial data Db_0 to Db_n-1 with a natural random number Sig2 for each bit, and the exclusive OR The DFFs (data flip-flops) 44-1 to 44-n output the signals output from the signals 43-1 to 43-n in synchronization with the reference clock Sig1.

  In the scrambler 12, the transmission data Da_0 to Da_p-1 are parallel-serial converted into n transmission serial data Db_0 to Db_n-1, and each of the transmission serial data Db_0 to Db_n-1 is converted into bits. As shown in FIG. 7, the transmission data Da_0 to Da_p-1 is divided into blocks of q bit units (for example, q = p / n), and each block is exclusive ORed with the natural random number Sig2. A scrambler 12 ′ that outputs Sigs 3-1 to 3-n after performing an exclusive OR with a natural random number Sig2 as a unit and then performing parallel-serial conversion. FIG. 7 is a diagram showing the configuration of one block of the scrambler 12 '. The DFF 42-1 to 42-q that sequentially outputs the natural random number Sig2 to the subsequent DFF in synchronization with the reference clock Sig1, and the blocks for transmission Exclusive ORs 43'-1 to 43'-n that take exclusive OR of data (for example, Da_0 to Db_q-1) at the outputs of the DFFs 42-1 to 42-n, and the exclusive ORs Each block includes DFFs (Data Flip-Flops) 44'-1 to 44'-n that respectively output signals output from 43'-1 to 43'-n in synchronization with the reference clock Sig1. After taking an exclusive OR with a natural random number Sig2 as a unit, the parallel-serial converter 40 ′ performs parallel-serial conversion to output Sig3-1 to 3-n.

  Next, the encoder 15 will be described with reference to the drawings. FIG. 8 is a diagram showing the configuration of the encoder 15. FIG. 9A is a diagram showing the state transition of each signal in the encoder 15, and FIG. 9B is a diagram showing the state transition of each signal in the CDR unit 23.

  As shown in FIG. 8, the encoder 15 includes DFFs 51 and 52 and an exclusive OR 53, and inputs the natural random number Sig2 to the exclusive OR 53 in synchronization with the reference clock Sig1. . Also, the encoding clock is output to the exclusive OR 53 in synchronization with the reference clock Sig1. The exclusive OR 53 calculates the exclusive OR of the signals output from the DFFs 51 and 52 and outputs the result as the signal Sig4 (see FIG. 9A). Here, the encoding clock is a clock whose phase is slightly shifted from the reference clock Sig1, and thus, the signal Sig4 can be easily output as a signal encoded by Manchester. When the reference clock Sig1 and the natural random number Sig2 are 625 Mbps, the bit of the natural random number Sig2 is expressed by 2 bits, so that the signal Sig4 is transmitted at a rate of 625 Mbps × 2 = 1.25 Gbps. In FIG. 9A, Manchester encoding is expressed by 2 bits, such as (0, 1) when the input signal is “0” and (1, 0) when the input signal is “1”. ing. By performing such encoding, the frequency of edge generation can be guaranteed. The edge means a timing at which the data signal transitions from “0” → “1” or “1” → “0”.

  The signal Sig4 transmitted from the data transmission unit 10 is input as the signal Sig22 to the CDR unit 23 via the second transmission line 18 and the second receiver 22. The CDR unit 23 generates a decoding clock and a reference clock Sig 23 from the Sig 22. As shown in FIG. 9B, the CDR unit 23 is configured such that the rising timing of the decoding clock becomes the edge timing of the input signal Sig22, and the falling timing of the decoding clock comes at the antinode of the signal Sig22. Configured as follows. Since this is the Manchester encoding method, the data receiving unit 20 determines whether the data before encoding is “0” or “1” by detecting the first data, and outputs the decoded signal Sig24. Output. Since the data receiving unit 20 needs to handle 2 bits as one set in this way, the boundary between these sets is set during the training period at the start-up in the data transfer apparatus 1. become.

  Next, the configuration of the first receivers 21-1 to 21-n and the second receiver 22 will be specifically described with reference to the drawings. FIG. 10 is a diagram illustrating the configuration of the timing adjuster in each of the first receivers 21-1 to 21-n, and FIG. 11 illustrates the configuration of the adaptive equalizer 70 in each of the first receivers 21-1 to 21-n. FIG. Since each of the first receivers 21-1 to 21-n and the second receiver 22 has the same configuration, only the first receiver 21-1 will be described here.

  The first receiver 21-1 receives the signal Sig10-1 and dynamically adjusts the timing at which the signal Sig10-1 is received, and the signal output from the timing adjuster 60 on the first transmission line 17-1. And an adaptive equalizer 70 that recovers signal degradation based on predetermined parameters.

  As shown in FIG. 10, the timing adjuster 60 includes an edge detection amplifier 61 that amplifies the signal Sig 10-1, a data detection amplifier 62 that similarly amplifies the signal Sig 10-1, and a phase interpolator described later. A phase comparator that compares the timing of the rising edge (or falling edge) of the signal from 65 with the timing of the rising edge (or falling edge) of the output of the edge detection amplifier 61 and outputs a voltage corresponding to the result. 63, a filter 64 that filters and outputs the phase comparison result by the phase comparator 63, and a six-phase clock (0 deg, 60 deg, 120 deg, 180 deg, 240 deg, 300 deg) from the six-phase clock generator 67 And select two clocks from the six-phase clocks of the reference clock (for example, 60 deg and 12 deg. deg) Output from a phase interpolator 65 that generates a clock of an arbitrary phase (for example, an arbitrary phase between 60 deg and 120 deg) by interpolating the phases of two clocks, and an amplifier 62 for data detection The register 66 receives the signal Sig 10-1 by the clock output from the phase interpolator 65, receives the signal Sig 10-1, and outputs it to the adaptive equalizer 70.

  The phase interpolator 65 receives the signal output from the filter 64, and generates an edge detection clock Clock1 and a reception clock Clock2 having a phase corresponding to the signal. In addition, the phase interpolator 65 outputs the edge detection clock Clock 1 to the phase comparator 63 and outputs the reception clock Clock 2 to the register 66. The phase comparator 63 compares the timing of the rising edge (or falling edge) of the edge detection clock Clock 1 with the timing of the rising edge (or falling edge) of the edge detection amplifier 61. The register 66 holds and outputs a signal output from the data detection amplifier 62 in synchronization with the reception clock Clock2. The phase interpolator 65 outputs the reception clock Clock 2 and the edge detection clock Clock 1 with a difference of 90 degrees. For example, when the reception clock Clock2 has a phase of 70 deg and 250 deg, the edge detection clock Clock1 is set to 160 deg and 340 deg.

  In this way, the timing adjuster 60 adjusts the timing for taking in the signal Sig10-1 based on the edge (rising or falling) timing of the signal Sig10-1. If the frequency of the reference clock is 5 GHz, the second receiver 22 of the data receiving unit 20 receives the signal Sig11 at 10 Gbps. At this level of frequency, it is costly to make an amplifier operating at 10 GHz with CMOS, and as described above, the amplifier can be operated at the frequency of the reference clock as the minimum necessary frequency. .

  The adaptive equalizer 70 has a function of recovering signal degradation on the first transmission line 17-1 based on a predetermined parameter, and is sent to the first receiver 21 via the first transmission line 17-1. This is an equalizer that dynamically adjusts a predetermined parameter based on a state transition of a signal input and taken in by the timing adjuster 60. The adaptive equalizer 70 is configured as shown in FIG. 11, and data received several cycles in the past is stored in a register chain 73. By returning a signal corresponding to past data stored in the register chain 73 to the adder 71, the influence from the past cycle is canceled, and data in the current cycle is extracted. Here, the slicer 72 has a function of determining whether the signal output from the adder 71 is “0” or “1”. The error amplifier 74 and the parameter controller 75 are coefficients (h (1), h (2),..., H (i) in FIG. 11) for canceling the influence from the past cycle by the adder 71. ) Is always controlled to be optimal.

  In order for the adaptive equalizer 70 to be controlled correctly, it is important that the correlation between the current cycle data and the past cycle data is sufficiently small. If the correlation is strong, the above coefficient cannot be maintained at a correct value. In the data transfer apparatus 1 of this embodiment, since data is transmitted using natural random numbers, the correlation of received data in each cycle is sufficiently small, and there is no need to use a redundant code.

(Second Embodiment)
Next, a data transfer device 1 ′ in the second embodiment will be described with reference to the drawings. FIG. 12 is a schematic configuration diagram of a data transfer apparatus 1 ′ according to the second embodiment. In addition, the thing of the same structure as 1st Embodiment attaches | subjects the same code | symbol as 1st Embodiment, and abbreviate | omits description.

  The data transfer apparatus 1 'according to the second embodiment is different from the data transfer apparatus 1' according to the first embodiment in the transfer method of the natural random number Sig2. That is, the data transfer device 1 ′ of the first embodiment transmits the natural random number Sig2 from the second transmission line 18 on the reference clock Sig1, but in the second embodiment, the data transfer device 1 ′ and the reference clock Sig1 The natural random number Sig2 is transferred using a separate transmission line, the encoder 15 and the CDR unit 23 are removed, and a third transmitter 16 ′ and a third receiver 25 described later are provided.

  As shown in FIG. 12, the data transfer device 1 ′ transfers the natural random number Sig2 generated by the random number generator 11 in the data transmission unit 10 ′ as the signal Sig11 via the second transmission line 18 by the second transmitter 16. To do. The reference clock Sig1 generated by the reference clock source 13 is transferred as the signal Sig12 through the third transmission line 19 by the third transmitter 16 '. On the other hand, in the data receiver 20 ′, the signal Sig 11 input via the second transmission line 18 is received by the second receiver 22 and output to the descrambler 24 as a natural random number Sig 23 for descrambling. The signal Sig12 input via the third transmission line 19 is received by the third receiver 25 and output as the reference clock Sig23 of the first receivers 21-1 to 21-n. The third transmitter 16 'has the same configuration as the first transmitters 14-1 to 14-n and the second transmitter 16, and the third receiver 25 is the first receiver 21-1 to 21-n. The second receiver 22 has the same configuration. Note that the third receiver 25 may not use the same configuration as the second receiver 22 and the like, but may use a PLL.

  Since the data transfer device 1 ′ in the second embodiment is configured as described above, it is not necessary to provide an encoder or a clock extractor as in the first embodiment, and the mounting area of the data transfer device is reduced. Can do.

(Other embodiments)
In the first and second embodiments described above, the generation timing of the natural random number Sig2 is made the same as the clock cycle of the reference clock Sig1, but the generation timing of the natural random number Sig2 is made later than the clock cycle of the reference clock Sig1. be able to.

  That is, the ratio of the data transfer rate and the rate at which natural random numbers are transmitted to the second semiconductor element 3 is m (m is an integer equal to or greater than 2): 1. More specifically, every time the random number generators 11 and 11 ′ transmit m bits of signals Sig3-1 to Sig3-n output from the scrambler 12, from the first transmitters 14-1 to 14-n. Then, one natural random number Sig2 is generated. In addition, the scrambler 12 is provided with a transmission-side random number storage unit that stores a sequence of the latest m-bit natural random numbers Sig2 sequentially output from the random number generators 11 and 11 ′, and transmits transmission data in units of m bits. It is scrambled by performing a logical operation based on a sequence of natural random numbers of m bits stored in the side random number storage unit. The transfer of the natural random number Sig2 from the data transmission units 10 and 10 ′ is sequentially transmitted every time the random number generators 11 and 11 ′ generate the natural random numbers. On the other hand, on the data receiving unit 20, 20 ′ side, a descrambling unit 24 is provided with a receiving side random number storage unit that accumulates a sequence of natural random numbers for the latest m bits sequentially transferred from the data transmitting unit 10, 10 ′. The received signals Sig 21-1 to 21-n are scrambled by performing a logical operation based on a sequence of m-bit natural random numbers stored in the receiving-side random number storage unit in m bits.

FIG. 13 shows the state transition of each signal in such a configuration. FIG. 13A shows the state transition of each signal in the data transmitters 10 and 10 ′, and the ratio of the data transfer rate and the rate at which natural random numbers are transmitted to the second semiconductor element 3 is m: 1. While sending m pieces of data, only one natural random number is sent. In this case, as shown in FIG. 13, m data to be transferred is considered as one set of blocks. In block A shown in FIG. 13A, a sequence of m natural random numbers {r _k−1 , r _k ,... R _{k + n− 2} } is used as natural random numbers. As a sequence of n natural random numbers of {r _k , r _k ,..., R _{k + n−1} }. That is, in block B, the natural random number [r _{k + m−1} ] newly generated by discarding the natural random number [r _k−1 ] having the oldest generation time is used. The newly generated natural random number [r _{k + m−1} ] is transferred to the data receiving units 20 and 20 ′ via the transmission line as shown in FIGS. Used for scrambling. The position at which a new natural random number [r _{k + m-1} ] is added is the last of each block in FIG. 13, but may be the top of each block. That is, a new natural random number [r _{k + m−1} ] may be added to any position as long as the positions of the data transmitting units 10 and 10 ′ and the data receiving units 20 and 20 ′ are matched.

  Even if natural random numbers are reused in this way, for example, when m = 8, natural random numbers between 1 to 7 cycles apart are independent and sufficient for use in the adaptive equalizer 70. I will be away. However, when AC coupling is performed on the transmission line as shown in FIG. 3, m needs to be sufficiently large. This is because the number of independent random numbers is compressed to 1 / m.

  With the above configuration, it is not necessary to match the generation speed of the natural random number Sig2 by the random number generators 11 and 11 'with the data transfer rate (speed), and the circuit design is facilitated. In addition, since the transfer frequency of the natural random number Sig2 can be reduced, it is possible to suppress external influences such as unnecessary radiation.

  As mentioned above, some of the embodiments of the present invention have been described in detail with reference to the drawings. However, these are merely examples, and the present invention is variously modified and improved based on the knowledge of those skilled in the art. It is possible to carry out the invention.

  For example, in the data transmission unit 10, an example in which one natural random number is used in a plurality of first transmission lines has been described. However, the present invention is not limited thereto, and one random number generator may be provided in one first transmission line. It may be. In this case, it is necessary to provide a transmission path for transmitting natural random numbers to the data receiving unit 20 corresponding to the number of first transmission lines.

It is a schematic block diagram of the data transfer apparatus of 1st Embodiment. It is operation | movement explanatory drawing of the data transfer apparatus of 1st Embodiment. It is a figure for demonstrating the example using the AC coupling transmission line which couple | bonded the middle part with the capacitive element. It is a figure which shows the structure of the random number generator using the thermal noise inside a 1st semiconductor element. It is a figure which shows the structure of the random number generator using a ring oscillator. It is a figure which shows the structure of the scrambler in 1st Embodiment. It is a figure which shows the other structure of the scrambler in 1st Embodiment. It is a figure which shows the structure of the encoder in 1st Embodiment. It is a figure which shows the state transition of each signal in the encoder in 1st Embodiment. It is a figure which shows the structure of the timing adjuster of the 1st receiver in 1st Embodiment. It is a figure which shows the structure of the equalizer in the 1st receiver in 1st Embodiment. It is a schematic block diagram of the data transfer apparatus of 2nd Embodiment. It is a figure which shows the state transition of the signal of each part in other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data transfer apparatus 2 1st semiconductor element 3 2nd semiconductor element 10, 10 'Data transmission part 11 Random number generator 12 Scrambler 13 Reference clock source 14 1st transmitter 15 Encoder 16 2nd transmitter 16' 3rd Transmitter 17 First transmission line 18 Second transmission line 19 Third transmission line 20, 20 'Data receiver 21 First receiver 22 Second receiver 23 CDR unit 24 Descrambler 25 Third receiver

Claims (10)

In a data transfer apparatus for transferring data between two or more semiconductor elements,
A data transmission unit and a data reception unit;
The data transmitter is
A random number generator that sequentially generates and outputs binary natural random numbers;
A scrambler that sequentially inputs transmission data and scrambles and outputs the transmission data by sequentially performing a logical operation on the transmission data using the natural random number;
A first transmitter for sequentially transmitting the logically calculated transmission data to one or more first transmission lines;
A second transmitter for sequentially transmitting natural random numbers output from the random number generator to a second transmission line,
The data receiver is
A first receiver that receives the logically calculated transmission data via the first transmission line;
A second receiver for receiving the natural random number via the second transmission line;
A descrambler that restores the transmission data by performing a logical operation on the logically calculated transmission data received by the first receiver using a natural random number received by the second receiver. A data transfer device. The data transmitter is
A clock source that generates a reference clock that defines transmission timing of the first transmitter and the second transmitter;
An encoder that sequentially encodes the reference clock with the natural random number;
The second transmitter is
Transmitting the natural random number to the second transmission line by transmitting a reference clock encoded by the encoder to the second transmission line;
The data receiver is
A clock extractor for extracting the reference clock from a signal received via the second transmission line;
The data transfer device according to claim 1, wherein the first receiver receives the transmission data that is logically calculated based on a reference clock extracted by the clock extractor. The data transmitter is
A clock source that generates a reference clock that defines transmission timing of the first transmitter and the second transmitter;
A third transmitter for sequentially transmitting the reference clock to a third transmission line,
The data receiver is
A third receiver for receiving the reference clock via the third transmission line;
The data transfer apparatus according to claim 1, wherein the first receiver receives the transmission data that is logically calculated based on a reference clock received by the third receiver. The random number generator is
The data transfer device according to claim 1, wherein the sequence of natural random numbers is generated based on noise generated inside a semiconductor element having the data transmission unit. The random number generator is
A plurality of ring oscillators with different numbers of stages and different numbers of stages,
An exclusive OR circuit for calculating an exclusive OR of the output signals of the plurality of ring oscillators,
The data transfer apparatus according to claim 1, wherein an output of the exclusive OR is the natural random number. The data transfer device according to any one of claims 1 to 5, wherein the first transmission line has a capacitive element connected in series at an intermediate portion thereof. The first receiver has a timing adjuster that dynamically adjusts the timing for receiving and taking in the transmission data subjected to the logical operation,
The timing adjuster adjusts the timing for fetching the logically calculated transmission data based on the rising or falling timing of the logically calculated transmission data. The data transfer apparatus according to any one of claims. The first receiver has an adaptive equalizer that recovers signal degradation in the first transmission line based on a predetermined parameter;
The said adaptive equalizer adjusts the said predetermined parameter dynamically based on the state transition of the data for transmission by which the logic operation was carried out. The Claim 1 characterized by the above-mentioned. Data transfer device. The random number generator generates a natural random number each time m bits of transmission data subjected to the logical operation are transmitted from the first transmitter,
The scrambler has a random number storage unit that stores a sequence of the latest m bits of natural random numbers sequentially output from the random number generator, and stores the transmission data in the random number storage unit in units of m bits. The data transfer apparatus according to any one of claims 1 to 8, wherein the data is scrambled by a logical operation based on a sequence of natural random numbers for m bits. In a data transfer method for transferring data between two or more semiconductor elements,
Sequentially generating and outputting binary natural random numbers;
Sequentially inputting transmission data, scrambled and output the transmission data by sequentially performing a logical operation on the transmission data with the natural random number;
Sequentially transmitting the logically calculated transmission data to one or more first transmission lines;
Sequentially transmitting the natural random numbers to the second transmission line;
Receiving the transmission data subjected to the logical operation via the first transmission line;
Receiving the natural random number via the second transmission line;
A step of performing a logical operation on the received transmission data subjected to the logical operation using the received natural random number to restore the transmission data.