JP2008154292A - Imaging apparatus and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance AD conversion rate and accuracy of an image sensor incorporating an AD converter in an imaging apparatus having an array parallel AD converter. <P>SOLUTION: In an imaging apparatus with sensing elements 101 arranged in matrix and an AD converter arranged for each array, the AD converter 103 holds an electric signal corresponding to a signal of the sensing element 101 becoming an analog signal in a storage section 112 as an initial value. Subsequently, the AD converter begins charge or discharge of the storage section at a rate corresponding to the magnitude of a fixed signal being inputted, and measures the time having elapsed until the electric signal at the storage section becomes equal to a reference signal after charge start time or discharge start time as a digital value. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a CCD, a CMOS image sensor, a near-infrared or far-infrared image sensor in which an element that converts energy into an electrical signal, represented by photoelectric conversion, is a unit pixel and the pixels are arranged in a matrix. The present invention relates to an imaging apparatus and an imaging system in which AD converters are arranged for each column.

  In today's image sensor, it is possible to manufacture a complicated analog circuit, digital circuit, signal processing unit, and the like on a sensor chip by integrating a CMOS logic process and an image sensor process. One of the most promising applications is that an analog / digital converter (AD converter) is mounted on an image sensor chip in which pixels are arranged two-dimensionally.

  When an AD converter is mounted on an image sensor, a column parallel AD conversion architecture in which an AD converter is provided for each column is particularly used. This method can reduce the conversion rate of each AD converter from the readout rate of one pixel to the readout rate of one row, thereby reducing the speed of the AD converter itself and reducing the power consumption comprehensively. As a result, it is easy to increase the reading rate of the image sensor.

  The above-described image sensor using column parallel AD conversion is conventionally an image sensor using a ramp type that sweeps a triangular wave represented by Patent Document 1 and a successive approximation type represented by Patent Document 2. In addition, there are image sensors using a technique for discharging a reference voltage at a speed determined by an output voltage of a pixel, represented by Patent Document 3, as represented by Patent Document 3.

  The successive approximation type is inevitably increased in circuit scale in order to ensure accuracy, and as a result, the chip size of the image sensor is increased, limiting the application. On the other hand, an image sensor using a lamp type AD converter and an image sensor using a reference voltage discharge type AD converter are excellent in that the circuit scale can be made compact.

  FIG. 11 shows an example of an image sensor having a lamp type AD converter disclosed in Patent Document 1. The ramp type AD converter has a digital memory including a voltage comparator 10, a switch 11, and a digital data storage unit 12 in each column, and the digital memory is connected to a common counter 5. A signal from the pixel is input as an analog signal to the one end of the voltage comparator 10 via the transfer switch 3, and a triangular wave is applied from the DA converter 9 to the other end, and the counter when the comparator of each column is inverted. Is stored in the digital memory of each column. Since the triangular wave changes its voltage in synchronization with the counter 5, for example, in the case of an 8-bit AD converter, the sweeping of the triangular wave requires a processing time of 2 8 steps, that is, 256 steps.

FIG. 12 shows an example of an image sensor having a reference voltage discharge AD converter disclosed in Patent Document 3. The reference voltage discharge type AD converter has the same voltage comparator and digital memory as the ramp type AD converter. However, the reference voltage discharge type AD converter once accumulates a constant reference voltage as a charge in the comparator, and stores it in the current mirror circuit 1215. The voltage is discharged at a current proportional to the pixel signal that has been converted to voltage and current, and the time until the comparator is inverted is counted.
JP 05-048460 A US Pat. No. 5,880,691 JP 2002-033962 A

  In the image sensor incorporating the lamp type AD converter or the reference voltage discharge type AD converter, there are problems in increasing the speed and accuracy of the AD converter.

  Specifically, in an image sensor using a lamp-type AD, it is difficult to reduce the unit time per step. Since the triangular wave is supplied to the entire surface of the sensor as an analog voltage, it is theoretically necessary to shorten the period of one step to a certain time determined by the RC time constant, which is necessary for the output of the triangular wave to be stabilized throughout the chip. It is difficult to. Therefore, it is difficult to increase the speed by reducing the time per step. In addition, if the accuracy is further increased, the number of steps itself increases, and the increase in speed is further hindered.

  Further, in the reference voltage discharge AD converter, if the signal level of the pixel is remarkably low when discharging a constant voltage, the current value becomes remarkably low. For this reason, it is necessary to wait for a very long time. Inversion does not occur, and it is difficult to increase the speed. In addition, the circuit for converting the voltage into the current is insufficient, and the charging slope exhibits a very nonlinear behavior.

  Therefore, the present invention provides a technique for reducing the time per step using a technique that does not require applying an analog voltage that changes with time to the entire sensor in an imaging apparatus having a column-parallel AD converter, and further a pixel signal. An object of the present invention is to provide a highly accurate method that is not affected by the increase in discharge time depending on the level, and to further improve the AD conversion speed and accuracy of an image sensor incorporating an AD converter.

In the imaging apparatus of the present invention, sensing elements are arranged in a matrix, and an AD converter is provided for each column of the sensing elements.
The AD converter holds an electrical signal corresponding to the signal of the sensing element, which is an analog signal, in the storage unit as an initial value, and then the AD converter responds to the magnitude of the input fixed signal. Charging or discharging of the storage unit is started at a speed, and the time from the charging start time or the discharge start time until the electrical signal of the storage unit becomes equal to the reference signal is measured to obtain a digital value.

  According to such an imaging apparatus, it is not necessary to apply a reference voltage that changes with time in the entire chip, and the time required for one comparison step of the comparator of the AD converter as compared with an image sensor that uses lamp-type AD conversion. Can be shortened, and the speed of AD conversion can be improved. In addition, since the optical signal is set as an initial value and then discharged at a constant slope, the comparison can always be completed in less than a certain number of steps compared to the reference voltage discharge type.

  In the imaging apparatus of the present invention, the AD converter includes an integrator, and the initial value is determined by integrating the signal of the sensing element by the integrator for a predetermined time, and the determined initial value is the It is preferable to be charged or discharged using an integrator.

  According to such an imaging apparatus, since the setting of the initial value and the discharging thereof are performed using an integrator having the same time constant, the variation in charging characteristics between adjacent AD converters affects the variation in AD conversion errors. It is possible to configure an imaging device that does not.

  In the imaging apparatus of the present invention, the imaging apparatus includes a digital counter, the AD converter includes an integrator, a comparator, and a digital memory, and an output of the integrator is connected to an input of the comparator, and the comparison The output of the storage device is connected to the capture trigger terminal of the digital memory, the digital counter is connected to the input terminal of the digital memory, and the output of the digital counter stored in the digital memory is the digital value. Is preferred.

  According to such an imaging apparatus, it is possible to easily provide an accurate AD converter for each column using a general electric circuit.

  In the imaging apparatus of the present invention, the integrator includes an operational amplifier, a resistor connected to one input terminal of the operational amplifier, and a capacitor connected between the one input terminal and the output terminal. It is preferable to make it.

  According to such an imaging device, the integrator can be configured with high accuracy, and a highly accurate AD converter with good linearity can be provided on the imaging device regardless of the signal level of the sensing pixel. .

  In the imaging device of the present invention, it is preferable that the integrator includes an operational amplifier and a switched capacitor circuit connected to one input terminal of the operational amplifier.

  According to such an imaging apparatus, the resistance necessary for the integrator can be configured by a capacitance, and the equivalent resistance value can be made variable by control, and the AD conversion characteristics can be changed as necessary. become.

  In the imaging apparatus of the present invention, the storage unit can be an output unit of an integrator.

In the imaging apparatus of the present invention, the sensing elements arranged in the column direction are selectively connected to the vertical output lines (for example, the sensing elements arranged in the row direction are selected for each row and connected to the vertical output lines. It is preferable that the vertical output line and the AD converter are connected via a voltage amplifier.
According to such an image pickup apparatus, it is possible to reduce effective input conversion noise by amplifying a signal, fixed pattern noise at the time of sample / hold of AD conversion, random noise at the time of AD conversion, quantization The influence of errors and the like can be reduced.

  In the imaging apparatus of the present invention, the sensing elements arranged in a column direction are selectively connected to a vertical output line, and the vertical output line and the AD converter are connected via a noise removal circuit, and the noise removal circuit Preferably has a function of removing the noise signal of the sensing element from the signal after sensing.

  According to such an imaging apparatus, the dynamic range of AD conversion can be expanded as compared with the technique of subtracting the noise level from the signal level after AD conversion.

  According to the present invention, in an imaging apparatus having a column-parallel AD converter, the time per step can be shortened by using a technique that does not need to apply an analog voltage that changes with time to the entire sensor. Therefore, it is possible to provide a highly accurate AD conversion technique that is not affected by the increase in the discharge time due to.

  A first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram showing an example of a circuit diagram of the first embodiment of the present invention. Here, a case where the sensing element is a pixel that performs photoelectric conversion is taken as an example of the sensing element, and the pixel 101 is arranged in a matrix to form the pixel unit 102, and a two-dimensional image signal is converted into an electric charge or a voltage. Convert to electrical signal. These pixels are, for example, a CCD, a CMOS sensor, a near-infrared sensor, or a sensor that converts far-infrared rays into heat and converts them into electric signals. Of course, it is not limited to these examples, For example, a pressure sensor etc. may be sufficient as a sensing element.

  In FIG. 1, reference numeral 103 denotes an AD converter, and a signal from a pixel group is input to the AD converter 103 via a CDS (correlated double sampling) circuit 120 that removes reset noise.

  The signal from the pixel after CDS is connected to the output 112 of the integrator 107 via the sample and hold (S / H) circuit 104, the buffer 105, and the switch 106. One input terminal of the integrator 107 is connected to a fixed voltage (V_DE) 110 for integration via a resistor 108 and a switch 109, and a reference voltage 111 is connected to the other input terminal of the integrator. Yes.

  The output terminal 112 of the integrator 107 is connected to the input terminal of the comparator 113, and the comparator 113 compares the output 112 of the integrator 107 with the reference voltage 114. Here, the voltage applied to the reference voltage 111 and the reference voltage 114 is the same V_REF. The output 115 of the comparator 113 determines the capture trigger of the n-bit memory unit 116, and holds the value output from the counter 117. The memory unit of each AD converter 103 is selectively connected to the horizontal digital signal line 118 and output to the outside through the buffer 119.

Each memory unit is connected to the horizontal digital signal line 118 via a switch (not shown), and performs selective output by turning on the switch one at a time. The switch pulse includes a method of decoding an address or a method of sequentially turning on each column using a digital shift register. In this way, selective output from the digital memory to the horizontal digital signal line 118 is performed.
These buffers, switches, resistors, etc. are all described schematically at the functional level, and there is no limitation on the specific embodiments thereof. They are design items that are selected after deciding what manufacturing process and circuit technology to use. For example, when making a buffer, there are a case where a CMOS inverter is used, or a case where a voltage is once amplified by positive feedback using a so-called sense amplifier and then output again through the CMOS inverter. The CMOS inverter is a circuit for actively amplifying an electric signal and transmitting the signal by changing (usually decreasing) the output impedance. Since a signal is inverted in a CMOS inverter, an impedance converter called a buffer is configured by connecting two inverters in series.
When making a switch, simply by turning on and off the voltage of the gate of one MOS transistor, when making a switch with logic such as AND and OR, bipolar transistor, JFET, SIT, etc. instead of MOS transistor There are various cases, such as when using.
There are various cases in which the resistance is made, for example, by making the metal stretched, in the case of making it by polysilicon, and in the case of making the resistance by ion implantation into the silicon substrate.
The operation of this circuit will be described with reference to FIG. 2, FIG. 3, FIG. 4, and FIG. FIG. 2 is a voltage transition of the output unit 112 of the integrator, and FIGS. 3 to 5 are charts showing the operation in the time direction of each row at the function level.

  The basic principle is that, while the signal of the counter 117 is synchronously counted up, the counter value at that time is received in the memory 116 in response to the trigger from the comparator 113, and is necessary for the signal from the pixel and the discharge by integration. AD conversion is performed using the proportional relationship between the two times.

  First, a signal after CDS (correlated double sampling) is applied to the output 112 of the integrator via the sample and hold circuit 104, the buffer 105, and the switch 106. The switch 106 is turned off, and the signal 201 from the pixel is stored in the output terminal 112 of the integrator (stored in the capacity of the output unit of the integrator). At time 202, the switch 109 is turned on, and counting by the common counter 117 is also started. Integration is performed with a negative slope toward the reference voltage 203. At time 204, the integrator output 112 crosses the reference voltage 203. At this time, the comparator 113 triggers the memory unit 116, and the value of the counter 117 at that time is taken into the memory unit 116.

  Since the time from the start of integration, that is, the time from time 202 to time 204 is proportional to the signal 201 from the pixel, the counter value taken into the memory is the AD conversion result.

  The configuration of this embodiment is particularly preferably used in an image sensor. In the image sensor using the lamp-type AD as described with reference to FIG. 11, it is difficult to reduce the unit time per step because of the AD conversion accuracy required for the image sensor and the large chip size. It was difficult to increase the speed in further increasing the number of bits. Since the triangular wave is supplied to the entire surface of the sensor as an analog voltage, it is theoretically necessary to shorten the period of one step to a certain time determined by the RC time constant, which is necessary for the output of the triangular wave to be stabilized throughout the chip. Because it is difficult. Therefore, when the number of steps increases in further multi-biting, it is difficult to shorten the time per step and increase the speed.

  By using the configuration of the present embodiment, the integrator inside each AD converter performs AD conversion using the fixed voltage V_DE given to the entire surface, so it is necessary to provide a waiting time for stabilizing the lamp voltage. Therefore, the time per step can be reduced as compared with the method using the lamp voltage, and the time required for AD conversion itself can be reduced.

  Here, the buffer 105 is a 1 × buffer. However, for example, a buffer that performs voltage amplification of 1 × or more may be used. When performing voltage amplification, it is also possible to incorporate a voltage amplification function into the CDS. By performing voltage amplification in this way, the input conversion value of noise superimposed on the amplified signal can be reduced. Further, it is assumed that the voltage amplification includes an amplification factor of less than 1 time or 1 time.

  In an actual circuit, the initial value is determined by resistance division determined by the output impedance of the integrator and the output impedance of the buffer 105. For this, for example, the output impedance of the buffer is reduced or the capacitance is reduced. A technique may be used such as forming a circuit that clips the maximum value using a buffer in which an additional source follower is provided in the final stage.

  Further, one AD converter may be provided in two rows and one in a plurality of rows. The number of rows of AD converters to be provided is a design item determined by the allowable chip area and AD conversion speed.

  The above description was for a one-dimensional line operation. Next, a case where the two-dimensional operation is performed will be described with reference to FIGS.

  FIG. 3 shows the simplest example. A series of operations in which the reset level is subtracted by the CDS in 301, AD conversion is performed in 302, and finally, the digital data resulting from the AD conversion is output to the outside in 303. Repeat every time. By adopting this method, high-speed operation is sacrificed, but AD conversion with less noise is possible.

  301 is a period from when the signal output from the sensing element is input to the CDS 120 to when the output of the CDS 120 is applied to the output 112 of the integrator and the switch 106 is turned off. 302 is the time when the switch 109 is turned on at time 202. Until the AD conversion result is taken into the memory unit 116 (time 204), and 303 is a period in which the AD conversion result is sequentially output from the arranged memory units 116 via the buffer 119.

  FIG. 4 shows a technique for improving the speed, in which the reset level is subtracted by CDS while outputting the AD conversion result of the Nth row. By multiplexing the operations, it is possible to improve the AD conversion throughput and the image data readout throughput. It is also possible to suppress the noise to a range that can be ignored by design.

  FIG. 5 shows a technique for further improving the speed. While the AD conversion of the (N + 1) th row is performed at 501, the AD conversion result of the Nth row is output at 502 and the CDS of the (N + 2) th row is set to 503. It was made to do in. As a result, the AD conversion throughput is further improved as compared with the circuit operation of FIG. 4, and the image data can be read out at high speed.

  FIG. 9 shows a configuration example when the pixel of the sensing element is a photoelectric conversion pixel. The pixel shown in FIG. 9 represents one pixel of the CMOS sensor.

  In FIG. 9, PD is a photodiode, Q1 is a transfer MOS transistor that transfers charges accumulated in the photodiode to a floating diffusion (FD) region (floating diffusion region), Q2 is a reset MOS transistor that resets the FD region, and Q3 is The amplifying transistor Q4 is a selection MOS transistor.

The signal φRST is set to the high level to turn on the reset MOS transistor Q2 to reset the FD region, and the noise signal N is output via the selection transistor Q4. Then, the charge accumulated in the photodiode PD is read out to the FD region through the transfer MOS transistor Q1 with the signal φTX set to the high level. The signal charge Q _sig by capacitance C _FD of the floating diffusion region FD and a voltage converted to Q _sig / C _FD, is a signal by the amplification MOS transistor the floating diffusion region FD and the gate is connected to the amplifier, the MOS transistor for selection Read signal S from. The signal S is subtracted from the noise signal N by the CDS circuit. Such pixels are arranged in a matrix to form the pixel portion 102 of FIG. In each pixel row arranged in the row direction, the gate of the transfer transistor Q1 is connected to the common transfer line, the gate of the reset transistor Q2 is connected to the common reset line, and the gate of the selection transistor Q4 Are connected to a common selection line, and φRST, φTX, and φT are sequentially applied to a reset line, a transfer line, and a selection line provided for each row by a vertical scanning circuit (not shown). A signal transfer operation, a reset operation, and a pixel selection operation (signal output operation) are controlled. A configuration may be adopted in which a plurality of photodiodes are connected to the gate of one amplifying transistor Q3 via a plurality of transfer transistors, and the amplifying transistor and the resetting transistor are shared.

  FIG. 6 is a diagram for explaining a second embodiment of the present invention. In the first embodiment, the value of the pixel signal is directly written in the output of the integrator. However, in this embodiment, both the pixel signal and the reference voltage are integrated.

  The reset level of the output from the pixel 701 is removed by the CDS circuit 702, which is held by the sample and hold (S / H) circuit 703 and input to the integrator via the buffer 704 and the switch 705. An input of the integrator can be switched by a switch 705 between a signal from a pixel or a fixed voltage for integration (V_DE) 706. Reference numeral 707 denotes an output unit of the integrator.

  Next, the circuit operation will be described with reference to FIG. FIG. 7 shows the change of the signal of the output unit 707 of the integrator with respect to time. First, in the period 801, the integrator is reset to initialize the output to V_REF, and then at time 802, the switch 705 is switched from floating to a signal from the pixel to integrate the input voltage. By integrating the input signal for a certain time, the final arrival point 803 is determined only by the parameter of the magnitude of the input signal.

  Thereafter, the switch 705 is switched to the reference voltage side, and integration is started with a negative slope in the V_REF direction. At that time, the common counter also starts counting. At 804, the integrator output crosses V_REF, but at that time, a trigger signal is sent to the memory, and the value of the counter is latched.

  The effects of this embodiment are as follows. In the first embodiment, there is an effect that the time per unit step can be shortened, and the effect can be enjoyed as it is also in the present embodiment.

  In the first embodiment, the input signal is not integrated, and the discharge is performed with a fixed voltage and a fixed RC time constant, and the discharge time is measured. This sometimes leads to variations in AD conversion columns.

  In particular, in an image sensor, this variation between columns affects the image in a visible manner, and therefore it is desirable to suppress the variation as much as possible. In this embodiment, since both the input and output are integrated by the same integrator and the same RC time constant is used, even if there is an error in the RC time constant of the ADC for each column, the error can be invalidated. .

  FIG. 8 is a view for explaining a third embodiment of the present invention. The configuration is the same as in FIG. 1 except for the switched capacitor 601. The integrator operation is realized by operating the switched capacitor 601 as a resistor equivalent to the resistor 108 of the first embodiment while switching the switch 602.

  The operation as a line and the operation as a two-dimensional sensor when using this circuit are the same as in the first embodiment. The advantage of the first embodiment is that when the RC time constant of the integrator is determined, a fixed value is used when a resistor is used. However, when a switched capacitor is used, various advantages can be obtained by switching the frequency of the switch. It is to be able to realize a proper resistance value. As a result, the degree of freedom of design is widened, and it becomes possible to cope with various image signals caused by various scenes.

  Hereinafter, an embodiment when the solid-state imaging device of the present invention is applied to a still camera will be described in detail with reference to FIG.

  FIG. 10 is a block diagram showing a case where the imaging apparatus of the present invention is applied to a “still video camera”.

  In FIG. 10, reference numeral 2101 denotes a barrier that doubles as a lens protect and main switch, 2102 denotes a lens that forms an optical image of a subject on a solid-state imaging device (imaging device) 2104, and 2103 denotes a variable amount of light passing through the lens 2102 Aperture 2104 is a solid-state image sensor for capturing an object imaged by the lens 2102 as an image signal, 2107 is a signal processing unit for performing various corrections on the output image data and compressing the data, and 2108 is a solid-state image sensor 2104, an imaging signal processing circuit 2105, a timing generation unit that outputs various timing signals to the signal processing unit 2107, 2109 an overall control / operation unit that controls various operations and the entire still video camera, and 2110 temporarily stores image data. Memory unit for storing, 2111 records or reads out on a recording medium Interface unit Utame, 2112 removable recording medium such as a semiconductor memory for recording or reading of the image data, the 2113 is an interface unit for communicating with an external computer or the like.

Next, the operation of the still video camera at the time of shooting in the above configuration will be described.
When the barrier 2101 is opened, the main power supply is turned on, the control system power supply is turned on, and the imaging system circuit power supply is turned on.

  Then, in order to control the exposure amount, the overall control / arithmetic unit 2109 opens the diaphragm 2103, and the signal output from the solid-state imaging device 2104 is input to the signal processing unit 2107.

  Based on the data, the exposure calculation is performed by the overall control / calculation unit 2109.

  The brightness is determined based on the result of the photometry, and the overall control / calculation unit 2109 controls the aperture according to the result.

  Next, based on the signal output from the solid-state imaging device 2104, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 2109. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts.

  When the exposure is completed, the image signal output from the solid-state imaging device 2104 passes through the signal processing unit 2107 and is written into the memory unit by the overall control / calculation unit 2109.

  Thereafter, the data stored in the memory unit 2110 is recorded on a removable recording medium 2112 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 2109.

  Further, the image may be processed by inputting directly to a computer or the like through the external I / F unit 2113.

  The present invention is applied to an imaging apparatus in which high-speed and high-precision AD converters are arranged for each column in an imaging apparatus such as a CCD, a CMOS image sensor, a near-infrared or far-infrared image sensor.

It is drawing which shows an example of the circuit structure of 1st embodiment of the imaging device of this invention. It is a figure which shows an example of operation | movement of 1st embodiment of the imaging device of this invention. It is a figure which shows an example of operation | movement of 1st embodiment of the imaging device of this invention. It is a figure which shows an example of operation | movement of 1st embodiment of the imaging device of this invention. It is a figure which shows an example of operation | movement of 1st embodiment of the imaging device of this invention. It is a figure which shows an example of the circuit structure of 2nd embodiment of the imaging device of this invention. It is a figure which shows an example of operation | movement of 2nd embodiment of the imaging device of this invention. It is a figure which shows an example of the circuit structure of 3rd embodiment of the imaging device of this invention. It is a figure which shows one pixel of a CMOS sensor. It is a block diagram which shows the case where the imaging device of this invention is applied to a "still video camera". It is a figure which shows one prior art example. It is a figure which shows one prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Pixel 102 Pixel part 103 AD converter 104 Sample hold circuit 105 Buffer 106 Switch 107 Integrator 108 Resistor 109 Switch 110 Fixed voltage for integration 111 Reference voltage 112 Output terminal of integrator 113 Comparator 114 Reference voltage 115 Comparator of comparator Output 116 Memory unit 117 Counter 118 Horizontal digital signal line 120 CDS (correlated double sampling) circuit 601 Switched capacitor 602 Switch 701 Pixel 702 CDS circuit 703 Sample hold (S / H) circuit 704 Buffer 705 Switch 706 Fixed voltage for integration (V_DE)
707 Output of integrator

Claims (9)

In an imaging device in which sensing elements are arranged in a matrix and an AD converter is provided for each column of the sensing elements,
The AD converter holds an electrical signal corresponding to the signal of the sensing element, which is an analog signal, in the storage unit as an initial value, and then the AD converter responds to the magnitude of the input fixed signal. Charging or discharging the storage unit at a speed, and measuring the time from the charge start time or discharge start time until the electrical signal of the storage unit becomes equal to a reference signal to obtain a digital value apparatus.   The AD converter includes an integrator, and the initial value is determined by integrating the signal of the sensing element with the integrator for a certain period of time, and the determined initial value is charged using the integrator or The imaging apparatus according to claim 1, wherein the imaging apparatus is discharged.   The imaging apparatus includes a digital counter, the AD converter includes an integrator, a comparator, and a digital memory. An output of the integrator is connected to an input of the comparator, and an output of the comparator is the digital memory. The digital counter is connected to an input terminal of the digital memory, and the output of the digital counter stored in the digital memory is the digital value. Or the imaging device of 2.   The integrator includes an operational amplifier, a resistor connected to one input terminal of the operational amplifier, and a capacitor connected between the one input terminal and the output terminal. The imaging device according to claim 3.   The imaging device according to claim 3, wherein the integrator includes an operational amplifier and a switched capacitor circuit connected to one input terminal of the operational amplifier.   The imaging apparatus according to claim 2, wherein the storage unit is an output unit of the integrator.   The sensing elements arranged in a column direction are selectively connected to a vertical output line, and the vertical output line and the AD converter are connected via a voltage amplifier. The imaging apparatus of Claim 1.   The sensing elements arranged in a column direction are selectively connected to a vertical output line, the vertical output line and the AD converter are connected via a noise removal circuit, and the noise removal circuit is a noise signal of the sensing element. The imaging device according to claim 1, wherein the imaging device has a function of removing a signal from a signal after sensing.   An image pickup apparatus according to claim 1, an optical system that forms an image of light on the image pickup apparatus, and a signal processing circuit that processes an output signal from the image pickup apparatus. An imaging system.