JP2008134067A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which decreases the number of test pins without increasing test times. <P>SOLUTION: The same test input value as that inputted from one input test pin is inputted to circuits K<SB>1</SB>-K<SB>N</SB>. The first test output value from the circuit K<SB>1</SB>is inputted to a comparison means, not illustrated, provided outside of a chip to compare with a predetermined expected value. And, the first test output value from the circuit K<SB>1</SB>is inputted to a coincidence and anticoincidence circuit D. The second test output values from the circuits K<SB>2</SB>-K<SB>N</SB>are inputted to the coincidence and anticoincidence circuit D. The coincidence and anticoincidence circuit D compares the second test output values from the circuit K<SB>2</SB>-K<SB>N</SB>with the first test output value from the circuit K<SB>1</SB>respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a technique for reducing the number of test pins and test time.

  In a semiconductor integrated circuit equipped with a plurality of circuits, a pin is switched from the normal mode to the test mode using a pin (mode pin) assigned for mode setting among a plurality of pins connected to the outside of the chip. Each circuit is tested. Below, what is used for a test among a plurality of above-mentioned pins is called a test pin. A conventional test in a semiconductor integrated circuit is disclosed in Patent Document 1, for example.

  In a semiconductor integrated circuit equipped with N circuits, in order to perform a 1-bit test, a 1-bit test input is externally input to the N circuits via N input test pins. A value is input and a test output value is output to the outside via each of N output test pins. Each circuit is tested by comparing the test output value with a predetermined expected value (1 bit).

  Accordingly, (2 × N) test pins are required to perform a test for 1 bit, and (2 × N × n) test pins are required to perform a test for n bits. Is required. Therefore, there is a problem that the number of necessary test pins becomes enormous according to the number of circuits N and the bit length n.

  In order to solve such a problem, it is possible to perform a test for each circuit by sequentially shifting the test time in N circuits. That is, one circuit selected using N selectors is connected to n input test pins and n output test pins to perform one test (one cycle). By repeating this N times (N cycles), it is possible to test N circuits using a total of (2 × n) test pins including n input test pins and n output test pins. It becomes possible.

JP-A-6-242188

  However, when the test is performed sequentially with the test time shifted using the selector, the number of test pins can be increased to 1 / N times, but there is a problem that the test time increases N times.

  The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor integrated circuit capable of reducing the number of test pins without increasing the test time.

  In one embodiment of the present invention, the same test input value input from one input test pin is input to all the circuits. The first test output value from one circuit is input to comparison means (not shown) provided outside the chip and is compared with a predetermined value. The first test output value from one circuit is input to the coincidence / mismatch detection circuit. The second test output value from another circuit is input to the coincidence / mismatch detection circuit. The coincidence / non-coincidence detection circuit compares the second test output value from another circuit with the first test output value from one circuit, respectively.

  According to the present invention, since information to be output to the outside of the chip can be collected, the number of test pins can be reduced without increasing the test time.

  In the same circuit, when the same test input value is inputted in the same circuit, the test output value outputted as a result of the test becomes the same, and the output test pins are reduced. Features. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Embodiment 1>
FIG. 1 is a schematic diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment.

In FIG. 1, the semiconductor integrated circuit includes N (an integer of 2 or more) identical circuits K _{1 to} K _N. In this semiconductor integrated circuit, as indicated by the alternate long and short dash line, a transition is made from the normal mode to the test mode using a pin (mode pin) assigned for mode setting among a plurality of pins connected to the outside of the chip. In the state, each circuit is tested. Hereinafter, a test operation when the semiconductor integrated circuit is set to the test mode will be described. As indicated by the dotted lines, selectors are arranged at the front and rear stages of each circuit, and the input / output signals of each circuit are switched according to the mode.

In the test mode, the same test input value (n (an integer of 2 or more) bits) input from n input test pins is input to the circuits K _{1 to} K _N.

The test output value (first test output value) output from the circuit K ₁ (one circuit) is branched into two paths. On the other hand, in the path, the first test output value from the circuit K ₁ is input to a comparison means (not shown) provided outside the chip and is compared with a predetermined expected value (n bits). The comparison means outputs a value “1” if the test output value output from the circuit K ₁ matches the expected value as a result of the comparison, and outputs a value “0” if they do not match. Output. Note that the expected value is a test output value output from the circuits K _{1 to} K _N in a normal operation.

In the other path, the first test output value from the circuit K ₁ is input to the coincidence / mismatch detection circuit D.

The test output values (second test output values) output from the circuits K _{2 to} K _N (other circuits) are input to the coincidence / mismatch detection circuit D. The coincidence / mismatch detection circuit D compares the second test output values from the circuits K _{2 to} K _N with the test output value from the circuit K ₁ , respectively. As a result of the comparison, if all match, the value “1” is output as the determination flag F (determination signal), and if there is a mismatch, the value “0” is output as the determination flag F. Output.

  FIG. 2 is a schematic diagram showing an internal configuration of the coincidence / mismatch detection circuit D of FIG. As shown in FIG. 2, the coincidence / noncoincidence detection circuit D includes a set of (N−1) XOR circuits (2 inputs) and 1 AND circuit ((N−1) inputs). In FIG. 2, only a configuration corresponding to one bit of the test input value is shown, and n such sets are provided for the n-bit test input value.

In (N-1) XOR circuits, the second test output value from the circuits K _{2 to} K _N is input to one input terminal, and the first test output value from the circuit K 1 is input to the other input terminal. . Each XOR circuit inputs a value “1” to the AND circuit only when the signal input to one input terminal matches the signal input to the other input terminal. The AND circuit outputs the value “1” only when all the signals input from the (N−1) input terminals are the value “1”. Thereby, the coincidence / non-coincidence detection circuit D outputs the value “1” only when all of the second test output values from the circuits K _{2 to} K _N match the first test output value from the circuit K _1. Can do.

  For an n-bit test input value, one AND circuit (n input) is connected to the subsequent stage of n AND circuits, and a signal output from the one AND circuit is determined as a determination flag F. And it is sufficient. That is, only when the value “1” is output from all the n AND circuits in the preceding stage, the value “1” is output from the one AND circuit in the subsequent stage.

In FIG. 1, since the same test input values are input to the circuits K _{1 to} K _N , it is expected that the output test output values are all the same when all are normal. Accordingly, by detecting whether the value “0” is output from the comparison means or the coincidence / mismatch detection circuit D, it is possible to detect a malfunction of the semiconductor integrated circuit. That is, a defect detection unit (not shown) is provided outside the chip, and when the value “1” is output from both the comparison unit and the coincidence / mismatch detection circuit D, it is not detected as a defect. If the value “0” is output from the coincidence / non-coincidence detection circuit D or both, it is detected as a defect.

Thus, in the semiconductor integrated circuit according to the present embodiment, not all of the test output values from the circuits K _{2 to} K _N are output to the outside of the chip via the output test pins, but the coincidence / mismatch detection circuit D After the comparison, a single determination flag F is collected and output outside the chip. Therefore, since information to be output to the outside of the chip can be collected from (N−1) bits to 1 bit, the number of necessary test pins can be reduced. Further, since the circuits K _{1 to} K _N are tested in one cycle instead of N cycles, it is possible to prevent the test time from increasing N times.

<Embodiment 2>
In the first embodiment, in the coincidence / non-coincidence detection circuit D, for example, when a malfunction that always outputs the value “1” occurs, the malfunction of the circuits K ₁ to K _N cannot be detected. Therefore, the normality of the coincidence / mismatch detection circuit D may be confirmed in the previous step of testing the circuits K ₁ to K _N.

FIG. 3 is a schematic diagram showing the configuration of the semiconductor integrated circuit according to the second embodiment. FIG. 3 is a circuit diagram between the circuits K _{2 to} K _N and the coincidence / mismatch detection circuit D in order to confirm the normality of the coincidence / mismatch detection circuit D in the semiconductor integrated circuit of FIG. 1 according to the first embodiment. , Selectors M _{1 to} M _N-1 (selection means) are interposed.

The selectors M _{1 to} M _N-1 have a select signal input terminal (not shown), and select one of the two signals input to the input terminals T1 to T2 according to a select signal input from the outside of the chip and output it. To do. In the selector M _k (1 ≦ k ≦ (N−1)), the second test output value is input from the circuit K _{k + 1} to the input terminal T1, and the n-bit length different from the expected value is input to the input terminal T2. Is assumed to be input (hereinafter referred to as an unexpected value). As the non-expected value, one value different from the expected value (for example, an inverted value of the expected value) may be input, or a plurality of values different from the expected value are sequentially input at different times. Also good. Further, the n-bit unexpected value is input from n test pins different from the input test pins and distributed to (N−1).

Hereinafter, with reference to FIG. 3, a process of confirming the normality of the coincidence / mismatch detection circuit D in the previous process of the tests of the circuits K _{1 to} K _N will be described. Specifically, an unexpected value is sequentially input to the input terminals T2 of the selectors M _{1 to} M _N−1 to check whether the coincidence / mismatch detection circuit D operates normally and outputs a value “0”.

First, the selector M ₁ selects the unexpected value and the selectors M _{2 to} M _N-1 select the second test output values from the circuits K _{3 to} K _N , respectively. Check if 0 ”is output. This makes it possible to check whether match or mismatch detection circuit D when defective circuit K ₂ is generated to work properly.

Next, each to select the second test output value from the circuit K _2, K ₄ ~K _N the selector _{M 1, M 3 ~M N-} 1 causes a selected non-expected value in the selector M _2, match or mismatch detection It is confirmed whether the circuit D normally outputs the value “0”. This makes it possible to check whether match or mismatch detection circuit D when defective circuit K ₃ is generated to work properly.

Hereinafter, similarly, with respect to the circuits K _{4 to} K _N , it is confirmed whether or not the coincidence / mismatch detection circuit D operates normally. Thereby, the normality of the coincidence / mismatch detection circuit D can be confirmed for all the circuits K _{2 to} K _N.

  That is, the semiconductor integrated circuit of FIG. 3 uses a non-expected value as the normality confirmation value for confirming the normality of the coincidence / non-coincidence detection circuit D so that the comparison results do not coincide.

As described above, in the semiconductor integrated circuit according to the present embodiment, the second test output value or the normality confirmation value is selectively input to the coincidence / mismatch detection circuit D via the selectors M _{1 to} M _N−1. I am letting. Therefore, the normality of the coincidence / mismatch detection circuit D can be confirmed in the previous process of testing the circuits K ₁ to K _N. Therefore, it is possible to increase the accuracy of the test.

<Embodiment 3>
In the second embodiment, a case has been described in which an unexpected value input from n test pins different from the input test pin is used as a normality confirmation value so that the comparison result does not match. However, the present invention is not limited to this, or the normality confirmation value may be given from the input test pin.

FIG. 4 is a schematic diagram showing an example of the configuration of the semiconductor integrated circuit according to the third embodiment. 4 includes a selector between the circuit K ₁ and the coincidence / mismatch detection circuit D in the semiconductor integrated circuit of FIG. 3 (intervene between the circuits K _{1 to} K _N and the coincidence / mismatch detection circuit D, respectively). The selectors are renumbered so that they become selectors M _{1 to} M _N ), and an input terminal T 3 is provided to each of the selectors M _{1 to} M _N to input a test input value.

In addition, an n-bit long unexpected value is input to the input terminal T2 of the selector _Mk in FIG. 3, but a 1-bit distributed signal is input in FIG. It is assumed that this distribution signal is input from one test pin different from the input test pins and distributed to (N−1).

Hereinafter, with reference to FIG. 4, a process of confirming the normality of the coincidence / mismatch detection circuit D in the pre-process of the tests of the circuits K _{1 to} K _N will be described. Note that the 1-bit value distribution signal input to the input terminals T2 of the selectors M _{1 to} M _N always takes the value “0”. Also, the n-bit test input value is “100... 00” (only the first bit has the value “1”), “010... 00” (only the second bit has the value in the test of one circuit. It is assumed that n values from “1”) to “000... 01” (only the nth bit is a value “1”) are sequentially taken (n cycles).

First, the distribution signal having the value “0” is selected by the selector M ₁ , and the second test output values from the circuits K _{2 to} K _N are respectively selected by the selectors M _{2 to MN} . In this state, the test input value is sequentially changed in the above-described n ways to check whether the coincidence / mismatch detection circuit D normally outputs the value “0”. Thereby, it is possible to confirm whether or not the coincidence / mismatch detection circuit D operates normally when a failure occurs in the circuit K ₁ . Further, by sequentially changing the test input values in the above-described n ways, it is possible to sequentially confirm the n sets of the set in FIG. In FIG. 2, the distribution signal having the value “0” is input to all (n × N) XOR circuits (that is, the selector M _k has the input 1-bit length value). 0 ”is converted to an n-bit length value“ 000... 00 ”).

Next, the selector M2 selects the distribution signal having the value “0” and the selectors M ₁ and M _{3 to} M _N select the second test output values from the circuits K ₁ and K _{3 to} K _N , respectively. In this state, the test input value is sequentially changed in the above-described n ways to check whether the coincidence / mismatch detection circuit D normally outputs the value “0”. This makes it possible to check whether match or mismatch detection circuit D when defective circuit K ₂ is generated to work properly.

Hereinafter, similarly, regarding the circuits K _{3 to} K _N , whether or not the coincidence / mismatch detection circuit D operates normally is confirmed. Thereby, the normality of the coincidence / mismatch detection circuit D can be confirmed for all the circuits K _{1 to} K _N.

  Thus, in the semiconductor integrated circuit according to the present embodiment, a normality confirmation value for confirming the normality of the coincidence / mismatch detection circuit D is given from the input test pin. Therefore, the number of test pins can be further reduced as compared with the second embodiment.

In the above description, the case where only the test output value output from the circuit K ₁ is compared with the expected value has been described with reference to FIG. However, the present invention is not limited thereto, or as shown in FIG. 5, by providing the selector M, not only the test output values from the circuit K ₁ but also the test output values from the circuits K _{2 to} K _N are expected. You may compare with a value. As a result, it is possible to specify in which of the circuits K ₂ to K _N a failure has occurred.

  In addition, the selector M may be provided in the semiconductor integrated circuit of FIGS. 1 and 3 without being limited to the semiconductor integrated circuit of FIG.

<Embodiment 4>
FIG. 6 is a schematic diagram showing a configuration of a semiconductor integrated circuit according to the fourth embodiment. FIG. 6 shows the semiconductor integrated circuit of FIG. 1 according to the first embodiment, in which the coincidence / mismatch detection circuit D is provided as the match / mismatch detection circuits D _{1 to} D _N-1 corresponding to the circuits K ₂ to K _N, respectively. The judgment flags F _{1 to} F _N-1 are output. In FIG. 2, the coincidence / mismatch detection circuits D _{1 to} D _N-1 omit one rear AND circuit (not shown) and output the outputs from the n preceding AND circuits to the determination flags F ₁ to F, respectively. _N-1 .

As described above, in the semiconductor integrated circuit according to the present embodiment, by using the coincidence / mismatch detection circuits D _{1 to} D _N-1 corresponding to the circuits K ₂ to K _N , (N−1) Determination flags F _{1 to} F _N-1 are output. Therefore, in addition to the effect of the first embodiment, it is possible to specify which of the circuits K ₂ to K _{N has} a problem.

1 is a schematic diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment. 2 is a schematic diagram illustrating an internal configuration of a coincidence / mismatch detection circuit according to Embodiment 1. FIG. FIG. 6 is a schematic diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment. FIG. 6 is a schematic diagram illustrating an example of a configuration of a semiconductor integrated circuit according to a third embodiment. FIG. 10 is a schematic diagram illustrating another example of the configuration of the semiconductor integrated circuit according to the third embodiment. FIG. 6 is a schematic diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment.

Explanation of symbols

  D Match / mismatch detection circuit, F determination flag, K circuit, M selector, T1 to T3 input terminals.

Claims (6)

A semiconductor integrated circuit having a plurality of identical circuits mounted thereon,
A first test output value that is a test output value from one circuit included in the plurality of circuits and a second test output value that is output from another circuit other than the one circuit included in the plurality of circuits. A semiconductor integrated circuit including a coincidence / mismatch detection circuit that compares a test output value and outputs a determination signal indicating coincidence / mismatch. The semiconductor integrated circuit according to claim 1,
The coincidence / mismatch detection circuit is a semiconductor integrated circuit which is a plurality of match / mismatch detection circuits provided for each of the other circuits. The semiconductor integrated circuit according to claim 1,
The coincidence / non-coincidence detection circuit is a semiconductor integrated circuit which is one coincidence / non-coincidence detection circuit provided in common with the other circuits. The semiconductor integrated circuit according to claim 3,
A semiconductor integrated circuit further comprising selection means for selectively inputting a normality confirmation value for confirming the normality of the second test output value or the coincidence / mismatch detection circuit to the coincidence / mismatch detection circuit. The semiconductor integrated circuit according to claim 4,
The normality confirmation value is a semiconductor integrated circuit including a value such that a comparison result of the coincidence / non-coincidence detection circuit becomes non-coincidence. The semiconductor integrated circuit according to claim 4,
The normality confirmation value is a semiconductor integrated circuit including a value given from an input test pin to the circuit.

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