JP2008124215A - Thin-film semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film semiconductor device having excellent electric characteristics, and to provide a manufacturing method thereof. <P>SOLUTION: The thin-film semiconductor device 10 is provided with a substrate 11, a first insulating layer (undercoat layer) 12, a first conductive layer 13, a second insulating layer 14, a semiconductor layer 15, a channel region 16, a source region 17, a drain region 18, a gate insulating film 19, an interlayer insulating film 20, a gate electrode 21, a source electrode 22, a drain electrode 23, and a bias electrode 24. A bias voltage is applied to an interface of a substrate side of the semiconductor layer 15 by the bias electrode 24 and the first conductive layer 13. Thus, instability such as reduction in an off-current or a threshold voltage can be suppressed and the thin-film semiconductor device 10 can have excellent electric characteristics. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a thin film semiconductor device and a manufacturing method thereof, and the present invention particularly relates to a thin film semiconductor device used for a liquid crystal display device and a manufacturing method thereof.

  Liquid crystal display devices occupy an important position in current major electronic devices such as personal computers and televisions. In this liquid crystal display device, high definition, high speed signal processing, and large screen are regarded as important issues for technological development. In order to realize these problems, the performance of thin film semiconductor devices (TFTs) used for driving each pixel has been improved. As the performance improvement, (1) improvement of carrier mobility and (2) reduction of current when the transistor is not driven (referred to as off-current or sub-threshold current: Ioff) are set as major issues.

  In order to meet these requirements, a technology has been developed to improve carrier mobility by instantaneously heating a conventional amorphous silicon semiconductor thin film with a laser to form a polycrystalline film. It has been put into practical use. Further, in order to improve the electron / hole mobility in the semiconductor layer, technological development for using an alloy of silicon and germanium or germanium as a semiconductor thin film is also being advanced.

  Various structures have been proposed and put into practical use for thin film semiconductor devices necessary for driving each pixel of liquid crystal. The structure of a thin film semiconductor device can be roughly classified into a bottom gate type and a top gate type.

  By the way, in such a thin film semiconductor device, there are problems that an off-current level is higher than that of a MOS transistor formed on a normal silicon wafer single crystal substrate, and variation in threshold voltage and instability are large. In particular, in a thin film semiconductor device, since the semiconductor layer is generally formed with a thickness of about 100 nm, it is difficult to reduce leakage current such as off-current in the substrate. This is because the semiconductor layer is thin so that the source / drain ends are in contact with or close to the underlying glass substrate or the insulating layer interface, and the channel region of the MOS transistor extends to or reaches the vicinity of the interface. In the vicinity of the base interface, there is a high possibility that the crystal grains are finer than the upper surface area of the film, and an interface exists. This interface tends to cause a leak current to flow beyond the crystal grain boundary.

Patent Document 1 discloses a semiconductor device in which a voltage is applied to a substrate and the entire substrate is set to a common potential.
JP-A-8-18809

  Incidentally, the semiconductor device disclosed in Patent Document 1 has a problem that the substrate itself has a common potential, and a bias voltage cannot be applied to each semiconductor device.

  Therefore, it is possible to apply a bias voltage to each semiconductor device, and by blocking or suppressing a path where leakage current is likely to occur at this interface, it is possible to reduce off-current and to suppress instability such as threshold voltage. There is a demand for thin film semiconductor devices having electrical characteristics.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a thin film semiconductor device having good electrical characteristics and a method for manufacturing the same.

In order to achieve the above-described object, a thin film semiconductor device according to the first aspect of the present invention includes:
A substrate made of resin or glass;
A semiconductor layer formed on the substrate;
A first semiconductor region formed in a surface region of the semiconductor layer;
A second semiconductor region formed in a surface region of the semiconductor layer;
A first electrode formed on the first semiconductor region;
A second electrode formed on the second semiconductor region;
A gate electrode disposed through a gate insulating film between the first semiconductor region and the second semiconductor region in the surface region of the semiconductor layer,
A conductive layer formed of a conductive material so as to face the semiconductor layer is further provided between the substrate and the semiconductor layer.

  An insulating layer may be formed between the substrate and the semiconductor layer.

  The first semiconductor region and the second semiconductor region may be formed so as to extend from a surface region of the semiconductor layer to an interface of the semiconductor layer on the substrate side.

  The semiconductor layer is formed on the substrate, and is formed on a lower surface of the first semiconductor region and the second semiconductor region with a higher resistance than the first semiconductor region and the second semiconductor region. A semiconductor region may be provided.

The thin film semiconductor device is mounted on a liquid crystal display device,
The conductive layer may be formed of the same material as the common electrode of the display unit of the liquid crystal display device.

  The semiconductor layer may be composed of a single layer made of one of silicon, germanium, a mixture thereof, and a carbide of these materials, or a thin film stack made of any of these materials.

  The semiconductor layer may be composed of a single layer of a so-called chalcogenide film such as an oxide, carbide, sulfide, selenium compound, or tellurium compound having semiconductor characteristics, or a thin film stack made of any of these materials.

  The semiconductor layer may be a compound containing zinc as a main component.

  The conductive layer may be made of a conductive oxide.

  The conductive oxide may have translucency.

  The conductive oxide may contain zinc as a main component.

  The conductive oxide may be an oxide containing indium and tin.

In order to achieve the above-described object, a method of manufacturing a thin film semiconductor device according to the second aspect of the present invention includes:
A semiconductor layer forming step of forming a semiconductor layer on a substrate made of resin or glass;
A first semiconductor region forming step of forming a first semiconductor region in a surface region of the semiconductor layer;
A second semiconductor region forming step of forming a second semiconductor region in the surface region of the semiconductor layer;
A first electrode forming step of forming a first electrode on the first semiconductor region;
A second electrode forming step of forming a second electrode on the second semiconductor region;
A gate electrode forming step of forming a gate electrode disposed through a gate insulating film between the first semiconductor region and the second semiconductor region in the surface region of the semiconductor layer, and the substrate and the A conductive layer forming step of forming a conductive layer formed of a conductive material so as to face the semiconductor layer between the semiconductor layer and the semiconductor layer is further provided.

  An insulating film forming step of forming an insulating layer between the substrate and the semiconductor layer may be further provided.

  In the first semiconductor region forming step and the second semiconductor region forming step, the first semiconductor region and the second semiconductor region are formed so as to extend from the surface region of the semiconductor layer to the interface of the semiconductor layer on the substrate side. A semiconductor region may be formed.

The semiconductor layer is formed on the substrate;
In the first semiconductor region forming step and the second semiconductor region forming step, the lower surfaces of the first semiconductor region and the second semiconductor region are lower than the first semiconductor region and the second semiconductor region. A semiconductor region formed with high resistance may be formed.

The thin film semiconductor device is mounted on a liquid crystal display device,
The conductive layer forming step may be performed in the same step as the step of forming the common electrode of the display unit of the liquid crystal display device.

  According to the present invention, it is possible to provide a thin film semiconductor device having good operability by providing a conductive layer between a substrate and a semiconductor layer and controlling the potential of the semiconductor layer.

  A thin film semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
A thin film semiconductor device 10 according to Embodiment 1 of the present invention is shown in the drawing. FIG. 1 is a cross-sectional view showing a configuration example of the thin film semiconductor device 10.

  The thin film semiconductor device 10 of this embodiment is used as a switching element for driving each pixel unit 41 of the liquid crystal display device 40 as shown in FIG. The liquid crystal display device 40 includes drive circuits such as a column driver 42 and a row driver 43 formed on the substrate 11 as shown in FIG. The liquid crystal display device 40 is provided with a plurality of thin film semiconductor devices 10.

  As shown in FIG. 1, the thin film semiconductor device 10 includes a substrate 11, a first insulating layer (undercoat layer) 12, a first conductive layer 13, a second insulating layer 14, a semiconductor layer 15, and a channel region. 16, a source region 17, a drain region 18, a gate insulating film 19, an interlayer insulating film 20, a gate electrode 21, a source electrode 22, a drain electrode 23, and a bias electrode 24. Further, a transparent electrode 31 made of indium-tin oxide for applying a voltage to the pixel portion 41 of the liquid crystal display device 40 is connected to the thin film semiconductor device 10.

  The substrate 11 is made of, for example, a glass substrate. A first insulating layer (undercoat layer) 12 is formed on the upper surface of the substrate 11.

  The first insulating layer 12 includes a silicon nitride film 12a and a silicon oxide film 12b. The silicon nitride film 12a is formed on the main surface of the substrate 11 to a thickness of 100 nm, for example. The silicon oxide film 12b is formed with a thickness of, for example, 100 nm on the silicon nitride film 12a. The first insulating layer 12 can prevent impurities contained in the substrate 11 and the like from diffusing into the semiconductor layer 15.

  The first conductive layer 13 is made of a conductive material, for example, an indium-tin oxide film, and is formed on the first insulating layer 12. The first conductive layer 13 is used to fix or control the potential of the entire thin film semiconductor device 10 from the substrate 11 side. Therefore, a resistivity of about several milliΩ · cm is sufficient for the conductivity required for the first conductive layer 13. The first conductive layer 13 is formed with a thickness of 100 nm, for example. In the present embodiment, the first conductive layer 13 is formed together with a common electrode (not shown) of the pixel unit 41. The first conductive layer 13 may be a zinc oxide transparent conductive film containing Ga, Al, or the like. Further, the first conductive layer 13 is not limited to a light-transmitting conductive film, and an opaque metal film can be used depending on the method of using the thin film semiconductor device 10. In the present embodiment, a plurality of thin film semiconductor devices 10 are formed on the substrate 11. However, since the first conductive layer 13 is provided independently for each thin film semiconductor device 10, each thin film semiconductor device 10 is provided. The same voltage can be applied to the device 10 or a different bias voltage can be applied to each thin film semiconductor device 10. Specifically, the applied voltage can be adjusted for each thin film semiconductor device 10 such that the thin film semiconductor device 10 is an n-channel transistor, −1 V, and the p channel transistor is +1 V.

  The second insulating layer 14 is made of an insulating material such as a silicon oxide film, and is formed on the first conductive layer 13. The second insulating layer 14 is formed with a thickness of 20 nm, for example. As described above, a bias voltage is applied to the first conductive layer 13 in order to fix or control the potential of the thin film semiconductor device 10. The bias voltage is applied to the semiconductor layer 15 through the second insulating layer 14.

The semiconductor layer 15 is made of, for example, Si _x Ge _1-x or the like, and is formed on the first conductive layer 13 with a thickness of, for example, 100 nm. Note that x is preferably in the range of 0.9 to 0.4, and 0.5 is used here. A channel region 16, a source region 17, and a drain region 18 are formed in the surface region of the semiconductor layer 15. A bias voltage is applied to the semiconductor layer 15 from the first conductive layer 13.

The channel region 16 is formed in the surface region of the semiconductor layer 15. Since the channel region 16 has a predetermined threshold voltage, impurities such as phosphorus and boron are diffused in the order of, for example, 10 ¹³ atoms / cm ² to 10 ¹⁴ atoms / cm ² using an ion implantation method or the like.

The source region 17 is formed in the surface region of the semiconductor layer 15. In the source region 17, impurities such as phosphorus, arsenic, antimony, boron, or indium are diffused in the order of, for example, 10 ¹⁵ atoms / cm ² to 10 ¹⁶ atoms / cm ² . A source electrode 22 is formed on the upper surface of the source region 17.

The drain region 18 is formed in the surface region of the semiconductor layer 15. In the drain region 18, impurities such as phosphorus, arsenic, antimony, boron, or indium are diffused with an impurity concentration of about 10 ¹⁵ atoms / cm ² to 10 ¹⁶ atoms / cm ² , for example. A drain electrode 23 is formed on the upper surface of the drain region.

  The gate insulating film 19 is formed of an insulating material, for example, a 100 nm thick silicon oxide film or a 200 nm thick silicon nitride film. The gate insulating film 19 is formed on the channel region 16 formed in the surface region of the semiconductor layer 15.

  The interlayer insulating film 20 is made of an insulating material such as a silicon nitride film, and is formed so as to cover the first insulating layer 12, the semiconductor layer 15, and the gate electrode 21. Further, in the interlayer insulating film 20, a contact hole 20s is formed in a region corresponding to the source electrode 22, a contact hole 20d is formed in a region corresponding to the drain electrode 23, and a contact hole 20b is formed in a region corresponding to the bias electrode. The A silicon nitride film (not shown) is formed on the side walls of the contact holes 20s, 20d, and 20b.

  The gate electrode 21 is made of a conductive material such as chromium or tungsten, and is formed on the gate insulating film 19.

The source electrode 22 is made of a conductive material, such as aluminum, and is formed so as to fill the contact hole 20 s provided in the interlayer insulating film 20 on the source region 17. Note that a titanium nitride film is formed on the side wall of the contact hole 20s as a barrier layer for suppressing a reaction between a metal such as aluminum as an electrode material and Si, Si _x Ge _1-x, or the like.

  The drain electrode 23 is made of a conductive material, such as aluminum, and is formed so as to fill the contact hole 20 d provided in the interlayer insulating film 20 on the drain region 18. A titanium nitride film is formed on the side wall of the contact hole 20s as the barrier layer.

  The bias electrode 24 is made of a conductive material, such as aluminum, and is formed so as to fill the contact hole 20b. A titanium nitride film is formed on the side wall of the contact hole 20b as the barrier layer. By applying a bias voltage to the first conductive layer 13 via the bias electrode 24, it is possible to suppress the drift of transistor characteristics due to the generation of charges near the interface side of the substrate 11 of the semiconductor layer 15. Instability and variation in characteristics can be eliminated.

  In the thin film semiconductor device 10 of the present embodiment, the first conductive layer 13 is formed on the first insulating layer 12, and a bias voltage is applied by the bias electrode 24, whereby the semiconductor layer 15 near the interface side of the substrate 11. It is possible to suppress the drift of transistor characteristics due to the generation of electric charges and the like, and to eliminate the instability of characteristics and the dispersion of characteristics.

  In the present embodiment, in particular, a plurality of thin film semiconductor devices 10 are formed on the substrate 11, but the first conductive layer 13 is provided independently for each thin film semiconductor device 10. Different bias voltages can be applied depending on the thin film semiconductor device 10.

  Next, a manufacturing method of the thin film semiconductor device 10 according to the embodiment of the present invention will be described with reference to the drawings.

First, for example, a substrate 11 made of a glass substrate is prepared.
A silicon nitride film 12a having a thickness of, for example, 100 nm is formed on the substrate 11 by a CVD (Chemical Vapor Deposition) method or the like. Subsequently, a silicon oxide film 12b having a thickness of, for example, 100 nm is formed on the silicon nitride film 12a by a CVD method or the like. As a result, the first insulating layer (undercoat layer) 12 is formed on the substrate 11 as shown in FIG.

  Next, a metal film made of, for example, an indium-tin oxide film is formed on the first insulating layer 12 by sputtering, vacuum evaporation, or the like. Subsequently, patterning is performed on the pattern of the first conductive layer. Thus, the first conductive layer 13 is formed as shown in FIG. When the first conductive layer 13 is formed, a common electrode (not shown) of the pixel portion 41 of the liquid crystal display device 40 on which the thin film semiconductor device 10 is mounted is formed at the same time.

  Subsequently, for example, a silicon oxide film with a thickness of, for example, 20 nm is formed on the first conductive layer 13 by CVD or the like, and the second insulating layer 14 is formed as shown in FIG.

Next, a Si _x Ge _1-x layer 81 is formed by sputtering or the like as shown in FIG. The Si _x Ge _1-x layer 81 is formed to a thickness of 100 nm, for example.

Subsequently, as shown in FIG. 4E, a silicon oxide film 82 is formed on the Si _x Ge _1-x layer 81 to a thickness of, for example, 100 nm. Instead of the silicon oxide film, for example, a 200 nm thick silicon nitride film may be formed.

Next, a mask 91 in which an opening corresponding to a region where the semiconductor layer 15 is to be formed is formed on the silicon oxide film 82. Subsequently, as shown in FIG. 4F, in order to realize a thin film transistor having a predetermined threshold voltage in the surface region of the Si _x Ge _1-x layer 81, an impurity such as phosphorus or boron is ion-implanted. The impurity region 83 is formed by doping in the order of 10 ¹³ atoms / cm ² to 10 ¹⁴ atoms / cm ² .

  Next, the mask 91 is removed, and a conductive film 84 made of, for example, chromium or tungsten is formed on the silicon oxide film 82 to a thickness of, for example, 150 nm by sputtering, vacuum evaporation, or the like as shown in FIG.

  Subsequently, a silicon nitride film (not shown) that functions as a mask material when processing the gate electrode pattern is formed on the conductive film 84 to a thickness of, for example, 100 nm. After processing the silicon nitride film into a pattern corresponding to the gate electrode by photolithography technique and dry etching technique, the conductive film 84 is etched using the silicon nitride film as a mask for dry etching, as shown in FIG. 5 (h). Form.

Next, the silicon oxide film 82 formed under the gate electrode 21 is etched so that a region functioning as a transistor remains, thereby forming the gate insulating film 19. Further, the Si _x Ge _1-x layer 81 is etched so as to correspond to the shape of the gate insulating film 19 to form the semiconductor layer 15. Thereby, the gate insulating film 19 and the semiconductor layer 15 are formed as shown in FIG.

Next, using the gate electrode 21 formed by such a process as a mask, an impurity such as phosphorus or boron is doped into the surface region of the semiconductor layer 15 by ion implantation. This doping region becomes the source region 17 and the drain region 18 of the thin film semiconductor device 10. Therefore, the doping amount is larger than the ion implantation amount for setting the threshold voltage described above, and is on the order of 10 ¹⁵ atoms / cm ² to 10 ¹⁶ atoms / cm ² . In the present embodiment, the impurity is diffused so that the source region 17 and the drain region reach the second insulating layer 14 as shown in FIG. Although this ion implantation is performed through the silicon oxide film 82 that becomes the gate insulating film 19, the silicon oxide film 82 around the gate electrode 21 is removed in advance, and the semiconductor layer 15 is exposed, and then ion implantation is performed directly. It is also possible.

In this embodiment, element isolation is achieved by removing the Si _x Ge _1-x film 81 other than the region functioning as the thin film semiconductor device 10. This removal step for element isolation is performed after the Si _x Ge _1-x film 81 is formed, after the silicon oxide film 82 is formed, or after the gate electrode 21, the source region 17 and the drain region 18 are formed. It is done at this stage.

  Next, as shown in FIG. 6K, a silicon oxide film 20 having a thickness of, for example, 500 nm is formed so as to cover the semiconductor layer 15, the gate insulating film 19, and the first insulating layer 12. Subsequently, contact holes 20s, 20d, and 20b are provided in regions of the silicon oxide film 20 corresponding to the source electrode 22, the drain electrode 23, and the bias electrode 24, respectively. In place of the silicon oxide film 20, a silicon nitride film can be formed.

  A 500 nm thick aluminum film is formed after forming a 10 nm thick titanium nitride film as the barrier layer in each of the contact holes 20 s, 20 d, and 20 b, and these metal films are overlaid using ordinary lithography and dry etching. Are processed into a source electrode 22, a drain electrode 23 and a bias electrode 24.

Thereafter, a transparent electrode 31 made of indium tin oxide (ITO) having a thickness of 100 nm for applying signals from these electrodes / wirings to the liquid crystal display is formed.
From the above steps, the thin film semiconductor device 10 is manufactured as shown in FIG.

  In the manufacturing method of the thin film semiconductor device 10 described above, the semiconductor device includes the step of forming the first conductive layer 13 on the undercoat layer 12 and the step of forming the first insulating layer 14 on the first conductive layer 13. The first conductive layer 13 can be provided in a region facing the layer 15. Accordingly, a bias voltage can be applied to the semiconductor layer 15 via the bias electrode 24 and the first conductive layer 13, and a drift in transistor characteristics due to generation of electric charge in the vicinity of the interface side of the substrate 11 of the semiconductor layer 15 occurs. Thus, it is possible to manufacture a thin film semiconductor device capable of suppressing this and eliminating characteristic instability and characteristic variation.

  Further, in the method of manufacturing the thin film semiconductor device of the present embodiment, the first conductive layer 13 is formed so as to correspond to the semiconductor layer 15 of each semiconductor device 10, so that a different bias voltage is applied to each semiconductor device 10. Is possible. Furthermore, in the present embodiment, the first conductive layer 13 can be formed using the same material in the same process as the common electrode of the pixel portion 41 of the liquid crystal display device 40 formed on the substrate 11.

(Embodiment 2)
A thin film semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. The thin film semiconductor device of the present embodiment is different from the thin film semiconductor device 10 of the first embodiment. In the first embodiment, the semiconductor layer is formed on the first conductive layer via the second insulating layer. In the embodiment, the semiconductor layer is formed directly on the first conductive layer. Portions common to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  A thin film semiconductor device 50 according to this embodiment is shown in FIG. FIG. 7 is a cross-sectional view showing a configuration example of the thin film semiconductor device 50. As shown in the figure, the thin film semiconductor device 50 includes a substrate 11, a first insulating layer (undercoat layer) 12, a first conductive layer 13, a semiconductor layer 55, a channel region 16, a source region 57, and a drain region. 58, a gate insulating film 19, an interlayer insulating film 20, a gate electrode 21, a source electrode 22, and a drain electrode 23. Further, in the present embodiment, a transparent electrode 31 for supplying a signal to a liquid crystal display device (not shown) is formed.

The semiconductor layer 55 is made of, for example, Si _x Ge _1-x, and is formed directly on the first conductive layer 13 unlike the first embodiment. In the present embodiment, the semiconductor layer 55 is formed thicker than that in the first embodiment, and is formed to a thickness of, for example, 250 nm. This is because if the semiconductor layer 55 is formed thin, doping impurities may penetrate through the semiconductor layer 55 and reach the first conductive layer 13 during ion implantation for forming the source region 57 and the drain region 58. This is because it becomes difficult to realize a transistor because the first conductive layer 13 shorts between the source and the drain in such a situation.

  Note that the semiconductor layer 55 forms a source region 57 and a drain region 58 containing a high concentration of impurities only in the surface region, and a region having a low content of impurities or a high resistance not containing them under these regions. The semiconductor region may be formed.

  As described above, in the thin film semiconductor device 50 according to this embodiment, the semiconductor layer 55 is thickened to provide a high-resistance semiconductor layer not doped with impurities under the source region 57 and the drain region 58 doped with impurities. As a result, it is possible to omit the insulating layer, to avoid a short circuit between the source region 57 and the drain region 58 due to the first conductive layer 13 and to control the bias potential from the substrate 11 side.

Further, since the thin film semiconductor device 50 of the present embodiment does not have the second insulating layer 14 interposed between the first conductive layer 13 and the semiconductor layer 15 as in the first embodiment, the first conductive layer 13 and the semiconductor layer 15 are not provided. There is an advantage that trapped charges are less likely to accumulate at the interface of the substrate. That is, fluctuations in the thin film semiconductor characteristics during long-term operation can be reduced.

  Further, the thin film semiconductor device 50 of the present embodiment can be manufactured by substantially the same method as the manufacturing method of the thin film semiconductor device 10 of the first embodiment. For example, when the thin film semiconductor device 50 is manufactured, the step of forming the second insulating layer 14 is excluded. Further, in the step of forming the semiconductor layer 55, the semiconductor layer 55 is formed to be thicker than that of the first embodiment, for example, to a thickness of 250 nm. Further, a region where impurities are not diffused or diffused at a very low concentration is formed under the source region 57 and the drain region 58 of the semiconductor layer 55.

  In the manufacturing method of the thin film semiconductor device 50 of the present embodiment, the step of forming the second insulating layer 14 can be omitted. Furthermore, in the manufacturing method of the present embodiment, the semiconductor film thickness needs to be slightly thicker than the structure of Example 1, but has the following advantages. In the case where the first conductive layer 13 is formed of indium-tin oxide, the indium-tin oxide can form a film having a very coarse crystal grain size of 200 nm to 500 nm without special measures. The SiGe film (semiconductor layer 55) formed thereon has a large particle size of 100 nm to 200 nm in a state where the film is formed without performing the heat treatment for solid phase growth described above. In this phenomenon, when a zinc oxide film is formed as a semiconductor layer, a polycrystalline film having a structure in which the crystal grain size of indium-tin oxide as the first conductive layer is extended as it is can be obtained. The larger the particle size, the higher the mobility of electrons and holes, and the better electrical characteristics can be obtained.

  However, in the structure of this embodiment, when a relatively high temperature heat treatment of 400 ° C. to 500 ° C. is performed in the manufacturing process of the thin film semiconductor device, undesirable impurities from the material of the first conductive layer diffuse into the semiconductor layer and Consideration in the manufacturing process is necessary because the leakage current characteristics may be deteriorated. Special care should be taken especially when the conductive layer contains zinc such as ZnO. This is because when zinc diffuses into the silicon-based semiconductor layer, a deep impurity level is formed, and the leakage current of the source / drain is increased even in a very small amount.

(Example 1)
In this example, non-alkali glass was used as the substrate 11 and the undercoat layer 12 was formed using a plasma CVD apparatus at a substrate temperature of 400 ° C. as described above. Next, an indium-tin oxide film having a thickness of 100 nm was formed using a magnetron sputtering apparatus. Next, a 20 nm thick silicon oxide film was formed again using a plasma CVD apparatus.

A Si _x Ge _1-x film having a thickness of 100 nm was formed on the layered structure using an ECR (Electron Cychrotron Resonance) sputtering apparatus. In this film formation, a sputter target in which a Si plate and a Ge plate were bonded together in a mosaic shape was used. The composition of Si and Ge of the film formed at this time was controlled by the area occupied by each plate in the target plane. In the present example, targets having the same area ratio were applied. As a result of obtaining the elemental composition of the 100 nm-thick Si _x Ge _1-x film obtained by using a normal mass spectrometer, the atomic composition of Si and Ge was approximately 50%, respectively. That is, x was 0.5. This sputtering apparatus can be formed while controlling the substrate temperature in the range from room temperature to 500 ° C. Here, however, the ECR sputtering apparatus performed with the substrate temperature set at 450 ° C. has a plurality of sputtering chambers, Different types of films can be formed continuously by moving between chambers in a vacuum without exposure to the atmosphere. In this example, using this function, after forming the Si _x Ge _1-x film, the sample was moved to another sputtering chamber in a vacuum, and an SiO ₂ film having a thickness of 100 nm was formed by ECR sputtering.

Next, a region other than the n-channel transistor is covered with a high heat resistance resist using a lithography technique, and Si _x Ge _{1-x in a} region not covered with the resist through a silicon oxide film with an ion implantation apparatus at a substrate temperature of 300 ° C. Was ion-implanted at 40 keV. The dose at this time was 5 × 10 ¹³ atoms / cm ² . Next, after removing the resist, similarly, using the resist as a mask, phosphorus ions were implanted at 2 × 10 ¹³ atoms / cm ² at 120 keV into a region to be a p-channel transistor. After removing these resists with a so-called asher device using oxygen plasma, the surface of the silicon oxide film 6 is cleaned with ultraviolet irradiation or ozone + sulfuric acid, and then a tungsten (W) film having a thickness of 200 nm is formed by ordinary magnetron sputtering. It was formed using an apparatus. Thereafter, a silicon nitride film having a thickness of 150 nm was formed using a plasma CVD (Chemical Vapor Deposition) apparatus. This silicon nitride film was processed into a gate electrode / wiring pattern using a lithography technique and a dry etching technique. Subsequently, the tungsten film was processed using the pattern made of the silicon nitride film as a mask to form a gate electrode.

Next, the insulating film formed under the gate electrode is etched so that the shape of a region functioning as a transistor remains, so that a gate insulating film is formed. Further, the Si _x Ge _1-x layer is etched so as to correspond to the shape of the gate insulating film, thereby forming a semiconductor layer.

Next, in the same procedure as in the previous ion implantation, phosphorus ions are implanted at a substrate temperature of 300 ° C. and a dose of 5 × 10 ¹⁵ atoms / cm ^{2 at} a substrate temperature of 300 ° C., and a p-channel is formed. The transistor region can be formed in a self-aligned manner with respect to the gate electrode without using a photoresist mask for forming a source region and a drain region by implanting boron at about 5 × 10 ¹⁵ atoms / cm ² at 50 keV. It was.

  Next, an interlayer insulating film made of a silicon oxide film having a thickness of 500 nm was formed at 400 ° C. using a plasma CVD apparatus. A contact hole was opened at a predetermined portion of the insulating film using a lithography technique and a dry etching technique. At this time, the opening forming step was performed in two steps classified according to the size of the desired contact hole. That is, the size of the contact hole for conduction for applying a voltage to the first conductive layer is very large compared to the contact hole to the circuit constituent element group such as the thin film transistor, and therefore these can be processed in parallel. It ’s difficult. Next, after depositing 10 nm of titanium nitride using a sputtering apparatus, an aluminum film having a thickness of 500 nm was continuously formed using the same sputtering apparatus. Then, the stacked structure of the titanium nitride film and the aluminum film was processed using a normal photolithography technique and a dry etching technique to form electrodes / wirings. When the thin film semiconductor device thus formed is used as a switching element of an active matrix liquid crystal, an ITO film or a zinc oxide film, which is a transparent conductive film, is formed thereafter to form a liquid crystal driving electrode. In this embodiment, this step and subsequent steps are omitted.

The characteristics of the semiconductor device thus obtained were evaluated. In this example, the Si _x Ge _1-x film formation temperature was 450 ° C. and a relatively high temperature. This is because the purpose is to obtain a film already having coarse crystal grains in the film formation process. Further, after the Si _x Ge _1-x film was formed, heat treatment was performed in a nitrogen atmosphere at 500 ° C. for 8 hours. This was performed for the purpose of coarsening the crystal grains by solid phase growth. Note that the relation between the coarsening of crystal grains by solid phase growth and the substrate temperature during film formation was examined. The average crystal grain size in the in-plane direction of the Si _x Ge _1-x polycrystalline film formed by setting the substrate temperature to 450 ° C. was 100 nm to 150 nm according to X-ray diffraction measurement. On the other hand, the film formed at room temperature was almost amorphous. When these films were subjected to heat treatment for solid phase growth, the particle size was increased to about 300 nm by 450 ° C. heat treatment. In other words, it was confirmed that the grain growth was caused by growing the crystal nuclei from the amorphous state rather than growing from the state where the crystal grains existed in advance. This is because if a grain boundary or the like exists before the solid phase growth treatment, the discontinuous region becomes an obstacle to growth. The section of the device using a Si _x Ge _1-x film formed at a substrate temperature of 450 ° C. was observed with a transmission electron microscope (TEM). It was found that the film in the observation region of the device cross section had a crystal grain size of 50 nm to 200 nm. In the TEM cross section observation, the element cross section was analyzed with an energy dispersive X-ray analyzer to evaluate the elemental composition in the film.

It was found that the Si _x Ge _1-x film was close to the element composition x = 1 expected from the sputter target, that is, composed of 55 atomic% Si and 45 atomic% Ge.

In addition, the electron mobility of the n-channel thin film MOS transistor obtained from the relationship between the source-drain current of the thin film semiconductor device and the applied voltage between the source and gate electrodes is 90 cm ² / V · s to 170 cm ² / V · s. The hole mobility obtained from the p-channel thin film MOS transistor was 50 cm ² / V · s to 90 cm ² / V · s. In the measurement, the bias voltage to the substrate side was -1 V for the n-channel transistor and +1 V for the p-channel transistor. The mobility in the above-mentioned n-channel transistor showed a high value close to that of a polycrystalline silicon film (generally called low-temperature polysilicon) whose crystal grain size was increased by annealing using an excimer laser.

  Also, the source-drain current (sometimes referred to as off-state current) when the transistor is not driven is a MOS transistor having a channel length of 10 μm and a channel width of 50 μm. The p-channel transistors showed the same characteristics as the transistors formed on the single crystal substrate, and the p-channel transistors were 0.4 pA / mm to 1.0 pA / mm.

  In this example, a thin film semiconductor device having high mobility was obtained without forming a substrate 450 at the time of film formation even if laser annealing treatment for crystal grain coarsening was not performed after semiconductor film formation like low-temperature polysilicon. Because of the high energy of flying particles in ECR sputtering, the substrate surface could be moved relatively easily during deposition, and for solid-phase growth after film formation. Although the effect of growing crystal grains by the effect of heat treatment or the like is also conceivable, by applying a bias voltage from the substrate side to the semiconductor layer in the present invention, the path of the current flowing through the channel region is near the surface of the layer. The effect of restricting carriers to flow through a coarser crystal grain region by pushing to a greater extent is significant.

  That is, the mobility is improved by 5% to 13% from the value measured with the potential floating in the same manner as the conventional MOS type thin film semiconductor device without applying a bias voltage to the substrate side, and the off current is more effective. A reduction of 12% to 20% was observed. The reason why the thin film semiconductor device exhibiting such a low off-state current is obtained is that the back bias voltage is applied to fix the potential from the substrate side of the semiconductor thin film layer according to the embodiment of the present invention.

  On the other hand, in a semiconductor system composed of a large number of thin film semiconductor element groups such as a switching thin film semiconductor element array and a thin film semiconductor integrated circuit device of a liquid crystal display device, a fixed charge generated at the interface between the thin film transistor and the substrate during long-term driving is Variations in characteristics such as threshold voltage, and variations in the amount of variation within the element group, along with the variations, are factors that reduce the operating margin of the entire system. These variations can be reduced by applying a voltage of about 1 V to the first conductive layer 13 as described above, as well as the variation in the system.

  Although the substrate bias was effective in suppressing fluctuations in transistor characteristics even at zero potential, a more remarkable effect was observed by applying a voltage of several volts as described above. This is because, as described above, by applying a bias, an effect of pushing a current that flows near the substrate side interface near the channel of the transistor is produced. As a result, a transistor with a high carrier mobility can be realized, and the oozing of carriers to the charge trapping site region that is likely to occur near the substrate interface can be suppressed. In the thin film, the crystal grains in the vicinity of the substrate interface at the initial stage of film formation are fine, and this corresponds to the phenomenon that the crystal grains become coarser as the distance from the substrate interface increases. That is, as described above, the mobility in the polycrystalline thin film is lowered mainly by scattering of carriers at the grain boundaries. In addition, there are a large number of carrier trap levels at the grain boundary, and each level exists at a high density. Therefore, in the vicinity of the substrate interface, the grain boundary scattering frequency in the carrier movement direction due to the grain boundaries of the fine crystal grains becomes high, so that the mobility is significantly reduced. Further, since scattering at the interface is added, it further decreases in the polar interface region. Similarly, since the carrier trap level density increases near the interface, carriers are easily trapped, and the characteristics fluctuate during long-term operation. Therefore, the amount of carriers flowing in this region can be reduced by applying a bias potential from the outside to the substrate side.

  A conventional thin film transistor is mounted on an insulator such as a glass substrate and does not have a function of adjusting a potential from the substrate side. For this reason, while the thin film transistor is driven, it is captured by various charge traps in the vicinity of the interface, and as a result, characteristic drift such as threshold voltage and leak current of the MOS transistor occurs, resulting in unstable operation. In large-scale thin-film semiconductor devices, especially switching transistor arrays in liquid crystal display devices or integrated circuits composed of a plurality of thin-film transistors, the drive margin of the device is greatly increased due to variations in the characteristics between elements and variations in the drift characteristics between elements. to shrink. On the other hand, by providing an electrode for fixing the substrate potential as in this embodiment, it is possible to suppress these fluctuation amounts and to make the drift characteristics of the entire integrated circuit such as the transistor array constant or reduced. Therefore, it is possible to suppress the operation margin of the thin film semiconductor device from being reduced.

  In addition, a device to which the present invention is applied and a device to which the present invention is not applied are prototyped in a liquid crystal display device having 80,000 pixels, and the threshold voltage fluctuation amount due to drift is compared. This long-term test was based on continuous driving at 80 ° C. for 500 hours. In the array in which the first-layer conductive film for substrate bias is not formed, the amount of drift voltage due to long-time driving of the in-plane threshold voltage is 2 V to 6 V, and the variation is large. On the other hand, in the array to which the present invention is applied, even when the substrate bias voltage is set to 0V, the drift amount is improved to 1.5V to 3V due to the effect of fixing the potential. Further, when the substrate bias voltage is set to −1V, the region where the current flows is separated from the vicinity of the substrate interface and is limited to the vicinity of the surface of the semiconductor thin film, which is 20 in comparison with the conventional structure in which the first conductive layer 13 of the present invention is not provided. Improved by about%.

(Example 2)
In Example 1, the semiconductor layer 15 was formed after forming the second insulating film 14 on the first conductive layer 13 for applying the bias voltage. Therefore, the bias voltage from the substrate 11 side is applied to the semiconductor layer 15 through the second insulating film 14. In this embodiment, the second insulating film 14 is omitted, and the semiconductor layer 15 is formed directly on the first conductive layer 13.

  However, in this structure, if the semiconductor layer 15 is thin, when doping is performed by ion implantation for forming the source region 17 and the drain region 18 described in the first embodiment, the doping impurity penetrates the semiconductor layer 15 and the first conductivity is increased. There is a possibility of reaching layer 13. In such a situation, since the source and drain are short-circuited by the first conductive layer 13, it is difficult to realize a transistor in the first place. Therefore, in this embodiment, the thickness of the semiconductor layer 55 is set to 250 nm, which is thicker than that of the first embodiment. The other process conditions were the same as in Example 1. Thus, by increasing the thickness of the semiconductor layer 55, the high-resistance semiconductor layer 55 that is not doped with impurities is provided below the source region 57 and the drain region 58 that are doped with impurities. With this structure, a short circuit between the source and the drain due to the first conductive layer 13 is avoided, and the bias potential can be controlled from the substrate 11 side.

In the structure of this example, the semiconductor film thickness needs to be slightly larger than that of the structure of Example 1, but the following advantages were observed. That is, indium-tin oxide can form a film having a very coarse crystal grain size of 200 nm to 500 nm without special measures. Then, the Si _x Ge _1-x film formed thereon has a large particle size of 100 nm to 200 nm in a state where the film is formed without performing the heat treatment for solid phase growth described above. It was. This phenomenon indicates that when a zinc oxide film is formed as a semiconductor layer, a polycrystalline film having a structure in which the crystal grain size of indium-tin oxide as the first conductive layer is extended as it is can be obtained. Therefore, this embodiment is useful when a thin film semiconductor device made of such a material is formed.

  In this embodiment, since there is no second insulating layer 14 interposed between the first conductive layer 13 and the semiconductor layer 15 as in the first embodiment, trapped charge is accumulated at the interface between the first conductive layer 13 and the semiconductor layer 55. There is an advantage that it is difficult to occur. That is, it has been found that the fluctuation of the semiconductor characteristics during the long-term operation is extremely small. For example, in the same manner as in Example 1, a device to which the present invention was applied and a device to which the present invention was not applied were manufactured on a liquid crystal display device having 80,000 pixels, and the threshold voltage fluctuation amount due to drift was compared. This long-term test was based on continuous driving at 80 ° C. for 500 hours. When driven for a long time, the drift amount can be suppressed from 0.5 V to 1.0 V, and it can be said that the present embodiment can obtain better results than the first embodiment in terms of drift suppression.

  However, in this structure, when a relatively high temperature heat treatment of 400 ° C. to 500 ° C. is performed in the manufacturing process of the thin film semiconductor device, undesirable impurities from the first conductive layer diffuse into the semiconductor layer and deteriorate the leakage current characteristics of the transistor. Consideration of handling is necessary. Special care should be taken especially when the conductive layer contains zinc such as ZnO. This is because, as is well known, when zinc diffuses into the silicon-based semiconductor layer, a deep impurity level is formed, and even a very small amount increases the leakage current of the source / drain.

The present invention is not limited to the above-described embodiments, and various modifications and applications are possible.
For example, in the above-described embodiment, a top-gate thin film transistor in which a semiconductor device such as a thin film transistor is formed over a flat base layer has been described as an example, but the present invention can also be applied to a bottom-gate thin film transistor. In this case, an electrode layer for substrate bias as shown in this embodiment is provided on the top of the semiconductor device. In such a bottom gate type structure, a channel region where carriers flow flows near the substrate side interface of the semiconductor thin film. Since this region is composed of fine crystal grains as described above, high mobility cannot be expected. Therefore, when the present invention is applied to a bottom gate type semiconductor device, a positive voltage may be applied to the bias electrode provided on the surface in the case of an n-channel transistor and a negative voltage in the case of a p-channel transistor. This makes it possible to make the carrier movement region close to the surface of the semiconductor film, so that the mobility can be improved.

In the above-described embodiments, when referring to the number of elements and the like (including composition, chemical formula, number, numerical value, amount, range, etc. of the compound), it is limited to a specific number when clearly indicated and in principle. Except sometimes, it is not limited to the specific number, and may be a specific number or more. For example, when it is described as a SiGe or Si _x Ge _1-x film, the film composition display includes all composition ranges of the plurality of elements other than a film made of a single substance such as Si or Ge.

  Further, when referring to a silicon oxide film, unless otherwise specified, generally, various silicon oxide films containing various additives and auxiliary components, that is, PSG (Phospho Silicate Glass) film, BPSG (Boro It shall include other single films or composite films such as -Phospho Silicate Glass) film, TEOS (Tetra-Ethoxy Silane) oxide film, silicon oxynitride film.

Furthermore, the term “silicon nitride”, “silicon nitride”, or “silicon nitride” includes not only Si ₃ N ₄ but also an insulating film having a similar composition of silicon nitride.

  The gate insulating film includes a silicon thermal oxide film, a silicon oxynitride film, other thermal oxide films, a deposited film, and a coating system film, and in terms of materials, a non-silicon metal oxide other than a silicon oxide film, Insulating nitride such as silicon nitride, or a composite film thereof is included.

  In addition, although the deposited film is amorphous at the beginning of deposition, it may become polycrystalline immediately after the subsequent heat treatment. It may be displayed in a later form. For example, polycrystalline silicon (polysilicon) may be in an amorphous state at the beginning of deposition and is changed to polycrystalline silicon by a subsequent heat treatment. However, it goes without saying that polycrystalline silicon can be used from the beginning. The amorphous state at the beginning of deposition has advantages such as prevention of channeling in ion implantation, avoidance of difficulty in workability depending on the shape of agglomerates during dry etching, and low sheet resistance after heat treatment.

It is sectional drawing which shows the structural example of the thin film semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the structural example of the liquid crystal display device by which the thin film semiconductor device which concerns on Embodiment 1 of this invention is mounted. It is a figure which shows the manufacturing method of the thin film semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the manufacturing method of the thin film semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the manufacturing method of the thin film semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the manufacturing method of the thin film semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the structural example of the thin film semiconductor device which concerns on Embodiment 2 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Thin-film semiconductor device, 11 ... Substrate, 12 ... 1st insulating layer (undercoat layer), 13 ... 1st conductive layer, 14 ... 2nd insulating layer, 15 ... Semiconductor layer, 16 ... Channel region, 17 ... Source region , 18 ... drain region, 19 ... gate insulating film, 20 ... interlayer insulating film, 21 ... gate electrode, 22 ... source electrode, 23 ... drain electrode, 24 ... bias electrode, 31 ... transparent electrode, 40 ... liquid crystal display device, 41 ... Pixel part, 42 ... Column driver, 43 ... Low driver

Claims (17)

A substrate made of resin or glass;
A semiconductor layer formed on the substrate;
A first semiconductor region formed in a surface region of the semiconductor layer;
A second semiconductor region formed in a surface region of the semiconductor layer;
A first electrode formed on the first semiconductor region;
A second electrode formed on the second semiconductor region;
A gate electrode disposed through a gate insulating film between the first semiconductor region and the second semiconductor region in the surface region of the semiconductor layer,
A thin film semiconductor device, further comprising: a conductive layer formed of a conductive material so as to face the semiconductor layer between the substrate and the semiconductor layer.   The thin film semiconductor device according to claim 1, wherein an insulating layer is formed between the substrate and the semiconductor layer.   The thin film according to claim 2, wherein the first semiconductor region and the second semiconductor region are formed so as to extend from a surface region of the semiconductor layer to an interface of the semiconductor layer on the substrate side. Semiconductor device. The semiconductor layer is formed on the substrate;
2. The semiconductor region according to claim 1, further comprising a semiconductor region formed at a lower resistance than the first semiconductor region and the second semiconductor region on a lower surface of the first semiconductor region and the second semiconductor region. The thin film semiconductor device described. The thin film semiconductor device is mounted on a liquid crystal display device,
5. The thin film semiconductor device according to claim 1, wherein the conductive layer is formed of the same material as a common electrode of a display portion of the liquid crystal display device.   The semiconductor layer is composed of a single layer made of one of silicon, germanium, a mixture thereof, and a carbide of these materials, or a thin film laminated film made of any of these materials. The thin film semiconductor device according to any one of 1 to 5.   The semiconductor layer is composed of a single layer of a so-called chalcogenide film such as an oxide, carbide, sulfide, selenium compound, tellurium compound or the like having semiconductor characteristics, or a thin film stack made of any of these materials. The thin film semiconductor device according to claim 1.   6. The thin film semiconductor device according to claim 1, wherein the semiconductor layer is a compound containing zinc as a main component.   The thin film semiconductor device according to claim 1, wherein the conductive layer is made of a conductive oxide.   The thin film semiconductor device according to claim 9, wherein the conductive oxide has translucency.   The thin film semiconductor device according to claim 9, wherein the conductive oxide is an oxide containing zinc as a main component.   The thin film semiconductor device according to claim 9, wherein the conductive oxide is an oxide containing indium and tin. A semiconductor layer forming step of forming a semiconductor layer on a substrate made of resin or glass;
A first semiconductor region forming step of forming a first semiconductor region in a surface region of the semiconductor layer;
A second semiconductor region forming step of forming a second semiconductor region in the surface region of the semiconductor layer;
A first electrode forming step of forming a first electrode on the first semiconductor region;
A second electrode forming step of forming a second electrode on the second semiconductor region;
A gate electrode forming step of forming a gate electrode disposed through a gate insulating film between the first semiconductor region and the second semiconductor region in the surface region of the semiconductor layer, and the substrate and the A method of manufacturing a thin film semiconductor device, further comprising a conductive layer forming step of forming a conductive layer formed of a conductive material so as to face the semiconductor layer between the semiconductor layer and the semiconductor layer.   The method of manufacturing a thin film semiconductor device according to claim 13, further comprising an insulating film forming step of forming an insulating layer between the substrate and the semiconductor layer. In the first semiconductor region forming step and the second semiconductor region forming step,
The thin film semiconductor device according to claim 14, wherein the first semiconductor region and the second semiconductor region are formed so as to extend from a surface region of the semiconductor layer to an interface of the semiconductor layer on the substrate side. Manufacturing method. The semiconductor layer is formed on the substrate;
In the first semiconductor region forming step and the second semiconductor region forming step, the lower surfaces of the first semiconductor region and the second semiconductor region are formed on the lower surface of the first semiconductor region and the second semiconductor region. 14. The method of manufacturing a thin film semiconductor device according to claim 13, wherein a semiconductor region having a high resistance is formed. The thin film semiconductor device is mounted on a liquid crystal display device,
17. The thin film semiconductor device according to claim 13, wherein the conductive layer forming step is performed in the same step as the step of forming the common electrode of the display unit of the liquid crystal display device. Production method.

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