JP2008112277A - Timing chart generation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing chart generation device for generating a timing chart by converting a content described in a property language into a timing chart as the other equivalent expression. <P>SOLUTION: This timing chart generation device for generating the content of property information acquired by describing the specifications of hardware in a specification description language as a timing chart is provided with a syntax information storage means for storing configuring unit information relating to configuring elements configuring the property information and temporal change information logically meant by the configuring unit information; a syntax analyzing means for analyzing the grammatical structure of the property information based on the configuring unit information, and for acquiring timing chart composition instruction information as a composition instruction for compounding the timing charts at each configuring unit information; and a timing chart compounding means for compounding the temporal change of the signal logically meant by the property information as a timing chart based on the timing chart composition instruction information. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a timing chart generation apparatus that can generate contents described in a property language by converting them into a timing chart that is another equivalent expression.

  In general, in the design process of a semiconductor integrated circuit, first, the entire semiconductor integrated circuit is regarded as a system, a behavior level description describing its operation is created, and then the created behavior level description is used as circuit design data. Convert to RT (Register Transfer) level description. Furthermore, the RT level description is automatically converted into a gate level description (gate level logic circuit; net list), layout design is performed based on the net list generated in this way, and then chip design is performed. Is called. In the design of the semiconductor integrated circuit as described above, design verification is performed to check the validity of the design made by the above steps. This design verification includes, for example, equivalence verification for verifying whether the conversion of each step is correct and specification verification for verifying whether each description correctly represents the design object.

  Conventionally, as an apparatus for performing this equivalence verification, for example, a logic circuit expressed by a hardware description in a functional level hardware description language and the same as the above expressed by a hardware description in a gate level hardware description language Individual parts obtained by dividing a logic circuit to determine whether to use logic verification by comparison of pool expressions or logic verification by comparison simulation using a test pattern to verify logic equivalence with the logic circuit A logic verification device or the like that is performed by separating each circuit has been proposed (see, for example, Patent Document 1).

JP-A-3-29868

  In recent years, by inputting properties that are specifications written in a specification description language (hereinafter referred to as property language) and design information written in a hardware description language into a verification tool, the logic equivalence between the two can be improved. It can be verified (hereinafter referred to as model check). Here, the property language refers to a dedicated language that describes hardware design specifications. In addition, by using such a verification tool, it is possible to expect hardware quality improvement by a third party check by directly reviewing the properties used in the verification during the design / verification review.

  However, there are multiple types of property languages, each with many ways of expression. At the present time, since the history of the property language is short, engineers who are familiar with the property language are insufficient. For this reason, even if a property writer intends to describe a property according to the design specification, it is difficult to determine whether the described property is really in accordance with the design specification, and a description error may occur in the property itself.

  In addition, there is a problem that the content of the property can be understood only by those who are familiar with the logical meaning of the property language, which has hindered understanding at the time of design / verification review. Further, the logic verification device described in Patent Document 1 is not related to the property language, and does not solve the above-described problems related to the property language.

  The present invention has been made in view of the above, and an object of the present invention is to provide a timing chart generation device that can convert and generate content described in a property language into a timing chart that is another equivalent expression. .

  In order to solve the above-described problems and achieve the object, a timing chart generation device according to the present invention is a timing chart generation device that generates the contents of property information in which hardware specifications are described in a specification description language as a timing chart. And the syntactic information storage means for storing the structural unit information related to the constituent elements constituting the property information and the time change information logically defined by the structural unit information, and the grammatical structure of the property information based on the structural unit information. Analyzing and synthesizing means for acquiring timing chart synthesis instruction information that is a synthesis instruction for synthesizing a timing chart for each unit of unit information, and property information logically means based on the timing chart synthesis instruction information Timing to synthesize time variation of signal as timing chart Characterized in that it comprises a chart combining means.

  According to the present invention, since the timing chart can be generated as a simpler equivalent expression by translating the meaning expressed by the complicated and difficult property, the person who is familiar with the logical meaning of the property language Even if it is not, there is an effect that the contents of the property can be easily understood. As a result, it is possible to easily determine whether or not a property that matches the design specification is described.

  Also, by checking the generated timing chart, it is possible to find and remove property description mistakes before executing model check, so it is possible to reduce the re-execution of model checks that are linked to property description mistakes. There is an effect. In addition, an easy-to-understand timing chart generation contributes to an engineer's property description education.

  Preferred embodiments of a timing chart generating device according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a schematic configuration of a timing chart generating apparatus 1 according to the first embodiment of the present invention. As shown in FIG. 1, the timing chart generation device 1 includes an input unit 10, a timing chart synthesis unit 20, a syntax analysis unit 30, a syntax database 40, and an output unit 50.

  The input unit 10 inputs property information A related to a property that is a property in which hardware specifications are described in a property language and is a conversion target in the timing chart generation device 1. When the property information A is directly described, the input unit 10 includes an input device such as a keyboard, a pointing device, and a mouse. When reading a file from the recording medium or communication medium as the property information A, the input unit 10 is configured by a file reading device. The input unit 10 outputs the input property information A to the timing chart synthesis unit 20.

  The timing chart synthesis unit 20 outputs the property information A received from the input unit 10 to the syntax analysis unit 30 as the property information A. Then, in accordance with the timing chart synthesis instruction information C output from the syntax analysis unit 30, the timing chart synthesis unit 20 generates one or more time changes of the signal logically meaning the property information from the property information A. The synthesized timing chart information is output to the output unit 50 as the timing chart information. That is, the timing chart synthesis unit 20 converts the time change of the signal logically indicated by the property information into a predetermined equivalent expression and outputs the converted equivalent expression.

  The syntax analysis unit 30 analyzes the grammatical structure of the property information A received from the timing chart synthesis unit 20, and constructs the timing chart synthesis instruction information C necessary for synthesis (equivalent conversion) from the property information A to the timing chart information. Generated for each unit information. The timing chart synthesis instruction information C is information used by the timing chart synthesis unit 20 when generating timing chart information.

  At this time, the syntax analysis unit 30 makes a query to the syntax database 40 by outputting the query information D to the syntax database 40 to the syntax database 40, and obtains property constituent unit information E described later from the syntax database 40. Then, the syntax analysis unit 30 analyzes the property information A while referring to the property structural unit information E. Then, the syntax analysis unit 30 outputs the created timing chart synthesis instruction information C to the timing chart synthesis unit 20.

  The syntax database 40 stores property constituent unit information E used when the syntax analysis unit 30 analyzes the syntax of the property information A. The property structural unit information E includes information on the grammatical structure of the property information A and syntax elements (keywords) constituting the property, time change information logically meanings the structural unit information, and each syntax element (keyword). Natural language information that is equivalent expression information of These property constituent unit information E is stored in advance in the syntax database 40 by the administrator or the user of the timing chart generating apparatus 1.

  FIG. 2 is a diagram illustrating an example of the property structural unit information E stored in the syntax database 40. In FIG. 2, as the property constituent unit information E, “keyword” that is a syntax element constituting the property and described in the property language, “classification” indicating the classification of the “keyword”, and equivalent to the “keyword” Each item of “natural language information” indicating natural language expression is shown. By using the property constituent unit information E, it is possible to convert the “keyword” described in the property language into a natural language expression equivalent to the “keyword”. For example, the keyword “X | => Y” can be converted to an equivalent natural language expression “Y after one cycle of X”. In addition, the keyword “a; b” can be converted to an equivalent natural language expression “b after one cycle after a”.

  The output unit 50 is means for presenting the timing chart information synthesized by the timing chart synthesis unit 20 to the user of the timing chart generation device 1, and visually displays the contents on a display device such as a graphic display. Or output in file format.

  Next, the operation of the timing chart generating apparatus 1 having such a configuration will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of correspondence between hardware specifications (property) in the timing chart generation device 1 and expression formats of the hardware specifications (property). In FIG. 3, if the signal α is High in the first cycle and the signal α falls (Low) in the second cycle, the signal β rises (becomes High) in the fifth cycle. No. (1) is described in “natural language”, No (2) is described in “property language”, No (3) is described in “timing chart (path waveform)”, No. (4) is described in “Timing chart (fail waveform)”.

  The “timing chart (path waveform)” indicated by No (3) in FIG. 3 is a timing chart (path waveform) having a time change of the signal logically coincident with the property information A, and is shown in FIG. The “timing chart (fail waveform)” shown in (4) is a timing chart (fail waveform) having a time change of a signal that does not logically match the property information A.

  First, the user of the timing chart generation device 1 inputs from the input unit 10 property information A regarding a property that is a hardware specification described in a property language and is a conversion target in the timing chart generation device 1. . For example, as the property information A, “If the signal α is High in the first cycle and the signal α reaches (Low) in the second cycle, the signal β rises (becomes High) in the fifth cycle”. It is assumed that the property information A in which the hardware specification (natural language) of the content is described in the property language is input.

  The property information A input from the input unit 10 is output to the timing chart synthesis unit 20. When receiving the property information A, the timing chart synthesis unit 20 outputs the property information A to the syntax analysis unit 30. Upon receiving the property information A, the syntax analysis unit 30 outputs query information D to the syntax database to the syntax database 40. The syntax database 40 outputs property constituent unit information E corresponding to the query information D to the syntax analysis unit 30.

  The syntax analysis unit 30 analyzes the grammatical structure of the property information A while referring to the property structural unit information E obtained from the syntax database 40, and the timing necessary for the synthesis (equivalent conversion) of the timing chart information from the property information A Chart synthesis instruction information C is generated. That is, the syntax analysis unit 30 divides the grammatical structure of the property information A from the left side based on the property structural unit information E, and “always”, “{α;! Α}”, “| =>”, A set of “{[* 2]; β}” is obtained.

  Then, the syntax analysis unit 30 further divides each of these and converts the syntax element into natural language information corresponding to each minimum unit when the minimum unit of the syntax element stored in the property constituent unit information E is reached. Thus, the converted natural language information is obtained as timing chart synthesis instruction information C.

  For example, when the syntax analysis unit 30 divides the property information A described as (2) in FIG. 3, the keyword “always” and the keyword “α” are used as the constituent elements of the minimum unit as shown in FIG. ”, Keyword“; ”, keyword“! Α ”, keyword“ | => ”, keyword“ [* 2] ”, keyword“; ”, and keyword“ β ”.

  At this point, the syntax analysis unit 30 sets the keyword “always” → natural language information ““ initialization ”(in the initial cycle)”, the keyword “α” → natural language information ““ α = 1 ”, as shown in FIG. Arrangement ”(first cycle)”, keyword “;” → natural language information “proceed to next cycle”, keyword “! Α” → natural language information ““ arrange α = 0 ”(second cycle)”, keyword “ | => ”→ natural language information“ “go to next cycle”, keyword “[* 2]” → natural language information ““ 1 is arranged for 2 cycles (no instructions for 2 cycles) ”(3rd to 4th cycles) ”, Keyword“; ”→ natural language information“ “go to next cycle”, keyword “β” → natural language information ““ place β = 1 ”(5th cycle)”. Thereby, the syntax analysis unit 30 obtains the converted natural language information as timing chart synthesis instruction information C.

  The syntax analysis unit 30 then outputs the timing chart synthesis instruction information C to the timing chart synthesis unit 20 in order from the left side of the constituent elements of the divided property information A. When receiving the timing chart synthesis instruction information C, the timing chart synthesis unit 20 synthesizes one or more timing chart information of a predetermined equivalent expression from the property information A based on the timing chart synthesis instruction information C.

  FIG. 4 shows the timing chart synthesis instruction information C received by the timing chart synthesis unit 20 from the syntax analysis unit 30 in the order received. The timing chart synthesizing unit 20 executes the received timing chart synthesis instruction information C in order (positions signals at appropriate times in the timing chart), whereby the timing as shown in No (3) in FIG. Timing chart information F corresponding to the chart (path waveform) is obtained.

  Then, the timing chart combining unit 20 outputs the combined timing chart information F to the output unit 50. Based on the timing chart information F, the output unit 50 visually displays the timing chart on a graphic display, for example. Thereby, the user of the timing chart generation device 1 can easily understand the contents represented by the property from the timing chart.

  According to the timing chart generating apparatus 1 according to the first embodiment described above, a timing chart is generated by using property information in which hardware specifications are described in a property language as a simpler equivalent expression. That is, the meaning represented by the property is translated to generate a timing chart as a simpler equivalent expression. As a result, even those who are not familiar with the logical meaning of the property language can easily understand the contents of the property using the generated timing chart, and the properties that match the design specifications are described. It can be easily determined whether or not there is.

  Also, by checking the generated timing chart, it is possible to find and remove property description mistakes before executing the model check. Therefore, it is possible to reduce the re-execution of the model check associated with the property description mistake. Furthermore, the generation of an easy-to-understand timing chart has the merit that it contributes to property description education for engineers.

Embodiment 2. FIG.
In the first embodiment, a case has been described in which a timing chart (path waveform) (see (3) in FIG. 3) having a time change of a signal logically coincident with the property information A is synthesized. It is also possible to synthesize a timing chart (fail waveform) (see (4) in FIG. 3) having a time change of a signal that does not logically match the property information A.

  For example, a timing chart (path waveform) having a time change of a signal that logically matches property information is generated, or a timing chart (fail waveform) having a time change of a signal that does not logically match property information is generated. This can be realized by using the timing chart generation setting information B that can be set. The timing chart generation setting information B is input from the input unit 10 to the timing chart synthesis unit 20 as shown in FIG.

  Then, in accordance with the timing chart generation setting information B, the timing chart synthesis unit 20 has a timing chart (path waveform) having a time change of a signal that logically matches the property information, or a signal that does not logically match the property information. This can be realized by selecting any one of the timing charts (fail waveforms) having time changes and synthesizing the timing charts.

  As described above, in the first embodiment, a method for generating a path waveform has been described. On the other hand, when the timing chart generating unit 20 sets the timing chart generation setting information B so as to generate a fail waveform, the timing chart combining unit 20 includes the keyword “| => in the received timing chart combining instruction information C. Invert one or more logics of the timing chart synthesis instruction information C received thereafter.

  FIG. 5 shows timing chart synthesis instruction information C received from the syntax analysis unit 30 when the timing chart synthesis unit 20 synthesizes a timing chart (fail waveform) having a time change of a signal that does not logically match the property information A. It is shown. FIG. 5 is obtained by inverting the logic of the synthesis instruction information (8) in the timing chart synthesis instruction information C shown in FIG.

  By synthesizing the timing chart based on the timing chart synthesis instruction information C shown in FIG. 5, the timing chart (fail waveform) shown as No (4) in FIG. 3 can be synthesized.

  According to the timing chart generating apparatus according to the second embodiment described above, it is possible to generate timing charts of a plurality of different formats from property information in which hardware specifications are described in a property language. That is, when the meaning represented by the property is translated and the timing chart is generated as a simpler equivalent expression, the meaning represented by the property can be represented in the timing chart in a different display format.

  As a result, even if you are not familiar with the logical meaning of the property language, you can generate a timing chart in a format that is convenient for understanding depending on conditions such as the property contents. It becomes possible to easily understand the contents of the property, and it is possible to easily determine whether or not a property matching the design specification is described.

Embodiment 3 FIG.
In the above, the method of converting from a keyword to corresponding natural language information when obtaining as timing chart synthesis instruction information C has been described. However, depending on the keyword, a plurality of conversion candidates can be selected when converting to natural language information. It may be possible. For example, in the case of the keyword “a | b” shown in FIG. 2, there are three conversion candidates “simultaneous establishment of a and b”, “establishment of only a”, and “establishment of only b”.

  In this case, it is possible to select the natural language information to be converted from these three and obtain the timing chart synthesis instruction information. Further, timing chart synthesis instruction information C can be obtained for all three. For example, in the timing chart generation setting information B described above, a plurality of selectable conversion candidates are sequentially selected and converted to natural language information by setting a plurality of waveform setting switches for setting a plurality of waveform generations to “ON”. Thus, the timing chart synthesis instruction information C can be obtained. That is, it is possible to generate timing charts of a plurality of path waveforms by repeatedly performing conversion from keywords to natural language information for only one of a plurality of selectable conversion candidates.

  According to the timing chart generating apparatus according to the third embodiment described above, it is possible to generate timing charts of a plurality of different formats from property information in which hardware specifications are described in a property language. That is, when translating the meaning represented by the property and generating a timing chart as a simpler equivalent expression, if there are multiple types of meaning candidates represented by the property, the timing chart corresponding to each meaning Can be generated. As a result, even if you are not familiar with the logical meaning of the property language, you can easily understand the contents of the property using the generated timing chart, and the properties that match the design specifications are described. It can be easily determined whether or not there is.

  As described above, the timing chart generation device according to the present invention is useful for understanding and judging the property contents, and in particular, those who are not familiar with the logical meaning of the property language understand the property contents. Suitable for you.

It is a block diagram which shows schematic structure of the timing chart production | generation apparatus concerning Embodiment 1 of this invention. It is a figure which shows an example of the property structural unit information E stored in a syntax database. It is a figure which shows an example of a response | compatibility with the hardware specification (property) in the timing chart production | generation apparatus concerning Embodiment 1 of this invention, and the expression format of this hardware specification (property). It is a figure for demonstrating conversion from a keyword to the timing chart synthetic | combination instruction | indication information C in the case of producing | generating the timing chart of a path waveform. It is a figure for demonstrating conversion from the keyword to the timing chart synthetic | combination instruction | indication information C in the case of producing | generating the timing chart of a fail waveform.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Timing chart production | generation apparatus 10 Input part 20 Timing chart synthetic | combination part 30 Syntax analysis part 40 Syntax database 50 Output part A Property information B Timing chart production | generation setting information C Timing chart synthetic | combination instruction information D Query information E Property structural unit information F Timing chart information

Claims (5)

A timing chart generating device that generates the contents of property information describing a hardware specification in a specification description language as a timing chart,
Syntax information storage means for storing structural unit information related to the structural elements constituting the property information and time change information logically meaning the structural unit information;
Syntactic analysis means for analyzing the grammatical structure of the property information based on the structural unit information and obtaining timing chart synthesis instruction information which is a synthesis instruction for synthesizing the timing chart for each structural unit information; ,
Based on the timing chart synthesis instruction information, timing chart synthesis means for synthesizing a time change of a signal logically meaning by the property information as a timing chart;
A timing chart generating device comprising: The timing chart generating device according to claim 1, wherein the timing chart synthesizing unit synthesizes a timing chart having a time change of a signal logically coincident with the property information. The timing chart generating device according to claim 1, wherein the timing chart synthesizing unit synthesizes a timing chart having a time change of a signal that does not logically match the property information. The timing chart synthesizing unit selects whether to synthesize a timing chart having a time change of a signal logically coincident with the property information or a timing chart having a time change of a signal not logically coincident with the property information. The timing chart generating device according to claim 1, wherein the timing chart generating device is possible. The timing chart synthesis means synthesizes the timing chart corresponding to each of the plurality of timing chart synthesis instruction information when there are a plurality of the timing chart synthesis instruction information corresponding to the property information. The timing chart production | generation apparatus as described in any one of Claims 1-4.

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