JP2008107872A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of checking the operation of an inside of a verification target circuit in respective abstraction level designing steps from an RT level up to a final ASIC. <P>SOLUTION: A system LSI 10 having a state machine 11 and a combination circuit 12 for executing predetermined logical processing according to an input signal IN and outputting an output signal OUT is provided with a function verification circuit 20 for detecting abnormality in a state of a signal line 13. The function verification circuit 20 is described by a hardware description function allowed to be converted into hardware and composed as a logical circuit and is provided with: a state history storage part 21 for storing the history of states of the inner signal line 13; a transition check signal generation part 22 for generating a signal to be output to the signal line 13 on the basis of the state history stored in the state history storage part 21; a comparison part 23 for comparing the signal generated by the transition check signal generation part 22 with a signal output to the signal line 13; and an output part 24 for outputting a comparison result. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having an operation monitoring function for monitoring an internal operation state and outputting an abnormal state.

CPU (Central Processing Unit) due to demands for miniaturization, weight reduction, power saving and cost reduction
The use of system LSIs in which a memory, various logic circuits, input / output interfaces, and the like are provided on a single chip has become widespread.

  The system LSI design uses the function block data for realizing various functions that have been developed so far, and creates new function blocks necessary for configuring the target system. A technique of configuring an LSI having a desired function by combining functional blocks is used.

  In such a design method, first, an operation model in which the functional content of each functional block is described at an algorithm level is used, and system verification is performed by simulation at a logical operation level. Next, using a model at RT (Register Transfer) level in which the functional content of each functional block is described by the operation of signals between and within the functional blocks, functional verification is performed by simulation at the RT level. At this RT level, since the actual operation delay of the parts is not included, the operation timing cannot be confirmed. Furthermore, a simulation is performed at a signal level using a net list of each functional block (a component such as a transistor as a component and a connection relation between the components), and operation timing in consideration of operation delay is verified. After that, a hardware emulator based on FPGA (Field Programmable Gate Array) is created based on the netlist, and a function confirmation test is performed by hardware. Furthermore, ASIC (Application Specified Integrated Circuit: specific system LSI) which is the final system LSI Dedicated standard IC) for function confirmation and performance test. In this way, from the algorithm level with a high level of abstraction to the final ASIC with progressively lower levels of abstraction, verification corresponding to each is performed at the design stage of each level of abstraction, and an ASIC with complete functions is completed. .

  In functional verification by RT-level simulation, as a mechanism for confirming the operation of the verification target circuit, a software model called “assertion” that automatically detects and notifies an abnormality is used for the verification target circuit described at the RT level. Incorporation in a model or in a simulation program (simulator) is performed.

  The assertion is a description of a state or operation permitted by the functional specification of the circuit to be verified using a verification-dedicated language or a hardware description language. By incorporating assertions, the state and operation of the verification target circuit are monitored during simulation execution, and if this verification target circuit falls outside the range allowed by the functional specifications, it is automatically performed without human intervention. Information about the occurrence of the abnormality can be output to a display device or a log file. The feature of the assertion is that not only the interface of the verification target circuit but also the state and operation inside the verification target circuit can be easily checked.

  By applying this assertion, it is not only necessary to visually check the signal waveform of the simulation result, but also the state inside the verification target circuit can be checked during the simulation execution, so that the location where the problem has occurred can be identified. It becomes easy. Furthermore, since it is not necessary to create an expected operation value for each function verification test program, it is possible to reduce human error and verification man-hours.

FIG. 2 is a diagram illustrating an example of a simulation environment using a conventional assertion.
In this simulation, the verification target circuit model 1 described at the RT level and the verification model 2 that gives the input signal IN to the verification target circuit and receives the output signal OUT from the verification target circuit to control the next input signal IN. Is used. In this simulation, an assertion 3 for monitoring an input / output signal between the verification target circuit model 1 and the verification model 2 and an assertion 4 for monitoring a signal in the verification target circuit model 1 from the outside of the circuit are used. Furthermore, an assertion 1a for monitoring a signal inside the circuit is incorporated in the circuit model 1 to be verified.

  When a simulation is performed using such a model, the output signal OUT from the verification target circuit model 1 is checked by the assertion 3, and the signal inside the verification target circuit model 1 is checked by the assertion 4 and the assertion 1a. If the signal checked by the assertions 3, 4, 1a is out of the range allowed in advance by the functional specification, it is detected as an abnormality by these assertions. The assertions 3, 4, 1a that have detected the abnormality output information on the occurrence of the abnormality to a display device or a log file (not shown).

JP 2001-101247 A JP 2006-163559 A

  In the RT-level simulation, verification is performed using assertions described in a hardware verification language such as SVA (System Verilog Assertion) of synopsys or PSL (Property Specification Language) of Accellera. Since such a hardware verification language is not a hardware description language such as HDL (Hardware Description Language), an assertion model described in this hardware verification language cannot be converted into a logic circuit. For this reason, there were the following problems.

  That is, when the functional verification by simulation at the RT level is completed and the next netlist simulation is performed, the verification target circuit model 1 is converted into a logic circuit. The incorporated assertion 1a is not subject to logic synthesis and cannot be synthesized as hardware. For this reason, when performing a simulation using a netlist, it becomes impossible to automatically monitor the signal inside the circuit model to be verified, which was possible in the simulation at the RT level. Therefore, in the simulation using the net list, it is necessary to visually check the signal waveform of the simulation result. Furthermore, in the simulation by hardware such as FPGA and ASIC, it is necessary to judge whether the function is normal or abnormal based only on the signal of the output terminal of the circuit to be verified. There was a problem of difficulty.

  In addition, since the hardware verification dedicated language is provided by the above companies with different specifications, it is necessary to use a simulator corresponding to the language. For this reason, there is an inconvenience that an assertion created for a certain simulator cannot be used for another simulator.

  An object of the present invention is to provide a semiconductor integrated circuit capable of checking the internal operation of a circuit to be verified at the design stage of each abstraction level from the RT level to the final ASIC.

  The present invention relates to a semiconductor integrated circuit having a combinational circuit that performs a predetermined logic process according to an input signal and outputs an output signal, to detect an abnormality in the state and change of the internal signal during the logic process in the combinational circuit. In addition, a function verification circuit described in a hardware description language whose function can be converted into hardware and synthesized as a logic circuit is provided.

  In the present invention, a semiconductor integrated circuit is described in a hardware description language that can be converted into hardware in addition to a combinational circuit that performs a predetermined logic process in accordance with an input signal and outputs an output signal. As shown in FIG. As a result, the internal operation of the combinational circuit that is the verification target circuit can be checked. Moreover, this function verification circuit is described in a hardware description language that can be converted into hardware. Therefore, if it is described as a model at the RT level design stage, it can be simulated with a general simulator, but it can also be converted into a hardware emulator using FPGA, or into an actual system LSI using ASIC. Sometimes it can be converted directly into hardware. Therefore, there is an effect that the internal operation of the circuit to be verified can be checked at the design stage of each abstraction level from the RT level to the final ASIC.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a diagram illustrating a test environment of a system LSI according to the first embodiment of the present invention.
This system LSI 10 is used to monitor the state of a plurality of signal lines 13 between the state machine 11 and the combinational circuit 12 in addition to the state machine 11 and the combinational circuit 12 that perform the original logical processing to be verified. A function verification circuit 20 is provided.

  The function verification circuit 20 includes a state history holding unit 21 for holding a past state of the signal line 13 and a history of changes thereof. The state history holding unit 21 is composed of, for example, a plurality of shift registers provided for each signal line 13, and shifts and holds the state of each signal line 13 with a clock signal common to the clock signal CLK supplied to the state machine 11. To do. The number of stages of each shift register is set to the number of stages that can hold the past state of the signal line 13 within a range that affects the current state of the signal line 13. A transition check signal generation unit 22 is connected to the state history holding unit 21.

  The transition check signal generation unit 22 is a sequential circuit that generates a signal to be output to the signal line 13 based on the past state of the signal line 13 held in the state history holding unit 21. A comparison unit 23 is connected to the output side of the transition check signal generation unit 22.

  The comparison unit 23 compares the expected signal generated by the transition check signal generation unit 22 with the signal actually output to each signal line 13. The comparison result by the comparison unit 23 is given to the output unit 24. The output unit 24 encodes the combination of the comparison result signals and outputs the encoded combination to the abnormality notification terminal 25.

  The function verification circuit 20 including the state history holding unit 21, the transition check signal generation unit 22, the comparison unit 23, the output unit 24, and the terminal 25 is the state machine 11 and the combinational circuit 12 from the initial design at the RT level. Are described in the same hardware description language such as HDL, and are converted into hardware simultaneously with the state machine 11 and the combinational circuit 12 and synthesized as a logic circuit.

  The system LSI 10 is connected to a test apparatus 30 corresponding to the verification model 2 shown in FIG. The test apparatus 30 provides the system LSI 10 with a clock signal CLK as an operation reference, provides an input signal IN to the state machine 11 and the combinational circuit 12 that are verification target circuits, and receives an output signal OUT from the verification target circuit. To control the next input signal IN. Further, the test apparatus 30 decodes the encoded abnormality occurrence notification signal output from the terminal 25 of the system LSI 10 and outputs a verification model 31 that outputs what abnormality is detected in the system LSI 10. A database 32 that holds in advance the relationship between the abnormality occurrence notification signal and the failure location and cause in the circuit to be verified, a display device 33 that displays the detected abnormal state, and a log file 34 that records information on the abnormal state I have.

Next, a function verification operation of the system LSI 10 in the test environment of FIG. 1 will be described.
(1) The input signal IN is supplied from the test apparatus 30 to the system LSI 10 in synchronization with the clock signal CLK.

(2) The state machine 11 and the combinational circuit 12 of the system LSI 10 perform a logical operation based on the input signal IN given from the test apparatus 30 and output the result of the logical operation to the test apparatus 30 as an output signal OUT.

(3) On the other hand, the function verification circuit 20 in the system LSI 10 holds the state of the signal line 13 in the state history holding unit 21 in accordance with the clock signal CLK.

(4) The transition check signal generation unit 22 generates a signal to be output to the signal line 13 based on the past state of the signal line 13 held in the state history holding unit 21.

(5) The comparison unit 23 compares the signal generated by the transition check signal generation unit 22 with the signal actually output to each signal line 13, and when they match, the logical value is “0”, and when they do not match Outputs a logical value “1” corresponding to each signal line 13.

(6) The output unit 24 encodes the combination of the comparison result signals output from the comparison unit 23 and outputs the result to the abnormality occurrence notification terminal 25. Therefore, when the state of at least one signal line 13 among the plurality of signal lines 13 is not an expected state, the value output from the terminal 25 is an abnormality occurrence notification signal other than zero.

(7) The verification model 31 of the test apparatus 30 decodes the abnormality occurrence notification signal output from the terminal 25 of the system LSI 10, refers to the database 32, and what abnormality is detected in the system LSI 10 The information of is output.

(8) The information output from the verification model 31 is output to the display device 33 and further recorded in the log file 34 for later analysis.

(9) If no abnormality notification signal is detected from the system LSI 10, the test apparatus 30 generates the input signal IN to be given next based on the output signal OUT output from the system LSI 10.

(10) Thereafter, returning to (1), the operations of (1) to (9) are repeated until the test input signal IN prepared in advance is completed.

  As described above, the system LSI 10 according to the first embodiment includes a plurality of signals to be verified between the state machine 11 and the combinational circuit 12 in addition to the state machine 11 and the combinational circuit 12 that perform the original logical processing. A function verification circuit 20 for monitoring the state of the line 13 is provided. Thereby, the internal operation of the verification target circuit can be checked.

  Further, the function verification circuit 20 is described in the hardware description language such as HDL, which is the same as that of the state machine 11 and the combinational circuit 12, from the beginning of the design at the RT level, and as a logic circuit simultaneously with the state machine 11 and the combinational circuit 12 It is synthesized. Therefore, in the simulation at the RT level, the simulation can be performed using a general simulator without being restricted by the simulator. Also in the conversion to the logic circuit by the net list, the net list of the function verification circuit 20 is generated simultaneously with the state machine 11 and the combinational circuit 12. Thereby, it is possible to check the internal operation of the circuit to be verified even in the simulation using the netlist.

  Therefore, the system LSI 10 has an advantage that the internal operation of the circuit to be verified can be checked at each design stage with different abstraction levels in the LSI design from the RT level to the final ASIC.

FIG. 3 is a configuration diagram of a system LSI showing a second embodiment of the present invention.
This system LSI 10A is provided with a function verification circuit 20A having a slightly different function and configuration in place of the function verification circuit 20 in the system LSI 10 in FIG. That is, the function verification circuit 20A is a circuit in which a circuit (holding unit) for holding the output signals S23a to S23n of the comparison unit 23 is inserted between the comparison unit 23 and the output unit 24 when an abnormality occurs.

  The output signals S23a to S23n of the comparison unit 23 are supplied to first input sides of AND gates (hereinafter referred to as "AND") 26a to 26n, respectively. The output sides of the ANDs 26a to 26n are connected to first input sides of OR gates 27a to 27n, respectively, and the output sides of these ORs 27a to 27n have reset functions (however, reset The terminals are connected to data input terminals of flip-flops (hereinafter referred to as “FF”) 28a to 28n (not shown). The output terminals of the FFs 28a to 28n are connected to the output unit 24 and to the second input sides of the ORs 27a to 27n, respectively.

  Further, the output terminals of the FFs 28a to 28n are connected to the input side of a negative OR gate (hereinafter referred to as “NOR”) 29, and the output side of the NOR 29 is connected in common to the second input side of the ANDs 26a to 26n. Has been.

  This system LSI is tested in a test environment using a test apparatus 30 similar to that shown in FIG. In the function verification circuit 20A, the state of the signal line 13 between the state machine 11 and the combinational circuit 12 is held in the state history holding unit 21 according to the clock signal CLK. The transition check signal generation unit 22 generates a signal to be output to the signal line 13 based on the past state of the signal line 13 held in the state history holding unit 21.

  The comparison unit 23 compares the signal generated by the transition check signal generation unit 22 with the signal actually output to each signal line 13, and is “0” when they match, and “1” when they do not match. The signal is output as output signals S23a to S23n corresponding to each signal line 13.

  In the initial state, since the FFs 28a to S28n are reset, the output signal of the NOR 29 is “1”. Accordingly, the output signals S23a to S23n of the comparison unit 23 are given to the input side of the FFs 28a to S28n via the ANDs 26a to 26n and ORs 27a to 27n, respectively, and are held in synchronization with the clock signal CLK. If no abnormality occurs, the output signals S23a to S23n are all "0", so the contents held in the FFs 28a to S28n are "0" and do not change.

  Here, it is assumed that an abnormality has occurred and, for example, the output signal S23a becomes “1”. As a result, “1” is held in the FF 28a at the timing of the next clock signal CLK, and the output signal of the NOR 29 changes to “0”. When the output signal of the NOR 29 becomes “0”, the output signals of the ANDs 26a to 26n all become “0” regardless of the output signals S23a to S23n. Further, the signals of the respective output terminals are fed back to the data input terminals of the FFs 28a to 28n via the ORs 27a to 27n. Accordingly, the values of the output signals S23a to S23n at the time when the output signal S23a becomes “1” are held in the FFs 28a to 28n and supplied to the output unit 24, respectively. This state is continued until a reset signal is given from the test apparatus side, for example.

  As described above, the system LSI 10A according to the second embodiment includes a circuit for holding the output signals S23a to S23n when an abnormality is detected by the comparison unit 23 until a reset signal is given. In addition to the same advantages as 1, the function on the test apparatus side can be simplified. That is, the occurrence of an abnormal operation and the cause thereof are confirmed only by using a simple device such as an LED (light emitting diode) instead of the verification model 31, the display device 32, and the log file 33 in the test apparatus 30 in FIG. can do.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) The verification target circuit of the system LSI is not limited to the state machine 11 and the combinational circuit 12, and any logic circuit is applicable. The internal signal to be verified may be singular or plural.
(B) The language for describing the function verification circuits 20 and 20A at the design stage of the system LSI is not limited to HDL. If the functional verification circuit is described using the same description language for the state machine or combinational circuit that performs the original logic processing as the verification target, it can be performed consistently from RT level simulation to hardware design. As a result, design man-hours can be reduced.
(C) In FIG. 3, the circuit configuration for holding the output signals S23 to S23n of the comparison unit 23 is an example, so long as the output signals S23 to S23n when the abnormal state is detected can be held as they are. Any circuit configuration may be used.
(D) The output unit 24 is configured to encode and output the output signals S23a to S23n of the comparison unit 23 to the terminal 25 in order to suppress an increase in the number of pins of the system LSI. If there is no problem, encoding is not necessary.

It is a figure which shows the test environment of the system LSI of Example 1 of this invention. It is a figure which shows an example of the simulation environment using the conventional assertion. It is a block diagram of the system LSI which shows Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 State machine 12 Combination circuit 13 Signal line 20, 20A Function verification circuit 21 State history holding part 22 Transition check signal generation part 23 Comparison part 24 Output part 25 Terminal 26 AND
27 OR
28 FF
29 NOR

Claims (4)

  In a semiconductor integrated circuit having a combinational circuit that performs a predetermined logic process according to an input signal and outputs an output signal, the function of detecting an abnormality in the state and change of the internal signal during the logic process in the combinational circuit A semiconductor integrated circuit comprising a function verification circuit described in a hardware description language that can be converted into hardware and synthesized as a logic circuit. The function verification circuit includes:
A state history holding unit for holding a history of the state of the internal signal;
A transition check signal generation unit that generates an internal signal to be output from the combinational circuit based on the state of the internal signal held in the state history holding unit;
A comparison unit that compares the internal signal to be output generated by the transition check signal generation unit with the internal signal actually output from the combinational circuit;
An output unit for outputting a comparison result in the comparison unit;
The semiconductor integrated circuit according to claim 1, further comprising:   A holding unit is provided that holds a comparison result in the comparison unit and supplies the comparison result to the output unit when the comparison unit detects an abnormality in the state or change of the internal signal during logic processing in the combinational circuit. The semiconductor integrated circuit according to claim 2.   4. The semiconductor integrated circuit according to claim 2, wherein the output unit encodes and outputs the comparison result.

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