JP2008103737A - Insulated gate semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a minute insulated gate semiconductor device of a short channel length while suppressing a short channel effect. <P>SOLUTION: The insulated gate semiconductor device has an N channel FET and a P channel FET isolated by a field oxide film wherein each FET has a source region, a drain region, a channel forming region, a gate electrode composed of polysilicon, a sidewall composed of a silicon nitride, a gate insulating film composed of a thermal oxidation film, a first silicide having one end aligned with the field oxide film and the other end aligned with the sidewall, and a second silicide having an end aligned with the sidewall wherein the channel forming region has such a region as a depletion region spreading from the drain region side to the channel forming region is restrained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The invention disclosed in this specification includes an insulating gate type semiconductor device having an SOI (Silicon-On-Insulator) structure, in particular, an insulating gate type field effect transistor (hereinafter simply referred to as IG-FET) and a manufacturing method thereof. About. Examples of the insulated gate semiconductor device having an SOI structure include a semiconductor device formed on an SOS (Silicon-On-Sapphire) substrate, a SIMOX (Separation-by-Implanted Oxygen) substrate, and the like.

  In particular, this technique is effective when a fine element having a channel length of 0.35 μm or less (particularly 0.1 μm or less) is manufactured. Therefore, the present invention can be applied to various semiconductor integrated circuits such as IC, VLSI, and ULSI configured by integrating IG-FETs.

  In this specification, the term “semiconductor device” means “a device that is used by using a semiconductor”, not to mention a semiconductor element such as an IG-FET, but also to integrate a semiconductor element. The integrated circuit, and even electronic equipment incorporating the integrated circuit are included in the category of “semiconductor device”. Note that in this specification, for convenience of explanation, terms such as a semiconductor element, an integrated circuit, and an electronic device are properly used as necessary.

  In recent years, integrated circuits such as VLSI have been increasingly miniaturized, and processing dimensions in the deep sub-micron region such as wiring widths of 0.35 to 0.1 μm or less and further 0.01 μm or less have been required. It is coming.

  At the same time, low power consumption is required, and the low power consumption characteristics of CMOS ICs are becoming indispensable configurations. When such a CMOS IC is miniaturized, a latch-up phenomenon that occurs between an N-type FET and a P-type FET becomes a problem, but an SOI-structured IG-FET solves this problem.

  Further, since the substrate and the element are completely insulated, the parasitic capacitance generated there can be greatly reduced, and high-speed operability can be pursued.

  As described above, a semiconductor device having an SOI structure is attracting a great deal of attention as a next-generation high-speed element, and is expected to increase in demand in the future.

  Such miniaturization of semiconductor elements has been advanced in accordance with a scaling law, and it has been generally known that miniaturization leads to improved characteristics of integrated circuits. However, when microfabrication is performed in the sub-micron region, a problem that simply does not follow the scaling law occurs.

  As such a problem, a phenomenon called a short channel effect is typically known. The short channel effect means that as the line width of the gate electrode becomes shorter, that is, as the channel formation region becomes shorter, the charge of the channel formation region is not limited to the gate voltage but also the depletion layer charge of the source / drain region, the electric field and the potential distribution. It is a phenomenon that is caused to become greatly affected.

  This state is simplified and shown in FIG. FIG. 3 shows a conventional semiconductor device formed on a SIMOX substrate, in which 301 is a silicon substrate and 302 is a buried oxide film layer formed by oxygen implantation. A crystalline semiconductor (single crystal silicon layer) is disposed on the buried oxide film layer 302, and a source region 303, a drain region 304, a channel region 305, and a gate electrode 306 are formed using the crystalline semiconductor. A dotted line indicated by 308 represents a depletion layer formed when the drain voltage Vd is small.

  Usually, the current flowing through the channel region 305 is controlled only by the gate voltage Vg. In this case, as indicated by 308, the depletion layer near the channel region 305 is substantially parallel to the channel, and a uniform electric field is formed.

  However, when the drain voltage Vd increases, the depletion layer in the vicinity of the drain region 304 spreads toward the channel region 305 and the source region 303, and the charge and electric field of the drain depletion layer are reduced as indicated by the solid lines indicated by 309. The depletion layer near the source region 303 and the channel region 305 is affected. That is, the on-current changes due to a complicated electric field distribution, which makes it difficult to control only with the gate voltage Vg.

  Here, the energy state around the channel formation region when the short channel effect occurs will be described with reference to FIG. 4 is an energy band diagram of the source region 401, the channel formation region 402, and the drain region 403 when the drain voltage is 0V.

  When a sufficiently large drain voltage Vd is applied in this state, the state changes to a state shown by a dotted line in FIG. That is, the depletion layer charge or electric field of the drain region 403 formed by the drain voltage Vd affects the depletion layer charge of the source and channel regions 401 and 402, and the energy (potential) state changes from the source region 401 to the drain region 403. It will change continuously.

  As the influence of such a short channel effect on a semiconductor element, for example, an IG-FET, phenomena such as a decrease in threshold voltage (Vth) and a decrease in device breakdown voltage due to punch-through are well known. It is also known that when the influence of the gate voltage on the drain current is reduced due to the punch-through phenomenon, the subthreshold characteristic is deteriorated.

  First, the decrease in threshold voltage is a phenomenon that can be seen in the same way for both N-channel and P-channel FETs. The degree of this reduction depends not only on the drain voltage but also on various parameters such as substrate impurity concentration, source / drain diffusion layer depth, gate oxide thickness, and substrate bias.

  Although lowering the threshold voltage is desirable in terms of reducing power consumption, generally, there is a problem in that frequency characteristics do not increase due to a decrease in driving voltage of an integrated circuit.

  Further, when the channel length is shortened, a state where the drain side depletion layer is connected to the source side depletion layer is formed to lower the diffusion potential in the vicinity of the source, so that a current flows between the source and drain even if the channel is not formed. become. This is a phenomenon called punch-through.

  When the punch-through phenomenon occurs, the drain current does not saturate even in the saturation region, so that a large current flows as the drain voltage increases, and the device breakdown voltage between the source and drain is greatly reduced. .

  Further, the deterioration of the subthreshold characteristic due to the punch-through phenomenon means that the subthreshold coefficient (S value) is increased, that is, the switching characteristic of the FET is deteriorated. Here, the influence of the short channel effect on the subthreshold characteristic is shown in FIG.

  FIG. 5 is a graph in which the horizontal axis represents the gate voltage Vg and the vertical axis represents the logarithm of the drain current Id, and the reciprocal of the slope (subthreshold characteristic) in the region 501 is the S value. FIG. 5 compares changes in characteristics when the channel length is gradually shortened, and the channel length decreases in the direction of the arrow.

  As a result, it can be confirmed that the slope of the characteristic decreases as the channel length decreases, that is, the S value tends to increase. This means that the switching characteristics of the FET deteriorate as the channel length becomes shorter.

  Various techniques have been proposed as means for suppressing the short channel effect as described above. For example, in a SOI structure in which a substrate and an element are insulated with a buried oxide film (such as those using bonding technology or ion implantation technology), reducing the thickness of the buried oxide film can suppress the short channel effect. It has been reported to be effective. However, this alone did not reach a sufficient resolution.

  In addition, an SOI structure semiconductor device with an extremely short channel length of about 0.1 μm has a characteristic that the existence probability of an impurity element in the channel region is extremely small (one to several), and the electron transfer speed even at room temperature. Has been confirmed to be faster than usual (speed overshoot effect). (K. Ohuchi et al., Jpn. J. Appl. Phys. 35, 960 (1996)).

  Furthermore, a high-speed semiconductor device that has improved its high-speed operability by utilizing the effect has been announced. However, in such a high-speed semiconductor device, various problems such as the punch-through phenomenon due to the short channel effect and the accompanying breakdown voltage degradation have not been solved.

  In addition, as a means for suppressing a decrease in threshold voltage due to the short channel effect, an impurity element that uniformly imparts one conductivity is added to the entire channel formation region, and the threshold voltage is determined by the addition amount. The method of controlling has been taken. However, in this method, since the added impurity causes the carrier to be scattered, there is a problem that the mobility of the carrier is lowered.

  In addition, as a method for manufacturing a single crystal silicon substrate which becomes a mother substrate of an SOI substrate, an FZ method having an extremely low oxygen content and a CZ method containing a certain amount of oxygen for stress relaxation and warpage prevention are formed. There is something. Usually, a single crystal silicon substrate by a CZ method is used for a memory IC or a logic IC.

However, the single crystal silicon substrate formed by the CZ method has a feature that the warpage amount due to thermal history increases as the oxygen content decreases, and conversely, the oxygen content is increased to a level at which the warpage amount can be sufficiently reduced ( Usually, about 1 to 2 × 10 ¹⁸ atoms / cm ³ ), oxygen atoms may interfere with carrier movement.

  In the current semiconductor industry, semiconductor integrated circuits integrated to the limit are required, and the key is how far down to the miniaturization of individual semiconductor elements can be pursued. However, even if a technique for forming a fine pattern in the deep sub-micron region has been developed, the problem of the short channel effect as described above has been a fatal obstacle that prevents miniaturization of the element.

  The present invention has been made in view of the above problems, and discloses a technique for effectively suppressing the short channel effect accompanying the miniaturization of a semiconductor element. It is another object of the present invention to make it possible to form a fine element in a deep submicron region that has been difficult to realize due to the short channel effect.

The configuration of the invention disclosed in this specification is as follows.
A source region, a drain region and a channel formation region formed using a crystalline semiconductor formed on an insulating substrate or an insulating layer;
A gate insulating film and a gate electrode formed on the channel formation region;
An insulated gate semiconductor device having an SOI structure having at least
The channel formation region is a region where carriers move,
An impurity region that is artificially and locally formed to pin a depletion layer extending from the drain region toward the channel formation region and the source region;
Have
An impurity element that shifts an energy band in a direction that prevents movement of electrons is added to the impurity region.

In addition, the configuration of other inventions is as follows:
A source region, a drain region and a channel formation region formed using a crystalline semiconductor formed on an insulating substrate or an insulating layer;
A gate insulating film and a gate electrode formed on the channel formation region;
An insulated gate semiconductor device having an SOI structure having at least
The channel formation region is a region where carriers move,
An impurity region that is artificially and locally formed to pin a depletion layer extending from the drain region toward the channel formation region and the source region;
Have
The impurity region is doped with an impurity element that shifts an energy band in a direction that prevents movement of holes.

In addition, the configuration of other inventions is as follows:
A source region, a drain region and a channel formation region formed using a crystalline semiconductor formed on an insulating substrate or an insulating layer;
A gate insulating film and a gate electrode formed on the channel formation region;
An insulated gate semiconductor device having an SOI structure having at least
The channel formation region is a region where carriers move,
An artificially and locally formed impurity region for controlling to a predetermined threshold voltage by addition of an impurity element;
Have
An impurity element that shifts an energy band in a direction that prevents movement of electrons is added to the impurity region.

In addition, the configuration of other inventions is as follows:
A source region, a drain region and a channel formation region formed using a crystalline semiconductor formed on an insulating substrate or an insulating layer;
A gate insulating film and a gate electrode formed on the channel formation region;
An insulated gate semiconductor device having an SOI structure having at least
The channel formation region is a region where carriers move,
An artificially and locally formed impurity region for controlling to a predetermined threshold voltage by addition of an impurity element;
Have
The impurity region is doped with an impurity element that shifts an energy band in a direction that prevents movement of holes.

In addition, the configuration of other inventions is as follows:
Forming a crystalline semiconductor on an insulating substrate or insulating layer;
Forming a source region, a drain region, and a channel formation region using the crystalline semiconductor;
Artificially and locally forming an impurity region in the channel formation region;
Forming a gate insulating film and a gate electrode on the channel formation region;
In a method for manufacturing an insulated gate semiconductor device including an SOI structure having at least
The channel formation region includes a region where carriers move and the impurity region,
An impurity element that shifts an energy band in a direction that prevents movement of electrons is artificially and locally added to the impurity region.

In addition, the configuration of other inventions is as follows:
Forming a crystalline semiconductor on an insulating substrate or insulating layer;
Forming a source region, a drain region, and a channel formation region using the crystalline semiconductor;
Artificially and locally forming an impurity region in the channel formation region;
Forming a gate insulating film and a gate electrode on the channel formation region;
In a method for manufacturing an insulated gate semiconductor device including an SOI structure having at least
The channel formation region includes a region where carriers move and the impurity region,
An impurity element that shifts an energy band in a direction that prevents movement of holes is artificially and locally added to the impurity region.

  The gist of the present invention is that the impurity region formed artificially and locally with respect to the channel formation region effectively suppresses the depletion layer extending from the drain region toward the channel formation region, and punch caused by the short channel effect. The purpose is to prevent various problems such as the through phenomenon, the deterioration of the subthreshold characteristic, and the deterioration of the breakdown voltage.

  The present applicant refers to the device according to the present invention as a pinning type semiconductor device because it is similar to forming a pin of an impurity region in a channel formation region. In the present specification, “pinning” means “suppression”, and “pinning” is used to mean “suppression”.

  That is, an impurity region is locally formed with respect to the channel formation region, and the region is used as an energy barrier. Then, by using the impurity region as an energy barrier, the depletion layer on the drain region side is energetically inhibited from spreading toward the channel formation region, and the electric field formed in the channel formation region is thereby only caused by the gate voltage. Be controlled.

  In order to achieve the above structure, the present invention uses an impurity element that shifts the energy band in a direction that prevents the movement of electrons or holes serving as carriers as an impurity element that forms an impurity region. As an impurity element that shifts the energy band in a direction that hinders the movement of electrons in the N-channel FET, a group 13 element (typically boron) is used, and the energy band in the direction that hinders the movement of holes in the P-channel FET. As the impurity element for shifting the element, a Group 15 element (typically phosphorus or arsenic) may be used.

  In this case, the added impurity element forms a high energy barrier. For example, when boron (B) that is an impurity element imparting p-type conductivity is added to an n-channel FET, the energy band of the channel formation region in the state shown in FIG. In the state shown in B), the barrier ΔE (called a diffusion potential difference or a built-in potential difference) is formed by shifting the Fermi level (Ef). The built-in potential difference in the state of FIG. 6B functions as an energy barrier that prevents the movement of electrons that are majority carriers of the N-channel FET.

  Of course, in this case, shifting the Fermi level is nothing but shifting the energy band of the channel formation region as a result. Further, the impurity region, which is a feature of the present invention, has reverse conductivity and has a low resistance value, but becomes a sufficient barrier in terms of energy.

  Similarly, when phosphorus (P) or arsenic (As) that is an impurity element imparting N-type conductivity is added to a P-channel FET, the channel formation region in the state shown in FIG. The energy band is in the state shown in FIG. The built-in potential difference in the state of FIG. 6D functions as an energy barrier that prevents movement of holes that are majority carriers of the P-channel FET.

  Further, in the present invention, the “region in which the carrier moves” is intrinsic or substantially intrinsic, which is a remarkable feature peculiar to a semiconductor device having an SOI structure. Note that an intrinsic region in this specification refers to a region not containing an impurity element, such as a single crystal silicon layer epitaxially grown on a sapphire substrate, or an impurity element imparting N-type or P-type and carbon, nitrogen, This refers to a region where an impurity element such as oxygen is not intentionally added.

  In addition, substantially intrinsic means a conductivity type that occurs without the intentional addition of an impurity element imparting N-type or P-type in a crystalline semiconductor (in this specification, single crystal silicon is a typical example). Or a region exhibiting the same conductivity type as the source and drain regions in a range where threshold control is possible.

In a substantially intrinsic region, the concentration of an impurity element (phosphorus or boron) imparting one conductivity in the vicinity of the surface of the crystalline semiconductor (crystalline silicon) is 5 × 10 ¹⁵ atoms / cm ³ or less (preferably 5 × 10 ¹⁴ atoms / cm ³ or less), and the oxygen concentration is 2 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁷ atoms / cm ³ or less).

  Note that the vicinity of the surface of the crystalline semiconductor here refers to a region which can function as a device element, and refers to a single crystal silicon layer of an SOI substrate or a region including at least a region where carriers move (inversion layer). Needless to say, the impurity region, which is a feature of the present invention, does not fall within the impurity concentration range because a large amount of impurity elements is contained in the impurity region.

  In this specification, single crystal silicon is a typical example of a crystalline semiconductor, but this single crystal silicon is of course the level of single crystal silicon generally used at the current IC and LSI levels. Furthermore, higher-level single crystal silicon (which is ultimately single crystal silicon in an ideal state as produced in outer space) is also included in the category.

  There are roughly two types of SOI structures. One is a structure in which a single crystal silicon layer is grown on an insulating substrate as represented by an SOS substrate. The other is a structure in which an insulating layer is formed in a single crystal silicon substrate as represented by a SIMOX substrate or a wafer bonding SOI. In particular, since 1986, the SIMOX substrate has been the main technology for forming the SOI structure.

  The present invention can be applied to all SOI substrates regardless of the method for manufacturing the SOI structure. That is, when a semiconductor device is manufactured, a method for manufacturing an SOI substrate or a method for obtaining a single crystal silicon layer can be determined as appropriate by a manufacturer.

  By utilizing the present invention, it is possible to prevent the short channel effect that occurs when the channel length is shortened. Specifically, the drain-side depletion layer is first blocked from spreading under the source region and the channel formation region by an impurity region locally formed in the channel formation region, and the drain voltage is changed to the energy (potential) state of the channel formation region. The configuration is not affected. As a result, it is possible to prevent the punch-through phenomenon and the deterioration of the subthreshold characteristics. At the same time, a high drain breakdown voltage can be realized.

  In addition, a decrease in threshold voltage, which is one of the characteristics of the short channel effect, can be suppressed by increasing the threshold voltage due to the narrow channel effect. This narrow channel effect can be artificially achieved by the structure of the present invention in which an impurity region is locally formed in a channel formation region.

  As described above, by using the present invention, a semiconductor device in a deep submicron region with an extremely short channel length can be operated without causing a short channel effect. Therefore, an integrated circuit integrated at a very high density can be formed by using the semiconductor device of the present invention.

  Further, in the present invention, by forming a slit-like lane region energetically in the channel formation region, it is possible to define the carrier moving direction and reduce scattering due to self-collision between carriers.

  That is, impurity scattering, lattice scattering, and scattering due to self-collision between carriers, which cause a decrease in carrier mobility, are greatly reduced, and the mobility is greatly improved. That is, further improvement in performance of a semiconductor device represented by IG-FET can be expected.

  Here, a case where the present invention is applied to an N-channel semiconductor device formed over a SIMOX substrate will be described with reference to FIG.

  FIG. 1A is a schematic diagram of the state when the source region, drain region, and channel formation region of the IG-FET of the present invention are viewed from above. Note that 101 is a source region, 102 is a drain region, and 103 is a channel formation region.

  A feature of the present invention is that the impurity region 104 is artificially and locally formed in the channel formation region 103. Although the case where the impurity region 104 is formed in a linear pattern shape is taken as an example here, the impurity region can also be provided in a dot pattern shape.

  Note that in the case where the impurity region 104 is provided in a linear pattern shape substantially parallel to the channel direction (the direction connecting the source and the drain or the direction in which the carriers move), the impurity region serves as a side wall to define the carrier movement. Since a typical rail is formed, an advantage that the probability of occurrence of scattering due to collision between carriers is reduced and the mobility is improved is desirable.

  Further, the applicant of the present application calls a path in which carriers move, that is, a region between the impurity region and the impurity region, as a potential slit region or a lane region.

  Here, the case where the impurity region 104 having a linear pattern shape is formed substantially parallel to the channel direction from one end to the other end in the channel formation region 103 (for example, from the source region 101 to the drain region 102). Give an explanation. In addition, a case where boron is used as an impurity to be added is taken as an example.

  As described above, the impurity region 104 whose energy band has been shifted in a direction that hinders the movement of electrons, which are majority carriers, by adding boron, has a built-in potential difference that becomes a sufficiently large barrier in terms of energy against the movement of electrons. Form. Therefore, carriers (electrons here) do not move through the impurity region 104.

  In particular, as shown in FIG. 1A, the junction between the drain region 102 and the channel formation region 103 is a region where the electric field changes most drastically. Therefore, it is desirable to arrange the impurity region 104 at this position. In addition, when the electric field due to the gate electrode extends into the drain region 102, the impurity region 104 is preferably applied over the drain region 102. Conversely, it is preferable that the impurity region 104 does not enter the source region 101.

  In addition, the present invention is extremely effective in forming a fine element that requires fine processing in the deep submicron region, such as 0.35 μm or less (particularly 0.1 μm or less), or 0.01 μm or less. Therefore, since the length of the channel formation region (channel length or source / drain distance) is as short as 0.01 to 0.35 μm, the impurity region must be cut into a finer pattern.

  For example, when a resist mask is used when forming a linear pattern-like impurity region, patterning for providing an opening in the resist mask cannot use a normal exposure method due to resolution problems. In such a case, a fine pattern in the deep submicron region can be obtained by using techniques such as an exposure method using an excimer laser such as KrF or ArF, an electron (beam) drawing method, and a FIB (Focussed Ion Beam) method. Should be realized.

  Further, since the impurity regions are artificially arranged by patterning, not only the arrangement as shown in FIG. 1A but also various arbitrary arrangements can be employed.

  Next, when the insulated gate semiconductor device (IG-FET) having the structure of the source region / channel formation region / drain region shown in FIG. 1A is driven, how the short channel effect is suppressed. This will be described below.

  First, FIG. 1B shows a cross-sectional view taken along A-A ′ of FIG. 105 is a silicon substrate, and 106 is a buried oxide film. Since the impurity region 104 is formed so as to connect the source region 101 and the drain region 102, the impurity region 104 appears in a cross section taken along A-A ′ as shown in FIG.

  1C is a cross-sectional view taken along B-B ′ of FIG. FIG. 1C shows a cross section in which the channel formation region 103 is cut perpendicular to the channel direction.

  At this time, the width of a certain impurity region 104 is represented by wpi, n, and the interval between the impurity regions (the width of the potential slit region) is represented by wpa, m. Here, n and m mean that wpi, n is the width of the n-th impurity region in the channel formation region 103, and wpa, m is the m-th potential slit region (path where carriers move). ing.

  The description so far has only been a description of the structure, but the effect will be described next. Here, FIG. 2A is a schematic view focusing on only the channel formation region of the IG-FET of the present invention.

  First, when a gate voltage and a drain voltage are applied to a semiconductor device having a structure as shown in FIG. 1B, the source-side depletion layer 201, the channel side in the state as shown in FIG. A depletion layer 202 and a drain side depletion layer 203 are formed. That is, the drain side depletion layer 203 has a shape in which the impurity region 204 serves as a barrier to prevent the drain side depletion layer 203 from spreading to the source side. Reference numeral 205 denotes a part of the buried oxide film.

  Although it is difficult to understand in FIG. 1B, the impurity regions 204 are arranged as shown in FIG. 1A, and are arranged in a state as shown in FIG. 1C when viewed from the channel direction. Therefore, it is easy to understand by considering a model in which the spread of the drain side depletion layer is suppressed by a lattice filter that blocks the channel formation region 103.

  Accordingly, in the semiconductor device having the structure according to the present invention, as shown in FIG. 2A, the depletion layers are divided without substantially interfering with each other. That is, since the source-side depletion layer 201 and the channel-side depletion layer 202 are distributed without being affected by the drain-side depletion layer 203, the energy state is as shown in FIG.

  That is, unlike the conventional energy state diagram shown in FIG. 4, the energy state of the channel region is controlled only by the electric field due to the gate voltage, and thus has a shape substantially parallel to the channel region. Therefore, there is no problem such as a punch-through phenomenon peculiar to the short channel effect, and a semiconductor device having a high drain breakdown voltage can be manufactured.

  Furthermore, as shown in FIG. 2 (A), in the present invention, even when the drain voltage is high, the volume occupied by the depletion layer is reduced compared to the conventional one as shown in FIG. The depletion layer charge is smaller than before, and the depletion layer capacitance is small. Here, the equation for deriving the S value is expressed by the following equation.

  That is, as described above, it can be seen that the reciprocal of the slope in the region indicated by 501 in the graph shown in FIG. Further, the expression of Equation 3 can be approximately expressed as the following expression.

  In Equation 4, k is the Boltzmann constant, T is the absolute temperature, q is the charge amount, Cd is the depletion layer capacitance, Cit is the equivalent capacitance of the interface state, and Cox is the gate oxide film capacitance. Therefore, according to the present invention, since the depletion layer capacitance Cd is sufficiently smaller than that of the conventional one, the S value can be set to a small value of 85 mV / decade or less (preferably 70 mV / decade or less), that is, excellent subthreshold characteristics. Can be obtained.

  Further, the present invention aims to make the depletion layer capacitance Cd and the interface state equivalent capacitance Cit as close as possible to zero. That is, the S value (60 mV / decade) in an ideal state where Cd = Cit = 0 is brought close to.

  In addition, the channel formation region having the structure shown in FIG. 1C is very important in mitigating the decrease in threshold voltage due to the short channel effect. This is because the structure shown in FIG. 1C is necessary for intentionally producing the narrow channel effect.

  The narrow channel effect is a phenomenon that has been confirmed in MOSFETs originally formed on bulk silicon, such as the effects of bird's beaks in field oxide films that isolate elements when the channel width becomes narrow, and the effects of impurity diffusion in channel stoppers, etc. In response, the threshold voltage increases.

  One of the ideas constituting the present invention is to intentionally generate a narrow channel effect by artificially forming and arranging an impurity region in the channel formation region. In the structure of the present invention, the threshold voltage is controlled by precisely controlling the distance between the impurity regions (corresponding to wpa, m in FIG. 1C) in the range of 30 to 3000 mm (preferably 30 to 1000 mm). This is based on the idea of performing control.

  For example, focusing on a cross section as shown in FIG. 1C, the width W of the channel formation region is divided by the impurity region 104, and an aggregate of a plurality of channel formation regions having a substantially narrow channel width wpa, m. Can be considered.

  That is, it is considered that a narrow channel effect can be obtained in a region having a plurality of narrow channel widths wpa, m. When viewed macroscopically, as shown in FIG. 1A, since there is a region where such a narrow channel effect can be obtained in the entire channel formation region, the narrow channel effect can be obtained as a whole, and the threshold voltage is reduced. It is thought to increase.

  Therefore, even if the threshold voltage is lowered due to the short channel effect due to the shortening of the channel length, the threshold voltage can be controlled by intentionally increasing the threshold voltage due to the narrow channel effect for the above reasons. As a result, it is possible to moderate the change in the threshold voltage.

  The present invention having the above-described configuration will be described in detail with the embodiments described below. Further, the embodiment described here shows an example of the configuration of the present invention, and various applications can be implemented according to the needs of the semiconductor device manufacturer.

  Therefore, it is considered that the matters described in the claims include all the inventions that can be made with the configuration of the present invention, even if the application is other than the examples described below.

  An example of forming an insulated gate field effect transistor on a SIMOX substrate using the present invention will be described with reference to FIG. In this embodiment, an example in which a CMOS circuit in which an N-channel FET and a P-channel FET are complementarily combined is formed will be described.

First, a single crystal silicon substrate 701 having weak N-type or P-type conductivity is prepared. Then, oxygen ions are implanted at a dose of about 1 × 10 ¹⁸ atoms / cm ² , and a heat treatment is performed in the range of 800 to 1300 ° C. to form a buried oxide film 702. Thus, a buried oxide film 702 having a thickness of 0.05 to 0.5 μm and a single crystal silicon layer 703 having a thickness of 100 to 2000 mm (preferably 200 to 600 mm) are obtained.

  At this time, one of the most significant features of the SOI technology is that one to several impurity elements contained in the obtained single crystal silicon layer 703 (which are included in advance in the base single crystal silicon substrate 701). The point is that a highly pure intrinsic or substantially intrinsic single crystal silicon layer can be obtained.

  Needless to say, the thickness of the buried oxide film 702 and the thickness of the single crystal silicon layer 703 are not limited to the values in the range shown in this embodiment, and can be appropriately adjusted as necessary. For a detailed description of the SIMOX substrate, see, for example, Maruzen Co., Ltd., Fumio Shimura, Semiconductor Silicon Crystal Engineering, published on September 30, 1993, P217 and below.

  In this way, a SIMOX substrate as shown in FIG. 7A is obtained. Of course, instead of a SIMOX substrate, an SOI substrate formed by using a wafer bonding technique, an SOS substrate in which a single crystal silicon layer is grown on an insulating substrate such as a sapphire substrate, and FIPOS using the oxidation of porous silicon ( Other types of SOI substrates such as Full Isolation by Porous Oxidized Silicon) substrates may be used.

  When the state of FIG. 7A is obtained, a thermal oxidation process is performed to form a thin thermal oxide film (not shown), and mask patterns 704 and 705 made of a silicon nitride film are formed thereon. At this time, the mask pattern 704 is disposed on the subsequent N-channel FET, and the mask pattern 705 is disposed on the subsequent P-channel FET.

  In this state, thermal oxidation is performed at a high temperature of about 1000 to 1200 ° C. to form a field oxide film 706 for element isolation. In this way, a region 707 that becomes an active layer of an N-channel FET and a region 708 that becomes an active layer of a P-channel FET are obtained.

  When the state shown in FIG. 7B is thus obtained, the mask patterns 704 and 705 and the thermal oxide film (not shown) are removed. Then, P (phosphorus) is added to form the source region 709 and drain region 710 of the N-channel FET, and further B (boron) is added to form the source region 711 and drain region 712 of the P-channel FET. .

  At this time, phosphorus and boron may be separated using a resist mask. At this time, the region to which no impurity is added is an intrinsic or substantially intrinsic region, and constitutes an N-channel FET channel formation region 713 and a P-channel FET channel formation region 714. (Fig. 7 (C))

As described above, when the channel formation region is an intrinsic or substantially intrinsic region, the active layer of the semiconductor device is N ⁺ (source region) −I (channel formation region) when an N-channel FET is taken as an example. The structure is such as −N ⁺ (drain region). Here, N ⁺ means a strong N-type, and I means intrinsic or substantially intrinsic.

In addition to such a configuration, for example, N ⁺ (source region) −N ⁻ (channel forming region) −N ⁺ (drain region), P ⁺ (source region) −P ⁻ (channel forming region) −P It is also possible to adopt a configuration such as ⁺ (drain region). Incidentally, N ^- is the very weak N-type, P ^- is meant to indicate a very weak P-type.

  Such a configuration has an advantage that the mobility is improved, but has a problem that the breakdown voltage is lowered. However, since a semiconductor device having high breakdown voltage characteristics can be manufactured by using the present invention, high mobility and high breakdown voltage can be satisfied at the same time.

  Next, when the state shown in FIG. 7C is obtained, boron (B) is added to the channel formation region 713 of the N-channel FET as shown in FIG. Phosphorus (P) or arsenic (As) is added to the channel formation region 714 to form impurity regions 715 and 716 that serve as stoppers for the depletion layer. The regions 715 and 716 to which the impurity element is added are selectively designed by providing openings in a resist mask (not shown) by patterning.

  Note that since the impurity regions 715 and 716 need to be formed with extremely fine processing dimensions, an elaborate lithography technique is required. For this purpose, the exposure of the linear pattern shape may be performed using a technique using an electron beam (electronic drawing method), a technique using an ion beam (FIB method), a technique using an excimer laser, or the like.

  At this time, the width (wpa, m) of the potential slit region is controlled within the range of 30 to 3000 mm (preferably 30 to 1000 mm). Further, all the intervals (wpa, m) are controlled to be within ± 20% (preferably within ± 5%). Since the width (wpa, m) of this potential slit region directly affects the narrow channel effect, it is important to control it precisely.

  Note that the value of 30 mm, which is the lower limit of the width of the potential slit region, is determined as a limit value at which the quantum effect does not occur. In the present invention, care is taken to control the width of the potential slit region within a range where the quantum effect does not occur or does not appear.

  Accordingly, the impurity regions 715 and 716 arranged as in the top view shown in FIG. 1A are formed in a state in which all the widths (wpa, m) of the potential slit region are aligned. Therefore, variations in threshold voltage (caused by variations in the narrow channel effect) and variations in heat generation (caused by variations in current density flowing through the potential slit region) can be effectively suppressed.

  In order to effectively improve the breakdown voltage of the semiconductor device, it is effective to dispose the impurity regions 715 and 716 so as to enter the drain regions 710 and 712 as shown in FIG. At this time, the source region may or may not be arranged so that it does not enter, but it is preferable that the source region does not enter (in this embodiment, the impurity region enters the source region in order to clarify the boundary of the channel formation region. To do).

  In the case where an LDD region is provided between the channel formation region and the source / drain region, it is preferable to form the impurity region up to the inside of the LDD region or beyond the LDD region to the inside of the drain region. . Such a configuration is effective for further improving the breakdown voltage of the semiconductor device.

  When the state as shown in FIG. 7D is obtained, thermal oxidation is performed in a temperature range of about 800 to 1200 ° C. to form thermal oxide films 717 and 718 of 100 to 500 mm. Thin thermal oxide films 717 and 718 formed by this thermal oxidation process function as gate insulating films as they are. In addition, the active layer / gate insulating film interface is excellent with few interface states.

  In addition, it is also preferable to perform the said thermal oxidation process in a halogen atmosphere. In that case, heavy metals such as Ni (nickel) and Cu (copper) segregated at the interface between the impurity regions 715 and 716 and the potential slit region can be gettered and removed.

  These heavy metals remain in the interior in the course of forming single crystal silicon and the like, and may become a carrier recombination center and reduce mobility. Therefore, if the thermal oxidation process is performed in a halogen atmosphere, a gettering effect of a metal element by a halogen element (for example, chlorine, fluorine, etc.) can be expected.

  Further, polysilicon films 719 and 720 are formed as gate electrodes on the thermal oxide films 717 and 718 above the channel formation regions 713 and 714. The gate electrodes 719 and 720 may be made conductive by adding an impurity element in advance at the stage of film formation. In this way, the state shown in FIG.

  Thereafter, as shown in FIG. 8B, a silicon nitride film is formed to a thickness of 3000 mm so as to cover the gate electrodes 719 and 720, and is etched only on the side surfaces of the gate electrodes 719 and 720 by using an etch back method. The side walls 721 and 722 are left. At this time, the gate insulating film in the source / drain regions is simultaneously removed.

  Next, in this state, a titanium film (not shown) is formed on the entire surface by sputtering, and silicide is formed by means such as heating, laser annealing, and lamp annealing. By this step, titanium silicides 723 to 725 are formed on the surfaces of the source region 709 and drain region 710 of the N-channel FET and the surface of the gate electrode 719.

  At the same time, titanium silicides 726 to 728 are formed on the surfaces of the source region 711 and the drain region 712 of the P-channel FET and the surface of the gate electrode 720.

  Since titanium silicides 723 to 728 have extremely low resistance, they are preferable for ensuring ohmic contact with wirings to be formed later. (Fig. 8 (B))

  When the silicide formation is completed, a silicon nitride film 729 is formed as an interlayer insulating film, contact holes are formed, and the source electrode 730 of the N-channel FET, the source electrode 731 of the P-channel FET, and the N / P channel FET are also used. The drain electrode 732 is formed. In this way, an IG-FET having a CMOS structure as shown in FIG. 8C is completed.

  Since the CMOS circuit having the structure shown in FIG. 8C can be miniaturized without causing the problem of the short channel effect of the present invention, an integrated circuit with a very high degree of integration can be formed.

  In this embodiment, a single gate type IG-FET is taken as an example. However, since it has an SOI structure, the present invention can be applied to the case where a double gate type FET in which a channel is formed on the upper and lower surfaces of the active layer is manufactured. . Of course, it can also be applied to power MOSFETs, MESFETs, MISFETs, and the like.

  In this embodiment, the impurity region is formed in a linear pattern in the channel formation region of the IG-FET. However, the formation of the linear pattern needs to satisfy a certain range of conditions. This will be described below with reference to FIG.

In FIG. 9, reference numeral 901 denotes a part of the channel formation region. The channel width is W. Here, of the channel width W, the width occupied by the linear pattern 902 is defined as Wpi. As the value of Wpi, for example, 10 to 100 Å is sufficient. If the width of an arbitrary linear pattern 902 is Wpi, ₁ , Wpi, ₂ , Wpi, ₃ ... Wpi _{, n} , Wpi is expressed by the following equation.

  However, in order to achieve the configuration of the present invention, since at least one impurity region needs to be formed in a region other than the end of the channel formation region, n is an integer of 1 or more.

Of the channel width W, the width occupied by the potential slit region (carrier moving path) 903 is defined as Wpa. The value of Wpa is a level at which the quantum effect does not appear, that is, 30 to 3000 cm (preferably 30 to 1000 cm). In the present invention, Vth, n and Vth, p can be adjusted in the range of 0 to ± 0.3 V by setting Wpa to about 1/3 to 1/1 of the channel length (0.01 to 0.35 μm). If an arbitrary potential slit region 903 is Wpa, ₁ , Wpa, ₂ , Wpa, ₃ ... Wpa _{, m} , Wpa is expressed by the following equation.

  However, since at least one impurity region is formed in a region other than the end of the channel formation region as described above, the channel formation region is divided into at least two and m is an integer of 2 or more.

That is, the relationship that the total channel width W is W = Wpi + Wpa and n + m is 3 or more is established. The relationship between W and Wpi, W and Wpa, and Wpi and Wpa preferably satisfy the following conditions at the same time.
Wpi / W = 0.1-0.9
Wpa / W = 0.1-0.9
Wpi / Wpa = 1/9 to 9

  The meaning of these mathematical expressions is that Wpa / W or Wpi / W must not be 0 or 1. For example, when Wpa / W = 0 (synonymous with Wpi / W = 1), the channel formation region is completely blocked with the impurity region as shown in FIG. Become.

  On the contrary, when Wpa / W = 1 (synonymous with Wpi / W = 0), as shown in FIG. 9C, no impurity region is present in the channel formation region, so that the spread of the drain side depletion layer cannot be suppressed. .

  For the above reasons, it is desirable that the relational expressions of Wpa / W and Wpi / W fall within the range of 0.1 to 0.9 (preferably 0.2 to 0.8), and at the same time satisfy Wpi / Wpa = 1/9 to 9.

  In the present invention, the arrangement of impurity regions having a linear pattern shape as shown in FIG. 1A has a very significant meaning for improving mobility, which is a typical parameter indicating the performance of an FET. is there. The reason will be described below.

  The mobility is determined by the scattering of carriers in the semiconductor (a silicon substrate in this embodiment), and the scattering in the silicon substrate is roughly divided into lattice scattering and impurity scattering. Lattice scattering has a low impurity concentration in the silicon substrate and is dominant at a relatively high temperature, and impurity scattering has a high impurity concentration and is dominant at a relatively low temperature. The overall mobility μ formed by these influences is expressed by the following equation.

The equation shown in Equation 5 is obtained when the overall mobility μ is affected by the reciprocal of mobility μ _l when _l is affected by lattice scattering ( _l means lattice) and by impurity scattering. This means that it is inversely proportional to the sum of the reciprocal of mobility μ _i ( _i means impurity).

Here, if the drift electric field is not so strong in the lattice scattering, the acoustic phonon plays an important role, and the mobility μ _l at that time is proportional to the −3/2 power of the temperature as shown in the following equation. Therefore, it is determined by the effective mass (m *) and temperature (T) of the carrier.

Moreover, the mobility mu _i due to impurity scattering is proportional to 3/2 power of the temperature as indicated by the following expression and inversely proportional to the concentration N _i of ionized impurities. That can be varied by adjusting the concentration N _i of ionized impurities.

  According to these equations, channel doping in which impurities are added to the entire channel formation region as in the prior art cannot gain mobility due to the influence of impurity scattering. However, since the impurity region is locally formed in the present invention, no impurity is added to the potential slit region (region having a width of Wpa).

In other words, it means that the closer to 0 without limit concentration N _i of impurities ionized in the number 7 in theory, the mobility mu _i will be approaching infinity as possible. That is, in Equation 5, the impurity is reduced to such an extent that the term of 1 / μ _i can be ignored, so the entire mobility μ approaches the mobility μ _l without limit.

It is also theoretically possible to further increase the mobility mu _l by reducing the effective mass of the carriers (m *). This can be achieved by utilizing a phenomenon in which the effective mass of carriers (especially in the case of electrons) varies depending on the crystal axis orientation in a cryogenic region.

  According to the literature, the minimum effective mass can be obtained when the channel direction connecting the source / drain (the direction in which carriers move) is configured to coincide with the <100> axis direction of single crystal silicon.

  For example, as shown in FIG. 10, a source region 1002, a channel formation region 1003, and a drain region 1004 are formed on a single crystal silicon substrate 1001 having a (100) plane. At this time, this corresponds to a case where the channel direction 1005 is set to [100]. However, this example is a result in an extremely low temperature region of 4 ° K.

  In addition, the channel direction and the axial direction (arrangement direction) of the impurity regions 707 and the axial direction of the crystal lattice are approximately parallel (the axial deviation is within ± 10 ° so that carriers can pass through the crystal lattices well). It is desirable to make it fit. In the case of a single crystal, since silicon atoms are regularly arranged, carriers moving parallel to the crystal lattice arrangement direction are hardly affected by lattice scattering.

  For example, when the rotation axis in the above-mentioned direction is 0 ° in the single crystal silicon substrate, the same effect can be obtained in the case of rotation shafts of 90 °, 180 °, and 270 °.

  As described above, carriers that move in the channel formation region pass through regions other than the impurity regions existing in the channel formation region. This will be briefly described with reference to the schematic diagram of FIG.

  In FIG. 11A, reference numeral 1101 denotes a channel formation region. That is, FIG. 11A is a view of the channel formation region as viewed from the upper right. In the three-dimensional channel formation region in which this embodiment is implemented, an impurity region 1102 is formed as shown in FIG.

  An arrow 1103 described in FIG. 11A indicates the traveling direction of carriers (electrons or holes). As shown in FIG. 11A, a plurality of impurity regions 1102 are arranged in the channel formation region 1101, and carriers pass through regions other than the impurity regions 1102.

  When the traveling direction of the carrier is viewed from the upper surface of the channel formation region 1101, it looks as shown in FIG. FIG. 11B is a view of the surface represented by ACEF in FIG. As shown in FIG. 11B, the carriers avoid the impurity region 1102 and move in a region without impurity scattering.

  That is, most carriers move between the source / drain through the impurity regions 1102 as indicated by arrows. Of course, when the impurity region is provided in a dot pattern shape, the case where the impurity region moves in a zigzag manner so as to avoid the impurity region is also included.

  FIG. 11C illustrates the channel formation region 1101 as viewed from the side. Note that FIG. 11C illustrates the surface represented by ABCD in FIG. Reference numeral 1103 denotes an arrow, which indicates that the arrow head is directed toward the front of the page. This figure also shows that carriers move between the impurity regions 1102.

  A distribution diagram schematically showing the energy state (potential state) in a region (potential slit region) sandwiched between impurity regions having a linear pattern shape is considered to be as shown in FIG. .

  In FIG. 12A, regions 1201 and 1202 indicate the energy state of the impurity region, which is a high energy barrier. As the distance from the impurity region increases, the region 1203 gradually becomes lower in energy. That is, carriers moving in the channel region (here, electrons are taken as an example) move preferentially in a low energy state indicated by 1203, and energy barriers (impurity regions) indicated by 1201 and 1202 are like walls. Play an important role.

  Here, an image of carriers (electrons) moving in the channel region is schematically shown in FIG. In terms of image, the carrier 1200 moving in the channel region is defined in its direction like a sphere rolling in a gutter as shown in FIG. 12B, and is almost the shortest from the source region to the drain region. Move the distance.

  The present applicant regards the energy distribution as shown in FIG. 12A as an electrical slit and calls it a potential slit region. In addition, a sphere rolling on a lane may be imaged from a model as shown in FIG.

  In addition, as shown in FIG. 12B, the channel formation region is formed by arranging a plurality of potential slit regions as shown in FIG. 12A in parallel. Therefore, carriers do not move between adjacent potential slit regions.

  For the above reason, the probability that a carrier collides with another carrier is greatly reduced, so that the mobility is greatly improved. In other words, the configuration of the present invention can not only reduce the impurity scattering but also reduce the scattering due to self-collision between carriers, thereby realizing a significant improvement in mobility.

  As described above, the idea of the present invention to intentionally form and use energy barriers (grain boundaries, etc.) that have always been considered to have adverse effects in the past is very new.

  In the present invention, as a means for forming an impurity region in the channel formation region, a method utilizing the segregation action of impurities can be used. In this embodiment, as such an example, a method using segregation of boron (B) and phosphorus (P) in the vicinity of the thermal oxide film will be described with reference to FIGS.

  The present embodiment is a technique using a phenomenon in which the impurity element (boron or phosphorus) contained in the periphery of the impurity region (potential slit region) is segregated in the impurity region. Here, the distribution of the boron or phosphorus concentration in the vicinity of the thermal oxide film / silicon interface in the thermal oxidation step will be described with reference to FIG.

As shown in FIG. 13, the added ions (B, P) present in Si are redistributed when an oxide film is formed. This is a phenomenon that occurs because the solubility and diffusion rate of the added ions differ in silicon (Si) and in the thermal oxide film (SiO _x ). The solubility in Si impurity and [C] _Si, when the solubility in SiO _x and [C] _SiOx, equilibrium segregation coefficient m is defined by the following equation.
m = [C] _Si / [C] _SiOx

At this time, the segregation of impurities near the Si / SiO _x interface is governed by the value of m. Normally, assuming that the diffusion coefficient of impurities in Si is sufficiently large, when m <1, the impurities in Si are taken into SiO _x (FIG. 13A). When m> 1, SiO _x eliminates impurities, and as a result, the impurity concentration near the Si / SiO _x interface increases (FIG. 13B).

According to literature values, the value of m for boron is about 0.3 and the value of m for phosphorus is about 10. Therefore, the boron concentration distribution after the thermal oxidation process in this embodiment is as shown in FIG. 13A, and boron is taken into the thermal oxide film, and boron on the side surface of the impurity region (near the Si / SiO _x interface). The concentration is extremely small. On the contrary, a large amount of boron is contained in the thermal oxide formed.

  Such a phenomenon of boron incorporation into the thermal oxide film has already been known, but the idea of utilizing this phenomenon to form an energy barrier (impurity region) as in the present invention is completely new.

  As shown in FIG. 13B, when phosphorus is used as the impurity element, segregation (pile-up) occurs at the interface between the thermal oxide film and silicon. This phenomenon can also be utilized when forming an impurity region in a P-channel FET.

  Next, an example in which an impurity region is actually formed will be described with reference to FIGS. FIG. 14A is an enlarged view of only the single crystal silicon layer of the SOI substrate. Reference numeral 1401 denotes an insulating layer, and 1402 denotes a single crystal silicon layer. As the SOI substrate, an SOS substrate, a SIMOX substrate, a FIPOS substrate, or the like can be used.

  Then, a resist pattern 1403 for forming an impurity region is disposed on the channel formation region using a fine lithography technique such as an electron beam method, an FIB method, or an excimer laser method.

  When the state shown in FIG. 14A is obtained, Ar (argon) is added by an ion implantation method. In this embodiment, Ar is used, but a rare gas such as He (helium) or Ne (neon) may be injected. (Fig. 14B)

  Since the purpose of this ion implantation is to damage the single crystal silicon layer, an electrically inactive element is used. This is because the method disclosed in this embodiment uses the property that the damaged region is preferentially oxidized when single crystal silicon is thermally oxidized.

  Therefore, the region 1404 to which Ar is added in FIG. 14B is a region in which the crystal arrangement is disordered, compared with other regions.

Next, after removing the resist pattern 1403, heat treatment is performed in a temperature range of 800 to 1200 ° C. as shown in FIG. In this example, the first 30 minutes of the treatment at 1000 ° C. for 60 minutes was treated in an oxidizing atmosphere, and the remaining time was 90% nitrogen (N ₂ ), 9% oxygen (O ₂ ), and hydrogen chloride (HCl). The processing is continued by switching to a 1% halogen atmosphere.

  That is, the first 30 minutes is a heat treatment for thermal oxidation, and the next 30 minutes is a heat treatment aimed at the gettering effect of the metal element by the halogen element. The latter heat treatment is performed in an atmosphere with a high nitrogen content in order to prevent the single crystal silicon layer from being excessively oxidized.

  Thus, as shown in FIG. 14C, a thermal oxide film 1405 is formed in the single crystal silicon layer. At the same time, the oxidation reaction preferentially proceeds in the region 1404 to form an impurity region (in this case, made of silicon oxide) 1406 that penetrates into the single crystal silicon layer. Note that although the impurity region 1406 does not reach the lower insulating layer 1401 in FIG. 14C, it may reach the insulating layer depending on Ar implantation conditions.

  In addition, this embodiment can be carried out even when the single crystal silicon layer is directly irradiated with an electron beam or a focused ion beam to cause damage.

  The impurity region 1406 formed as described above segregates impurity elements contained in the surrounding potential slit region in the process of being oxidized. Therefore, if an impurity element imparting one conductivity to the channel formation region is added in advance, it is segregated inside the impurity region 1406 (in the case of boron) or segregated on the side surface of the impurity region 1406 (phosphorus). in the case of). Accordingly, boron is segregated in the oxide when manufacturing the N-channel FET, and phosphorus is segregated on the side surface of the oxide when manufacturing the P-channel FET. A configuration can be obtained.

  In this embodiment, the gettering effect of the metal element by the halogen element and the segregation phenomenon of phosphorus or boron to the thermal oxide film are used together, so that the region where the carrier moves is intrinsic or substantially intrinsic. (In particular, the periphery of the impurity region 1406) 1407 has a structure in which no impurity element that causes impurity scattering or a recombination center exists.

This corresponds to the increase in μ _i in Equation 5 as described above, so that the overall mobility μ ideally approaches μ = μ _l . That is, it shows that an extremely large mobility determined substantially only by lattice scattering can be realized. As described above, according to this embodiment, a semiconductor device having extremely high mobility can be manufactured.

  In this embodiment, an example in which the shape of the impurity region formed in the channel formation region is a dot pattern is shown. The description will be given with reference to FIG. For convenience of explanation, the same reference numerals as those in FIG.

  The structure of the semiconductor device shown in FIG. 15 is obtained by replacing the impurity region having a linear pattern shape in FIG. 1 with a dot pattern shape. First, what is different from FIG. 1 is that an impurity region 1501 is arranged as shown in FIG.

  Further, a cross section taken along line A-A 'of FIG. 15A is as shown in FIG. 15B, and a cross section taken along line B-B' is as shown in FIG.

  In this embodiment, a circular impurity region is described as an example of a dot pattern-like impurity region, but an elliptical shape, a square shape, a rectangular shape, or the like may be used.

  When the impurity region is formed in a dot pattern, the role of the lane region shown in the first embodiment is eliminated, but the effective channel area through which carriers can move increases, so that the amount of current that can be passed through the semiconductor device can be increased. .

  In the first and third embodiments, the case of the linear pattern shape and the case of the dot pattern shape have been described as the simplest shapes as the shape of the impurity regions. In this embodiment, various variations of the shape of the impurity region will be described.

  The shape shown in FIG. 16A is another variation of the linear pattern shape. The structure shown in FIG. 16A ensures the effect of pinning (suppressing) a depletion layer extending from the drain region side to the channel formation region side in the present invention, and prevents the punch-through phenomenon due to the short channel effect. This is the structure that puts this first.

  In FIG. 16A, the feature of the impurity region 1601 is a shape in which a concavo-convex portion 1602 is provided on the side surface of the impurity region having a linear pattern shape when viewed from the upper surface, which is a so-called fishbone shape. It is that. That is, the uneven portion 1602 on the side surface effectively suppresses the spread of the depletion layer.

  An example in which the configuration of FIG. 16A is further developed to further secure the pinning effect is the configuration shown in FIG. In other words, the fishbone shape that is alternately meshed can increase the area facing the depletion layer and effectively prevent the depletion layer from spreading.

  At this time, as shown in FIG. 16B, it is desirable to form a certain uneven portion (a portion corresponding to the bone of the fishbone) so as to alternately overlap with the uneven portion of the adjacent impurity region (indicated by 1603). Area).

  However, in this structure, it is inevitable that the moving distance becomes long because the carrier moves along the broken line indicated by 1604. The longer movement distance may increase the carrier scattering probability and reduce the mobility.

  However, in the extremely fine semiconductor device in which the present invention is effective, it is considered that the influence of impurity scattering does not change greatly even if the movement distance is somewhat longer as long as the channel formation region is intrinsic or substantially intrinsic. . It can be said that it is more important to suppress the influence of the short channel effect (particularly the punch-through phenomenon) accompanying the miniaturization.

  When attention is paid to a certain impurity region, the distance between adjacent concave and convex portions (distance represented by Lpa in the figure) needs to be controlled. That is, it is preferable to shorten the distance Lpa in order to enhance the pinning effect, and to increase the distance Lpa if the emphasis is on improving mobility. In the present invention, the distance Lpa is controlled in the range of 70 to 3000 mm (preferably 100 to 1000 mm).

  In the case of the structure shown in FIG. 16B, the width and length of a region (potential slit region) 1605 where carriers other than the impurity region move affect the mobility of carriers.

  Further, the present invention can adopt various variations not only when forming a linear pattern but also when forming a dot pattern-like impurity region. For example, as shown in FIG. 16C, the impurity regions 1606 can be alternately arranged.

  In this case, since the gap between the dot pattern-like impurity regions 1606 is compensated for by adjacent columns, the effect of suppressing the spread of the depletion layer is enhanced. Also in this case, the carrier movement path is as shown by a broken line 1607, but as described above, it does not matter much as the element becomes finer.

  In addition, as illustrated in FIG. 16D, the impurity region 1608 having a dot pattern shape may be an ellipse or a rectangle perpendicular to the channel direction. The structure shown in FIG. 16D can be said to be an effective structure when depletion layer suppression is a top priority issue.

  As described above, in order to effectively prevent the punch-through phenomenon due to the short channel effect, the shape of the impurity region may be devised. Since the impurity region is artificially formed, the shape can be designed freely by the creator.

  In particular, the shapes shown in FIGS. 16A to 16D as shown in this embodiment are effective in forming an extremely fine semiconductor device having a channel length of 0.1 μm or less. . This is because, in such a fine element, a decrease in breakdown voltage due to the punch-through phenomenon becomes a fatal problem, and thus the improvement in breakdown voltage should be emphasized rather than an improvement in mobility.

  In the present embodiment, an example in which a device different from the fourth embodiment is applied when forming the impurity region of the present invention will be described. This embodiment will be described with reference to FIG.

  FIG. 17A shows an example in which the width (Wpi) of the impurity region 1701 is changed between the vicinity of the source region 1702 and the vicinity of the drain region 1703. Specifically, the structure is such that Wpi gradually increases as it approaches the vicinity of the drain region 1703.

  With the configuration as shown in FIG. 17A, it is possible to effectively suppress the spread of the depletion layer on the drain region side that causes the punch-through phenomenon associated with the short channel effect. On the source region side, the potential slit region 1704 has a sufficiently wide width (Wpa), so that the carriers can be moved smoothly.

  This configuration is not limited to the configuration shown in FIG. 17A. For example, the length of the uneven portion 1706 of the impurity region 1705 having a fishbone shape is made closer to the drain region 1707 as shown in FIG. It can also be achieved as a configuration in which the length increases with time.

  Further, as illustrated in FIG. 17C, a structure in which the concentration of the impurity element included in the impurity region 1609 is increased in the vicinity of the drain region 1708 can be employed. In this case, as shown in FIG. 17C, an impurity region 1709 is formed from the source region 1710 to the drain region 1708 when viewed from above.

  The concentration of the impurity element included in the impurity region 1709 can be higher in the vicinity of the drain region 1708 than in the vicinity of the source region 1710. (Fig. 17 (D))

  Note that FIG. 17D is a graph showing changes in the concentration of impurity elements in the impurity region 1709, where the horizontal axis represents distance and the vertical axis represents concentration. As shown in FIG. 17D, in order to make the concentration profile in the vicinity of the source region 1711 different from the concentration profile in the vicinity of the drain region 1712, the concentration of the impurity element added when forming the impurity region 1709 is adjusted. Just do it.

  That is, the concentration profile of the impurity element is not necessarily limited to the shape shown in FIG. 17D, and the concentration profile may be determined by appropriately adjusting the impurity addition step according to the needs of the manufacturer.

  As described above, the configuration as shown in this embodiment is effective when the positions of the source region and the drain region are specified. For example, the source / drain like a semiconductor device for driving a pixel of a liquid crystal display device is used. Is not always effective when it reverses in response to charge and discharge. When used in a liquid crystal display device, it can be said that it should be used for applications where the source / drain is specified, such as an inverter circuit constituting a peripheral drive circuit.

  Further, in this embodiment, an example in which the shape of the impurity region has a linear pattern shape substantially parallel to the channel direction is shown, but it is easy to apply the configuration of this embodiment to the impurity region in the dot pattern shape. It is. Therefore, this example shows only an example, and other various possible examples are considered to be appropriately made according to the needs of the manufacturer.

  A feature of the present invention is that an impurity region is artificially and locally provided in the channel formation region. However, an impurity element (carbon, nitrogen, oxygen selected from one or more selected locally from the channel formation region) A plurality of types of elements) show an effective effect when using a low-oxygen silicon substrate subjected to hydrogen annealing.

As mentioned in the conventional example, a semiconductor device (excluding a thyristor) constituting a normal LSI circuit uses a silicon substrate formed by the CZ method, and a predetermined amount of oxygen is contained in the silicon substrate for stress relaxation. include. Recently, however, there has been an increasing demand for improving the breakdown voltage of oxide films and reducing minute defects, and there is a substrate in which the oxygen concentration in the surface layer of about 5 μm is lowered to 1 × 10 ¹⁷ atoms / cm ³ or less by annealing in a hydrogen atmosphere. Many are used.

  On the other hand, a silicon substrate that has been subjected to such a low oxygen treatment can cause the surface layer of the substrate to become very fragile to stress, which may cause cracks and warpage during the manufacturing process of the semiconductor device. There is.

  However, when a silicon substrate subjected to low oxygen treatment is used in the present invention, stress concentrates on the impurity region formed in the channel formation region. Therefore, the impurity region serves as a buffer region that relieves stress generated in the crystalline semiconductor. It has the function of.

  The effect of functioning as a buffer region for relaxing the stress is one of the remarkable effects of the impurity region in the present invention. This effect is particularly remarkable when oxygen is used as the impurity element.

  Therefore, the influence of stress generated during the manufacturing process when a semiconductor device is manufactured using a silicon substrate subjected to low oxygen treatment can be reduced, so that the manufacturing yield is greatly improved.

  Further, such a silicon substrate can be expected to have an effect of reducing the influence of carrier impurity scattering in addition to the effect of improving the oxide film breakdown voltage and the reduction of minute defects. That is, reducing oxygen means bringing the potential slit region closer to a more intrinsic or substantially intrinsic region, so that the carrier mobility can be extremely high.

  In this embodiment, an integrated circuit (included in the category of a semiconductor device in this specification) including a semiconductor device (semiconductor element) using the present invention will be described with some examples. 18 and 19 are used for the description.

  FIG. 18A shows an example in which the present invention is applied to a stacked CMOS circuit in which an N-channel FET and a P-channel FET are stacked in a two-story structure. In general, a P-channel FET is often formed on the lower layer side due to a problem in operation performance. In this embodiment, the lower layer side is a P-channel FET.

  In FIG. 18A, the lower layer is a P-channel FET formed by a normal IC technique, 1801 is an N-type silicon substrate, 1802 is a field oxide film, and 1803 and 1804 are a source region and a drain region, respectively. In this embodiment, low-concentration impurity regions (the drain region side is called an LDD region) 1805 and 1806 are provided.

  Reference numeral 1807 denotes a gate electrode made of conductive polysilicon, and an impurity region 1808, which is a feature of the present invention, is disposed immediately below the gate electrode. Note that in FIG. 18A, one end of the impurity region 1808 is inside the low concentration impurity region 1806 and the other end is inside the drain region 1804 beyond the LDD region 1805.

  On the upper layer, an N-channel FET is formed using SOI technology. A single-crystal silicon layer serving as an active layer of an N-channel FET can be obtained by using a known wafer bonding technique. Therefore, the interlayer insulating film 1809 is composed of a laminated film of an interlayer insulating film covering the lower FET and the thermal acid film of the wafer to be bonded, and includes a bonding surface (indicated by a dotted line).

  Then, a source region 1810, a channel formation region 1811, and a drain region 1812 are formed using a known TFT technique. Here, the low-concentration impurity regions 1813 and 1814 are arranged so as to sandwich the channel formation region 1811. Further, an impurity region 1815 according to the present invention is arranged for the channel formation region 1811.

  Further, an interlayer insulating film 1817 is formed to cover the gate electrode 1816, and wirings 1818, 1819, and 1820 are formed. Note that the wiring 1818 is a wiring common to the drain region 1804 of the P-channel FET and the drain region 1812 of the N-channel FET.

  The stacked CMOS circuit having the above-described structure shown in FIG. 18A can reduce the area occupied by the element, so that the degree of integration can be improved when configuring a VLSI or ULSI circuit.

  In addition, by applying the present invention, high-speed operability can be pursued without impairing the breakdown voltage, so that a CMOS circuit with excellent frequency characteristics can be configured.

  Next, FIG. 18B shows an example in which the present invention is applied to a Bi-CMOS circuit in which a CMOS circuit and a bipolar transistor are combined. Here, the lower layer is a bipolar transistor, and the upper layer is a CMOS circuit composed of a semiconductor device having an SOI structure.

In FIG. 18B, 1821 is a P-type silicon substrate, 1822 is a buried N ⁺ region, 1823 is a p-well formed by epitaxial growth, and the p-well on the buried N ⁺ region 1822 is doped N-type. The n-well 1824 functions as a collector. Reference numeral 1825 denotes a DeepN ⁺ region that serves as an extraction electrode from the buried N ⁺ region 1822. Reference numeral 1826 denotes a field oxide film formed by a normal selective oxidation method.

In the n-well 1824 constituting the bipolar transistor, a p ⁻ region 1827 serving as an active base is formed first, followed by a p ⁺ region 1828 serving as an external base and an n ⁺ region 1829 serving as an emitter region.

  Above the bipolar transistor having the above configuration, an SOI structure CMOS circuit is formed using a single crystal silicon layer obtained by a wafer bonding technique as an active layer. An interlayer insulating film indicated by 1830 includes a bonding surface (indicated by a dotted line). Here, the detailed description of the CMOS circuit has been sufficiently described in the first embodiment, and is omitted here.

  In FIG. 18B, the N-channel FET impurity region 1831 and the P-channel FET impurity region 1832 are arranged so as not to enter the source regions 1833 and 1834 but only into the drain regions 1835 and 1836.

  Then, the Bi-CMOS structure can be realized by connecting the upper layer CMOS circuit and the lower layer bipolar transistor by wirings 1837 and 1838.

  The Bi-CMOS circuit configured as described above has a circuit configuration for effectively combining the high-speed operation of the bipolar transistor and the low power consumption of the CMOS circuit. In addition, as in this embodiment, by adopting a three-dimensional structure in which a CMOS circuit and a bipolar transistor are stacked, the size of the occupied area, which has been a problem in the past, can be significantly reduced.

  Next, FIG. 19A shows an example in which the present invention is applied to a DRAM (Dynamic Rondom Access Memory) manufactured using SOI technology. DRAM is a type of memory that stores stored information in a capacitor as electric charge. The input / output of electric charge as information to the capacitor is controlled by a semiconductor device (field effect transistor) connected in series to the capacitor. Here, a stacked capacitor type DRAM will be described.

In FIG. 19A, reference numeral 1901 denotes a silicon substrate, and reference numeral 1902 denotes an insulating film that separates the silicon substrate 1901 from a capacitor storage electrode 1903 provided thereon. A capacitor electrode 1905 is provided above the capacitor storage electrode 1903 via an insulating film 1904 made of a high dielectric constant material. In this embodiment, Ta ₂ O ₅ is used as the insulating film 1904, but Si ₃ N ₄ or the like can also be used.

  With such a structure, a large-capacity capacitor is formed between the capacitor storage electrode 1903 and the capacitor electrode 1905. A feature of the stacked structure shown in FIG. 19A is that the lower layer is used as a region for completely accumulating capacitance. The charge accumulated in the capacitor is taken in and out by an IG-FET formed in the upper layer portion using the SOI technology.

  In this embodiment, an N-channel FET provided with an LDD region is used as a semiconductor device for controlling a data signal arranged in an upper layer. The single crystal silicon layer serving as the active layer is obtained using a wafer bonding technique, but a polysilicon (or amorphous silicon) recrystallization technique using a laser or an electron beam may be used. In addition, what is shown with the dotted line in a figure is the bonding interface of bonding.

  An active layer made of a single crystal silicon layer is composed of a source region 1906 and a drain region 1907, and an impurity region 1908 of the present invention is disposed in a channel formation region. Note that the impurity region 1908 is provided so as to penetrate the LDD region 1909 and enter the drain region 1907.

  The data signal transmitted through the bit line 1910 is transmitted to the drain electrode 1912 by controlling the voltage of the word line 1911. The signal is accumulated in a capacitor (capacitance) in the lower layer through a buried plug 1913 that connects the drain electrode 1912 in the upper layer and the capacitor electrode 1905 in the lower layer.

  A feature of DRAM is that it is suitable for constructing a large scale memory with high integration density because the number of elements constituting one memory is very small with only IG-FETs and capacitors. In addition, since the manufacturing cost can be kept low, it can be said that the circuit is currently used in a large amount.

  Next, an example in which an FET manufactured using the present invention is applied to an SRAM (Static Rondom Access Memory) will be described. FIG. 19B is used for the description.

  The SRAM is a memory using a bistable circuit such as a flip-flop as a storage element, and stores a binary information value (0 or 1) corresponding to the bi-stable state of ON-OFF or OFF-ON of the bistable circuit. To do. This is advantageous in that the memory is retained as long as power is supplied.

  The memory circuit is composed of an NMOS circuit or a CMOS circuit. The SRAM circuit shown in FIG. 19B is a cross-sectional view of a cell in which a CMOS circuit is combined. Note that the two FETs arranged in the lowermost layer are both P-channel FETs, and the two middle-layer FETs are both N-channel FETs. Therefore, the description will be basically focused on a CMOS circuit composed of upper and lower FETs on the right side in the drawing.

  In FIG. 19B, a source region 1915 and a drain region 1916 made of a P-type well are formed in an N-type silicon substrate 1914, and a gate electrode 1918 is disposed with a gate insulating film 1917 interposed therebetween. Elements arranged on the left and right sides in the drawing are separated by a field oxide film 1919.

  Reference numeral 1920 denotes an impurity region of the present invention. Here, the arrangement is such that only the drain region enters, and the source region does not enter the impurity region.

  The active layer of the middle N-channel FET is formed using a laser (or electron) beam recrystallization method which is one of SOI technologies. In this technique, polysilicon or amorphous silicon is formed on a planarized interlayer insulating film 1921, and is melted by a laser beam, an electron beam or the like and recrystallized.

  Of course, an SOI technique such as a wafer bonding technique may be used, but in this embodiment, the drain region 1922 of the middle N-channel FET is directly connected to the P-channel FET by using a recrystallization method. The drain region 1916 is connected.

  The active layer (single crystal silicon layer) obtained by the above means is provided with a source region 1923 and a drain region 1922 using a known TFT technique, and a gate electrode 1925 is disposed with a gate insulating film 1924 interposed therebetween. Immediately below the gate electrode 1925 (channel formation region), the impurity region 1926 of the present invention is provided so as to enter only the drain region 1922.

  The gate electrode 1925 of the N-channel FET is made of polysilicon with conductivity, and the connection wiring 1927 is formed of the same material at the same time as the gate electrode 1925 is formed. The connection wiring 1927 is a wiring for transmitting the output signal of the right CMOS circuit to the gate electrodes 1928 and 1929 of the left CMOS circuit. Note that in FIG. 19B, a dotted line indicates that the connection wiring 1927 and the gate electrodes 1928 and 1929 are electrically connected although not shown in the drawing.

  An N-channel FET functioning as a transfer gate is disposed on the uppermost layer. The active layer of this FET is a single crystal silicon layer obtained by using a wafer bonding technique. After the single crystal silicon layer is processed into an island shape, the source region 1930, the drain region 1931, and the impurity region 1932 of the present invention are formed to become an active layer.

  The drain region 1931 of the N-channel FET serving as the transfer gate is electrically connected to the connection wiring 1927 provided in the middle layer via the connection electrode 1933. A voltage is applied to the word line 1934 to transmit a data signal from the bit line 1935 to the CMOS circuit.

  The CMOS type SRAM configured as described above has advantages such as a wide operation margin and a very small data holding current, and is often used for low-voltage battery backup. In addition, the SRAM has features such that it can operate at high speed, has high reliability, and can be easily incorporated into a system.

  As described above, the semiconductor device such as the Bi-CMOS circuit and the SRAM circuit described in this embodiment can be miniaturized while preventing the short channel effect by applying the present invention. It is possible to pursue the breakdown voltage characteristics) and the high-speed operation characteristics at the same time. That is, it can be said that the present invention is a technique that exerts a tremendous effect in order to realize an ultra-highly integrated circuit with the system-on-chip concept that will be required in the future.

  In this embodiment, an example in which a semiconductor device using the present invention is incorporated in a product (electronic device) is shown. Here, an explanation will be given by taking an IC circuit incorporated in a notebook personal computer as an example. The description will be given with reference to FIG.

  In FIG. 20, reference numeral 3001 denotes a main body, 3002 denotes a lid portion, 3003 denotes a keyboard, and 3004 denotes an image display portion. Various integrated circuits 3005 are incorporated in the main body 3001.

  When the integrated circuit 3005 is taken out, the outside is covered with a package 3011 and the internal semiconductor chip is protected with resin or the like. Also, the internal semiconductor chip is connected to the outside by leads 3012. Normally, the integrated circuit (IC chip) 3005 to be seen is completely a black box because only the black package 3011 and the lead 3012 are visible to the outside eye.

  When the semiconductor chip protected by the package 3011 is taken out and viewed, for example, it has the following configuration. First, an arithmetic unit (processor) 3014 and a memory unit 3015 are arranged on the substrate 3013. Reference numeral 3016 denotes a bonding portion for connecting the semiconductor element and the lead 3012.

  The arithmetic unit 3014 and the memory unit 3015 are configured using various other circuits such as a CMOS circuit, a Bi-CMOS circuit, a DRAM circuit, and an SRAM circuit. The configuration as shown in FIG. 20 shown in this embodiment is characterized in that the arithmetic unit 3014 and the memory unit 3015 are arranged on the same substrate. This is a concept called system-on-chip (system IC).

  When the arithmetic unit 3014 and the memory unit 3015 are adjacent to each other as described above, data is exchanged between the arithmetic unit 3014 and the memory unit 3015 at a very high speed. It becomes possible to form.

  In addition, since all the necessary circuits can be integrated on one chip, it can be expected that the manufacturing cost is greatly reduced. Furthermore, it is possible to reduce the size of the product by reducing the arrangement area. As described in the seventh embodiment, since the SOI technology can constitute a three-dimensional integrated circuit, the degree of integration must be higher and higher in the future.

  In addition, if the present invention is used, the IG-FET and further the integrated circuit can be miniaturized without causing the short channel effect, so that the semiconductor device can be realized by realizing the one-chip structure as described above. It can be expected that applied electronic devices will be further miniaturized and portable.

  In this embodiment, an example of an electronic device incorporating an IG-FET to which the present invention is applied and an integrated circuit configured by combining the IG-FET is shown. As described above, in this specification, for convenience, it is described as an IG-FET, an integrated circuit, an electronic device, or the like. It shall be included in the category of “device”.

  Semiconductor devices (electronic devices) to which the present invention can be applied generally include all semiconductor devices that require an IC circuit. Therefore, the application range is very wide and includes devices used in most everyday situations.

  Specific examples include active electro-optical devices such as liquid crystal display devices, EL display devices, and CL display devices, TV cameras, personal computers, car navigation systems, TV projections, video cameras, and portable information terminal devices. The portable information terminal device includes a semiconductor device such as a mobile phone or a mobile (mobile) computer. A typical example of the semiconductor device as described above will be briefly described with reference to FIG.

  FIG. 21A illustrates a TV camera, which includes a main body 2001, a camera portion 2002, a display device 2003, and operation switches 2004. The present invention can be applied to the integrated circuit 2005 incorporated in the device.

  FIG. 21B illustrates car navigation, which includes a main body 2101, a display device 2102, operation buttons 2103, and an antenna 2104. The present invention can be applied to the integrated circuit 2105 incorporated in the device. Although the display device 2102 is used as a monitor, it can be said that the allowable range of resolution is relatively wide because the main purpose is to display a map.

  FIG. 21C illustrates a portable information terminal device (a mobile phone in this embodiment), which includes a main body 2301, an audio output unit 2302, an audio input unit 2303, a display device 2304, operation buttons 2305, and an antenna 2306. The present invention can be applied to an integrated circuit 2307 incorporated in the device.

  Since a mobile phone as shown in FIG. 21C is a semiconductor device that requires high-frequency operation, extremely high-speed operation characteristics are required. Therefore, by applying the present invention, an integrated circuit that operates at high speed without impairing the breakdown voltage can be incorporated.

  FIG. 21D illustrates a video camera, which includes a main body 2401, a display device 2402, an eyepiece 2403, operation buttons 2404, and a tape holder 2405. The present invention can be applied to the integrated circuit 2406 incorporated in the device. Since the photographed image displayed on the display device 2402 can be viewed in real time through the eyepiece 2403, the user can photograph while viewing the image.

  As described above, the application range of the present invention is extremely wide and can be applied to various semiconductor devices (including electronic devices) having a semiconductor integrated circuit.

  The electrical characteristics of the semiconductor device according to the present invention are very excellent, and an integrated circuit configured using this can achieve high frequency characteristics. In this embodiment, an example of the performance of a semiconductor device using the present invention will be shown.

  The device characteristics (current-voltage characteristics of the IG-FET) of the single semiconductor element formed using the present invention are very excellent, and the threshold voltage Vth, n of the N-channel FET is -0.3 to 3.0. The threshold voltage Vth, p of the V and P channel FETs can be adjusted in accordance with the required driving voltage in the range of -3.0 to 0.3 V (typically in the range of 0 to ± 0.3 V). Further, an extremely excellent sub-threshold characteristic is obtained with an S value of 60 to 85 mV / decade, in other words, 60 to 70 mV / decade.

Further, high mobility (1000 cm ² / Vs or more) can be obtained for the reason described in the first embodiment. When the mobility is obtained by a calculation formula, it should be noted that the mobility is inversely proportional to the channel width W. When the present invention is implemented, since the channel width is not less than narrow in the channel formation region due to the impurity region, actual mobility cannot be obtained unless the measured channel width Wpa is substituted.

  When an integrated circuit is constituted by the semiconductor device of the present invention capable of achieving the above excellent electrical characteristics, extremely good frequency characteristics can be obtained. For example, when a nine-stage ring oscillator is configured using the semiconductor device of the present invention, a frequency characteristic of 2 to 10 GHz can be realized with a driving voltage of 3.3 V.

  The present invention is also effective for electronic devices that require high frequency characteristics, such as mobile phones that are high-frequency electronic devices. An integrated circuit used for an input unit of a cellular phone requires a frequency characteristic of about 2 GHz (2.4 GHz) like an I / O circuit or a MUX / DMUX circuit. A high frequency integrated circuit can be sufficiently handled.

  In addition, since the present invention is applied to a semiconductor device having an SOI structure, it has an operating characteristic that is 10% or more faster than an integrated circuit manufactured on a conventional bulk silicon substrate, and is driven with power consumption of 70% or less. A possible integrated circuit can be configured.

The figure which shows the structure of a channel formation area | region. The figure which shows the structure of a channel formation area | region. FIG. 6 is a diagram for explaining a conventional semiconductor device. The figure which shows the energy state of a channel formation area | region. 4A and 4B are diagrams for explaining characteristics of a conventional semiconductor device. The figure which shows the energy state of a channel formation area | region. The figure which shows the manufacturing process of an insulated gate type field effect transistor. The figure which shows the manufacturing process of an insulated gate type field effect transistor. The figure for demonstrating the shape and arrangement | positioning of an impurity region. The figure which shows the structure of a channel formation area | region. The figure which shows the structure of a channel formation area | region. The figure which shows the energy state of a channel formation area | region. The figure for demonstrating the segregation state of an impurity. 10A and 10B illustrate a manufacturing process of an impurity region. The figure which shows the structure of a channel formation area | region. The figure which shows the structure of a channel formation area | region. The figure which shows the structure of a channel formation area | region. FIG. 9 illustrates a structure of a semiconductor device. FIG. 9 illustrates a structure of a semiconductor device. FIG. 9 illustrates a structure of a semiconductor device. FIG. 9 illustrates a structure of a semiconductor device.

Explanation of symbols

101 source region 102 drain region 103 channel forming region 104 impurity region 105 silicon substrate 106 buried oxide film

Claims (10)

Having a N-channel FET and a P-channel FET separated by a field oxide film on a single crystal substrate;
The N-channel FET and the P-channel FET include a source region, a drain region, and a channel formation region,
A gate electrode made of polysilicon provided on the channel forming region;
A sidewall made of silicon nitride provided only on the side surface of the gate electrode;
A gate insulating film made of a thermal oxide film, separated by the field oxide film and provided only under the gate electrode and the sidewall;
A first silicide provided on the surface of the source region and the surface of the drain region, having one end aligned with the field and the oxide film and the other end aligned with the sidewall;
A second silicide provided on the surface of the gate electrode, the end of which is aligned with the sidewall;
An interlayer insulating film made of silicon nitride that covers the gate electrode and is in contact with the first silicide and the second silicide;
A wiring provided in contact with the first silicide via a contact hole of the interlayer insulating film;
The channel forming region has a region in which a depletion layer extending from the drain region side to the channel forming region side is suppressed, and has a channel length of 0.01 to 0.35 μm. apparatus. Having a N-channel FET and a P-channel FET separated by a field oxide film on a single crystal substrate;
The N-channel FET and the P-channel FET include a source region, a drain region, and a channel formation region,
A gate electrode made of polysilicon provided on the channel forming region;
A sidewall made of silicon nitride provided only on the side surface of the gate electrode;
A gate insulating film made of a thermal oxide film, separated by the field oxide film and provided only under the gate electrode and the sidewall;
A first silicide provided on the surface of the source region and the surface of the drain region, having one end aligned with the field and the oxide film and the other end aligned with the sidewall;
A second silicide provided on the surface of the gate electrode, the end of which is aligned with the sidewall;
An interlayer insulating film made of silicon nitride that covers the gate electrode and is in contact with the first silicide and the second silicide;
A wiring provided in contact with the first silicide via a contact hole of the interlayer insulating film;
The insulated gate semiconductor device, wherein the channel formation region selectively includes an impurity element that forms a high energy barrier and has a channel length of 0.01 to 0.35 μm. Having a N-channel FET and a P-channel FET separated by a field oxide film on a single crystal substrate;
The N-channel FET and the P-channel FET include a source region, a drain region, and a channel formation region,
A gate electrode made of polysilicon provided on the channel forming region;
A sidewall made of silicon nitride provided only on the side surface of the gate electrode;
A gate insulating film made of a thermal oxide film, separated by the field oxide film and provided only under the gate electrode and the sidewall;
A first silicide provided on the surface of the source region and the surface of the drain region, having one end aligned with the field and the oxide film and the other end aligned with the sidewall;
A second silicide provided on the surface of the gate electrode, the end of which is aligned with the sidewall;
An interlayer insulating film made of silicon nitride that covers the gate electrode and is in contact with the first silicide and the second silicide;
A wiring provided in contact with the first silicide via a contact hole of the interlayer insulating film;
The channel formation region has an impurity element which forms a high energy barrier in a region other than the end portion, and has a channel length of 0.01 to 0.35 μm. In claim 2 or claim 3,
The N-channel FET or the P-channel FET has an LDD region,
The insulated gate semiconductor device according to claim 1, wherein the impurity element in the channel formation region is in the LDD region. In claim 2 or claim 3,
The N-channel FET or the P-channel FET has an LDD region,
The insulated gate semiconductor device according to claim 1, wherein the impurity element in the channel formation region is in the drain region beyond the LDD region. In any one of Claims 2 thru | or 4,
An insulating gate type semiconductor device, wherein the impurity element in the channel formation region is provided in a dot pattern shape in the channel formation region. In any one of Claims 2 thru | or 4,
2. The insulated gate semiconductor device according to claim 1, wherein the impurity element in the channel formation region is provided in a linear pattern shape in the channel formation region. In any one of Claims 2 thru | or 4,
2. The insulated gate semiconductor device according to claim 1, wherein the impurity element in the channel formation region is provided in a fishbone shape in the channel formation region. Having a N-channel FET and a P-channel FET separated by a field oxide film on a single crystal substrate;
The N-channel FET and the P-channel FET include a source region, a drain region, and a channel formation region,
A gate electrode made of polysilicon provided on the channel forming region;
A sidewall made of silicon nitride provided only on the side surface of the gate electrode;
A gate insulating film made of a thermal oxide film, separated by the field oxide film and provided only under the gate electrode and the sidewall;
A first silicide provided on the surface of the source region and the surface of the drain region, having one end aligned with the field and the oxide film and the other end aligned with the sidewall;
A second silicide provided on the surface of the gate electrode, the end of which is aligned with the sidewall;
An interlayer insulating film made of silicon nitride that covers the gate electrode and is in contact with the first silicide and the second silicide;
A wiring provided in contact with the first silicide via a contact hole of the interlayer insulating film;
The channel forming region has a potential slit region and has a channel length of 0.01 to 0.35 μm. In claim 9,
2. The insulated gate semiconductor device according to claim 1, wherein the potential slit region has a width of 30 to 3000 mm.

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