JP2008089536A - Connection inspection apparatus for integrated circuit device - Google Patents

Connection inspection apparatus for integrated circuit device Download PDF

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JP2008089536A
JP2008089536A JP2006273723A JP2006273723A JP2008089536A JP 2008089536 A JP2008089536 A JP 2008089536A JP 2006273723 A JP2006273723 A JP 2006273723A JP 2006273723 A JP2006273723 A JP 2006273723A JP 2008089536 A JP2008089536 A JP 2008089536A
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integrated circuit
test wave
circuit device
connection
inspected
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Masao Kanetani
雅夫 金谷
Mutsumi Shimazaki
睦 島嵜
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To construct a connection inspection apparatus for integrated circuit devices capable of checking the quality of coupling sections of integrated circuit devices with a high degree of accuracy in a short time. <P>SOLUTION: The connection inspection apparatus for integrated circuit devices is constructed of a multipoint probe equipped with a test wave application circuit, where a plurality of probe pins contacting a plurality of contacting parts of an inspected integrated circuit device, respectively, are implanted in an insulating plate, connected to a test wave application terminal applying test wave through switching elements for each probe pin, a switching control means outputting switch signal selectively for each one element to switching elements of the test wave application circuit to form the test wave application circuit, a test wave application means applying test wave to the test wave application circuit formed by the switching control means, and a connectedness diagnostic means observing the applied test wave and the reflected wave reflected from the inspected integrated circuit device to diagnose connectedness of the inspected integrated circuit device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、例えばBGAIC等の集積回路が実装基板に実装された集積回路装置の接続状態を検査する集積回路装置の接続検査装置に関すものである。   The present invention relates to a connection inspection device for an integrated circuit device that inspects a connection state of an integrated circuit device in which an integrated circuit such as a BGAIC is mounted on a mounting substrate.

BGAパッケージやSOJパッケージのような集積回路装置は実装された実装基板下面に端子を有し、この端子と実装基板の間は半田ボールにより接続されている。その接続部はパッケージと実装基板との間に隠れた状態となっており目視検査ができない状態であるので、接続部の検査は、接続部の上部にX線発生源を置き、下部に画像検査部を配置してX線を照射し、画像検出部の検出信号に所定の信号処理を施し、これを画像化することで接続状態を検査する方法や、半導体接続部の上部にレーザー光源を配置し、このレーザ光源から半導体接続部にレーザ光を照射し、反射したレーザ光をCCDカメラで検出し、半田フィレットの形状で接続状態の良否を識別する方法が多く用いられている。   An integrated circuit device such as a BGA package or an SOJ package has terminals on the lower surface of the mounted mounting board, and the terminals and the mounting board are connected by solder balls. Since the connection part is hidden between the package and the mounting board and cannot be visually inspected, the connection part is inspected by placing an X-ray generation source on the upper part of the connection part and image inspection on the lower part. A part is placed and irradiated with X-rays, a predetermined signal processing is applied to the detection signal of the image detection part, and this is imaged, and a laser light source is placed above the semiconductor connection part In many cases, a laser beam is irradiated from the laser light source to the semiconductor connection portion, the reflected laser beam is detected by a CCD camera, and the quality of the connection state is identified by the shape of the solder fillet.

また、特許文献1には、半導体装置の接続部に超音波パルスを印加し、その反射状態を観測することにより、接続部の不接続状態を検出する方法が示されている。   Patent Document 1 discloses a method for detecting a non-connection state of a connection part by applying an ultrasonic pulse to a connection part of a semiconductor device and observing the reflection state thereof.

また、特許文献2には、高周波パルス波をプローブを介して基板のランドに印加し、入力パルス波と反射パルス波を計測し、波形を分析することで半田部の接続状態の良否を識別する方法が示されている。その方法におけるプローブと基板のランドへの接続は、X−Y駆動手段により移動して順次検査対象のランドに接続して入力パルスを入力し、入力パルスと反射波を観測して接続状態を検査する検査装置が示されている。   In Patent Document 2, a high-frequency pulse wave is applied to a land of a substrate via a probe, an input pulse wave and a reflected pulse wave are measured, and the waveform is analyzed to identify whether the connection state of the solder part is good or bad. The method is shown. In this method, the probe is connected to the land of the substrate by the XY drive means, sequentially connected to the land to be inspected, input pulses are input, the input pulse and the reflected wave are observed, and the connection state is inspected. The inspection device to be shown is shown.

特開平03−084453号公報Japanese Patent Laid-Open No. 03-084453 特開平09−061486号公報JP 09-061486 A

接続部にX線を照射して画像検出部の検出信号に所定の信号処理を施してこれを画像化することにより検査する方法では、確認したい部分が微小あり明瞭な画像を表示することが難しく、接続状態の詳細な確認ができないという問題点があった。
また、特許文献1に示された検査方法では、超音波パルスを印加し、多数の接続部を有する場合には接続部毎に順次検査することになり、検査時間が長時間となり、量産品に適用することは難かしいという問題点がある。
また、特許文献2の場合では、高周波パルス波をプローブを介して基板のランドに印加し、入力パルス波と反射パルス波を計測し、波形を分析することで接続部の良否を判定するものであり、プローブはX−Y駆動手段により移動して順次検査対象のランドに接続するが接続部を移動する移動時間が必要であり検査時間が長くなる問題点があった。
In the inspection method by irradiating the connection portion with X-rays and applying predetermined signal processing to the detection signal of the image detection portion and imaging it, it is difficult to display a clear image with a minute portion to be confirmed. There was a problem that the connection status could not be confirmed in detail.
In addition, in the inspection method disclosed in Patent Document 1, when an ultrasonic pulse is applied and there are a large number of connection portions, the inspection is sequentially performed for each connection portion, and the inspection time becomes long, and the product is mass-produced. There is a problem that it is difficult to apply.
In the case of Patent Document 2, a high-frequency pulse wave is applied to a land of a substrate through a probe, an input pulse wave and a reflected pulse wave are measured, and the waveform is analyzed to determine whether the connection part is good or bad. There is a problem that the probe is moved by the XY driving means and sequentially connected to the land to be inspected, but the moving time for moving the connecting portion is necessary, and the inspection time becomes long.

この発明は、上記問題点を解決するためになされたものであり、集積回路装置の多数の接続点の良否が精度よく短時間で検査できる集積回路装置の接続検査装置を提供することを目的とする。   The present invention has been made to solve the above-described problems, and an object thereof is to provide a connection inspection device for an integrated circuit device capable of accurately and quickly inspecting the quality of many connection points of the integrated circuit device. To do.

この発明に係る集積回路装置の接続検査装置は、被検査集積回路装置の複数の接触部にそれぞれ接触する複数のプローブピンが絶縁板に植設され、プローブピン毎にスイッチング素子を介して試験波を印加する試験波印加端子に接続される試験波印加回路を備えた多点プローブと、試験波印加回路のスイッチング素子に対して1素子毎に選択的に開閉信号を出力して試験波印加回路を形成する切換制御手段と、この切換制御手段により形成された試験波印加回路に試験波を印加する試験波印加手段と、印加された試験波と被検査集積回路装置から反射した反射波を観測して被検査集積回路装置の接続状態を診断する接続状態診断手段とを備えたものである。   In the integrated circuit device connection inspection device according to the present invention, a plurality of probe pins respectively contacting a plurality of contact portions of the integrated circuit device to be inspected are implanted in an insulating plate, and a test wave is connected to each probe pin via a switching element. A test wave applying circuit that selectively outputs an open / close signal for each element to a switching element of the test wave applying circuit and a multipoint probe connected to a test wave applying circuit connected to a test wave applying terminal A switching control means for forming a test wave, a test wave applying means for applying a test wave to a test wave applying circuit formed by the switching control means, and an observation of the applied test wave and a reflected wave reflected from the integrated circuit device to be inspected And connection state diagnosis means for diagnosing the connection state of the integrated circuit device to be inspected.

このように構成すると、外部から目視できない多数の接続部を備えた集積回路装置の接続部が非破壊で精度よく効率的に検査できる検査装置となる。   If comprised in this way, it will become an inspection apparatus which can test | inspect accurately and efficiently the non-destructive connection part of the integrated circuit device provided with many connection parts which cannot be visually recognized from the outside.

実施の形態1.
BGA(ball grid array)パッケージやSOJ(small outline j lead)パッケージの集積回路装置で、例えばBGAICが実装基板に実装されたBGAパッケージでは図1、図2のように構成されている。
図1(a)はBGAパッケージの集積回路装置の断面図であり、図1(b)は図1(a)の部分拡大図である。図2は実装基板のIC実装面とその反対面の接続側の状態を示す図であり、図2(a)はIC実装面のランド及びスルーホールの配置状態、図2(b)は図2(a)の反対の接続面の状態を示す図である。
Embodiment 1 FIG.
An integrated circuit device of a BGA (ball grid array) package or a SOJ (small outline j lead) package, for example, a BGA package in which a BGAIC is mounted on a mounting substrate, is configured as shown in FIGS.
FIG. 1A is a cross-sectional view of an integrated circuit device of a BGA package, and FIG. 1B is a partially enlarged view of FIG. FIG. 2 is a diagram showing a state of the connection side of the IC mounting surface of the mounting substrate and the opposite surface, FIG. 2A is an arrangement state of lands and through holes on the IC mounting surface, and FIG. It is a figure which shows the state of the connection surface opposite to (a).

図1に示した集積回路装置10のIC11は、実装基板側に規則的に整列した複数の接続部12を備え、実装基板21の実装側は、図2(a)に示すように、IC11の接続部12に対向する位置に半田ボール15を介して接続するランド22と、各ランド22のそれぞれから反対面に貫通するスルーホール23が設けられ、反対の接続面には外部に接続する接続ランド24が規則的に配列され、ランド22と接続ランド24はスルーホール23に導体を貫通させて接続している。
IC11の接続部12と実装基板21のランド22の間にそれぞれ半田ボール15を配置して加熱ずることでIC11と実装基板21を一体として集積回路装置10が構成されている。
The IC 11 of the integrated circuit device 10 shown in FIG. 1 includes a plurality of connecting portions 12 regularly arranged on the mounting board side, and the mounting side of the mounting board 21 is connected to the IC 11 as shown in FIG. A land 22 connected via a solder ball 15 is provided at a position facing the connection portion 12, and a through hole 23 penetrating from each land 22 to the opposite surface is provided, and a connection land connected to the outside is provided on the opposite connection surface. 24 are regularly arranged, and the land 22 and the connection land 24 are connected to the through hole 23 through a conductor.
The integrated circuit device 10 is configured by integrating the IC 11 and the mounting substrate 21 by disposing and heating the solder balls 15 between the connection portion 12 of the IC 11 and the land 22 of the mounting substrate 21.

図3は集積回路装置の接続検査装置の構成図、図4はプローブピン部分の拡大図、図5は多点プローブ30の構成説明図である。
集積回路装置の接続検査装置は、集積回路装置10の複数の接続部に同時に接触させ、接触部毎にスイッチイング素子を設けて開閉信号により検査する接続部の試験波印加回路を形成する多点プローブ30と、検査する接触部への試験波印加回路を順次形成する切換制御手段51、試験波印加手段52、接続状態診断手段53、記憶手段53、表示手段54を備えた構成としている。
3 is a configuration diagram of a connection inspection device for an integrated circuit device, FIG. 4 is an enlarged view of a probe pin portion, and FIG.
The integrated circuit device connection inspection device simultaneously contacts a plurality of connection portions of the integrated circuit device 10, and provides a switching element at each contact portion to form a test wave application circuit for a connection portion that is inspected by an open / close signal. The probe 30 and a switching control means 51 for sequentially forming a test wave application circuit to a contact portion to be inspected, a test wave application means 52, a connection state diagnosis means 53, a storage means 53, and a display means 54 are provided.

多点プローブ30は、絶縁板32に集積回路装置10の複数の接触部24に同時に接触するように、絶縁板32に集積回路装置10の接続部24の配置間隔に合わせてプローブピン穴33を孔設し、プローブピン35を植設したプローブ板31と、プローブ板31の全てのプローブピン35が接触し途中にスイッチング素子43を設けて試験波印加端子45に接続される試験波印加回路42を設け、各スイッチング素子43の開閉制御を行う制御線44は、切換制御手段51に接続されるように配線したインターフェース基板41とで構成している。   In the multipoint probe 30, probe pin holes 33 are formed in the insulating plate 32 in accordance with the arrangement interval of the connecting portions 24 of the integrated circuit device 10 so that the insulating plate 32 contacts the plurality of contact portions 24 of the integrated circuit device 10 simultaneously. A probe plate 31 in which holes are provided and the probe pins 35 are implanted, and a test wave application circuit 42 in which all the probe pins 35 of the probe plate 31 are in contact with each other and a switching element 43 is provided in the middle and connected to the test wave application terminal 45. The control line 44 for controlling the opening / closing of each switching element 43 is constituted by an interface substrate 41 wired so as to be connected to the switching control means 51.

プローブピン35は図4に示すように、円筒部材35aの内径中央部に押しばね35bを配置し、両端部に接触子35cおよび接触子35dを挿入して軸方向に移動可能に係止した構成である。
このように構成すると、プローブピン35は、集積回路装置10の接触部24に多少の凹凸があっても、スプリング35bによって集積回路装置10接触部24およびインターフェース基板41の試験波印加回路42に常時押圧されて確実な接触状態が確保される。
As shown in FIG. 4, the probe pin 35 has a configuration in which a pressing spring 35b is arranged at the center of the inner diameter of the cylindrical member 35a, and a contact 35c and a contact 35d are inserted at both ends so as to be movable in the axial direction. It is.
With this configuration, the probe pin 35 is always applied to the integrated circuit device 10 contact portion 24 and the test wave application circuit 42 of the interface substrate 41 by the spring 35b even if the contact portion 24 of the integrated circuit device 10 has some unevenness. It is pressed and a reliable contact state is ensured.

集積回路装置10の接触部24はランド22との間が導体を挿通して半田付けにより接続されているので、若干の凹凸があり確実に接触させるために図4に示すように王冠形(クラウンタイプ)に形成している。このように王冠形に形成すると接触点が2点あるので確実に接触させることができる。   Since the contact portion 24 of the integrated circuit device 10 is connected to the land 22 by soldering through a conductor, there is a slight unevenness and a crown shape (crown) as shown in FIG. Type). Thus, when it forms in a crown shape, since there are two contact points, it can be made to contact reliably.

切換制御手段51は、集積回路装置の検査を行う接続部に対して、試験波を印加する各接続部を選択して試験波印加回路42を形成するようにスイッチング素子43に対して開閉信号を伝送し、接続部が順次切り換えられるように構成されている。   The switching control means 51 sends an open / close signal to the switching element 43 so as to form a test wave application circuit 42 by selecting each connection part to which the test wave is applied to the connection part for inspecting the integrated circuit device. The transmission is configured so that the connection unit is sequentially switched.

試験波印加手段52は、集積回路装置10の接続部24に対して印加する高周波パルスを発生するパルス発生回路を備え、切換制御手段51の切換信号に同期して動作するように構成されている。   The test wave application unit 52 includes a pulse generation circuit that generates a high-frequency pulse to be applied to the connection unit 24 of the integrated circuit device 10, and is configured to operate in synchronization with the switching signal of the switching control unit 51. .

接続状態診断手段53は、試験波印加手段52から印加された高周波パルスの印加波と集積回路装置10からの反射波を観測し、印加波と反射波の時間間隔から反射点の距離を算出し、反射点の距離が算出された場合に不具合と判定され、算出された距離によって不具合の位置を特定することができる。
接続状態診断手段53の波形観測装置としては、時間領域反射測定装置(TDR:Time Domain Reflectometer) を使用することにより、集積回路装置10の不接続箇所が容易に検出できる。
The connection state diagnosis unit 53 observes the applied wave of the high-frequency pulse applied from the test wave applying unit 52 and the reflected wave from the integrated circuit device 10, and calculates the distance of the reflection point from the time interval between the applied wave and the reflected wave. When the distance of the reflection point is calculated, it is determined as a defect, and the position of the defect can be specified by the calculated distance.
By using a time domain reflectometer (TDR: Time Domain Reflectometer) as the waveform observation device of the connection state diagnosis means 53, the unconnected portion of the integrated circuit device 10 can be easily detected.

例えば、図6に示すように、集積回路装置10の半田ボール15の部分に半田割れ(クラック)があった場合の印加波と反射波の観測波形の例を図7に示す。
図7の(a)が印加波形であり、図7の(b)が接続状態診断手段53での観測波形を示す。観測波形(b)の印加時刻t0に対して、反射波が戻ってくる時刻trで電圧が階段状に上昇する波形となる。印加時刻t0と反射波観測時刻trとの間の時間Tから断線部分の位置が算出される。断線部分の位置が半田ボールの位置であれば、半田ボールの接続不具合と判定される。
For example, as shown in FIG. 6, examples of observed waveforms of applied waves and reflected waves when there is a solder crack (crack) in the solder ball 15 portion of the integrated circuit device 10 are shown in FIG.
FIG. 7A shows the applied waveform, and FIG. 7B shows the waveform observed by the connection state diagnosis means 53. With respect to the application time t0 of the observed waveform (b), the voltage rises stepwise at the time tr when the reflected wave returns. The position of the disconnection portion is calculated from the time T between the application time t0 and the reflected wave observation time tr. If the position of the disconnected portion is the position of the solder ball, it is determined that the solder ball has a connection failure.

記憶手段54は、接続状態診断手段53の診断結果をディジタル通信手段により伝送し、検査位置に対応して記憶する。記憶手段53は検査装置に装備してもよく、別の場所に配置してもよい。   The storage means 54 transmits the diagnosis result of the connection state diagnosis means 53 by the digital communication means and stores it corresponding to the inspection position. The storage means 53 may be installed in the inspection apparatus or may be arranged at another location.

表示手段55は、記憶手段54に記憶された各接続部の診断結果を接続部に対応して表示することができるように構成している。   The display unit 55 is configured to display the diagnosis result of each connection unit stored in the storage unit 54 corresponding to the connection unit.

このように構成された集積回路装置の接続検査装置を用いて集積回路装置10の接続部を検査するときは、多点プローブ30に被検査集積回路装置10を装着し、切換制御手段51により検査する接続部の試験波印加回路を形成し、試験波印加手段52により試験波を印加し、接続状態診断手段53により試験波の印加波形と反射波の波形が観測された場合に、印加時刻と反射波の検出時刻との差により反射点までの距離を算出し、算出した距離が断線位置となり、断線位置が半田付け位置の場合は半田付けの不具合となり、距離が集積回路装置内部の場合には集積回路内部の不具合と判定することができる。
このような動作を接続部毎に繰り返すことで外部から目視できない多数の接続部を備えた集積回路装置の接続部が非破壊で精度よく効率的に検査できる。
When the connection portion of the integrated circuit device 10 is inspected using the connection inspection device of the integrated circuit device configured as described above, the integrated circuit device 10 to be inspected is mounted on the multipoint probe 30 and inspected by the switching control means 51. A test wave application circuit for the connecting portion to be formed, a test wave is applied by the test wave application means 52, and when the application waveform of the test wave and the waveform of the reflected wave are observed by the connection state diagnosis means 53, the application time and The distance to the reflection point is calculated based on the difference from the detection time of the reflected wave, and the calculated distance becomes the disconnection position. If the disconnection position is the soldering position, it becomes a soldering defect. If the distance is inside the integrated circuit device, Can be determined as a malfunction in the integrated circuit.
By repeating such an operation for each connection portion, the connection portion of the integrated circuit device having a large number of connection portions that cannot be visually recognized from the outside can be inspected accurately and efficiently without destruction.

集積回路装置の構成を示す断面図である。It is sectional drawing which shows the structure of an integrated circuit device. 集積回路装置の実装基板のIC実装面とその反対面の接続側の状態を示す図である。It is a figure which shows the state of the connection side of the IC mounting surface of the mounting substrate of an integrated circuit device, and its opposite surface. 集積回路装置の接続検査装置の構成図である。It is a block diagram of the connection inspection apparatus of an integrated circuit device. 図3のプローブピン部分の拡大図である。It is an enlarged view of the probe pin part of FIG. 多点プローブの構成説明図である。It is a structure explanatory view of a multipoint probe. 集積回路装置の接続部の半田ボール部分に半田割れがあ留場合の説明図である。It is explanatory drawing when a solder crack remains in the solder ball part of the connection part of an integrated circuit device. 観測波形の説明図である。It is explanatory drawing of an observation waveform.

符号の説明Explanation of symbols

10 集積回路装置、11 集積回路、12 接続部、15 半田ボール、
21 実装基板、22 ランド、23 スルーホール、24 接続ランド、
30 多点プローブ、31 プローブ板、32 絶縁板、35 プローブピン、
41 インターフェース基板、42 試験波印加回路、43 スイッチング素子、
44 スイッチング素子制御回路、45 試験波印加端子、51 切換制御手段、
52 試験波印加手段、53 接続状態診断手段、54 記憶手段、55 表示手段。
DESCRIPTION OF SYMBOLS 10 Integrated circuit device, 11 Integrated circuit, 12 Connection part, 15 Solder ball,
21 mounting board, 22 lands, 23 through holes, 24 connection lands,
30 multipoint probe, 31 probe plate, 32 insulation plate, 35 probe pin,
41 interface board, 42 test wave application circuit, 43 switching element,
44 switching element control circuit, 45 test wave application terminal, 51 switching control means,
52 test wave application means, 53 connection state diagnosis means, 54 storage means, 55 display means.

Claims (5)

被検査集積回路装置の複数の接触部にそれぞれ接触する複数のプローブピンが絶縁板に植設され、プローブピン毎にスイッチング素子を介して試験波を印加する試験波印加端子に接続される試験波印加回路を備えた多点プローブと、上記試験波印加回路のスイッチング素子に対して1素子毎に選択的に開閉信号を出力して試験波印加回路を形成する切換制御手段と、該切換制御手段により形成された試験波印加回路に試験波を印加する試験波印加手段と、印加された試験波と上記被検査集積回路装置から反射した反射波を観測して上記被検査集積回路装置の接続状態を診断する接続状態診断手段とを備えたことを特徴とする集積回路装置の接続検査装置。 A plurality of probe pins that are in contact with a plurality of contact portions of the integrated circuit device to be inspected are implanted in an insulating plate and connected to a test wave application terminal that applies a test wave to each probe pin via a switching element. A multipoint probe having an application circuit; a switching control means for selectively outputting an opening / closing signal for each switching element of the test wave application circuit to form a test wave application circuit; and the switching control means A test wave applying means for applying a test wave to the test wave applying circuit formed by the method, and a connection state of the integrated circuit device to be inspected by observing the applied test wave and a reflected wave reflected from the integrated circuit device to be inspected. And a connection state diagnosis means for diagnosing the connection. 上記接続状態診断手段が診断した診断結果を検査位置毎に記憶する記憶手段と、記憶された上記診断結果を表示する表示手段とを付加したことを特徴とする請求項1記載の集積回路装置の接続検査装置。 2. The integrated circuit device according to claim 1, further comprising storage means for storing a diagnosis result diagnosed by the connection state diagnosis means for each inspection position and a display means for displaying the stored diagnosis result. Connection inspection device. 上記プローブピンは、円筒状部材の内径中央部に押圧ばねを配置し、両端部に接触子を挿入して軸方向に移動可能に係止したことを特徴とする請求項1または請求項2記載の集積回路装置の接続検査装置。 3. The probe pin according to claim 1, wherein a pressing spring is disposed at a central portion of the inner diameter of the cylindrical member, and contacts are inserted into both ends so as to be movable in the axial direction. Integrated circuit device connection inspection device. 上記プローブピンの上記被検査集積回路装置側に接触する接触子の先端は王冠形状に形成されていることを特徴とする請求項1〜請求項3のいずれかに記載の集積回路装置の接続検査装置。 4. The connection inspection of an integrated circuit device according to claim 1, wherein the tip of the contact that contacts the inspected integrated circuit device side of the probe pin is formed in a crown shape. apparatus. 上記接続状態診断手段は、時間領域反射測定装置としたことを特徴とする請求項1〜請求項4のいずれかに記載の集積回路装置の接続検査装置。 5. The integrated circuit device connection inspection device according to claim 1, wherein the connection state diagnosis means is a time domain reflection measurement device.
JP2006273723A 2006-10-05 2006-10-05 Connection inspection apparatus for integrated circuit device Pending JP2008089536A (en)

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JP2009294101A (en) * 2008-06-05 2009-12-17 Mitsubishi Electric Corp Apparatus and method of inspecting printed board
JP2010107365A (en) * 2008-10-30 2010-05-13 Mitsubishi Electric Corp Inspection device for substrate connection
JP2010261769A (en) * 2009-05-01 2010-11-18 Mitsubishi Electric Corp Apparatus and method of inspecting printed circuit board
JP2011100763A (en) * 2009-11-04 2011-05-19 Nec Computertechno Ltd Semiconductor package, semiconductor module and method of inspecting semiconductor module
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JP2012053010A (en) * 2010-09-03 2012-03-15 Mitsubishi Electric Corp Tdr type testing apparatus
CN102788928A (en) * 2012-08-25 2012-11-21 桐城信邦电子有限公司 Automatic inspecting machine for returning and inserting pins of electric connectors
JP2013181990A (en) * 2013-03-26 2013-09-12 Toshiba Corp Fault detection device

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JP2009294101A (en) * 2008-06-05 2009-12-17 Mitsubishi Electric Corp Apparatus and method of inspecting printed board
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JP2013181990A (en) * 2013-03-26 2013-09-12 Toshiba Corp Fault detection device

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