JP2008072257A - Phase locked oscillator and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a highly stable VCO output constantly through simple arrangement and control regardless of variation in characteristics or temperature of the VCO circuit. <P>SOLUTION: The phase locked oscillator has a PLL loop consisting of a phase comparator, a low-pass filter, a main control section, a VCO circuit being driven with a control voltage outputted from the main control section, and a variable frequency divider for dividing the frequency of that output. The control section locks the PLL loop with a plurality of frequencies and measures the control voltage at each locking time, determines a modulation sensitivity of the VCO circuit subjected to linearity calibration based on each control voltage thus measured, and under a state where the PLL loop is opened after being locked with a predetermined frequency, creates a control voltage for generating a frequency variation subjected to linearity correction centering on the predetermined frequency in the VCO circuit based on the modulation sensitivity thus obtained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a phase-locked oscillator and a control method thereof, and more particularly to a phase-locked oscillator suitable for use in an RF band oscillator such as an FM-CW radar and a control method thereof.

  FIG. 20 is a diagram for explaining the prior art, and FIG. 20A shows a frequency modulation portion of a conventional FM-CW radar. The basic configuration of the FM-CW system is to generate a triangular wave modulation signal with a function generator (FG) or the like, and to apply frequency modulation to the voltage controlled oscillator (VCO) with this modulation signal. What is important in the FM-CW system is to apply accurate triangular wave frequency modulation. For this purpose, for example, the maximum and minimum frequency deviations do not change with respect to the center frequency, and the frequency is time-dependent. In addition, it is necessary to change linearly and the inclination (frequency change rate) does not change. The output frequency of the FM-CW radar depends on the stability of the external conditions (temperature, power supply, etc.) of the VCO, and the frequency shift of the output frequency depends on the modulation sensitivity of the VCO and the output frequency. A new VCO is required. Also, in order for the frequency to increase linearly, good linearity of the VCO is required.

  FIG. 20B shows a typical configuration of a conventional FM-CW radar transmitter. For the temperature change of the oscillation frequency, the CPU refers to the data table based on the temperature detected by the temperature sensor and corrects the center voltage of the triangular wave. For the linearity of the oscillation frequency, the CPU similarly corrects the triangular wave voltage by referring to the data table.

  FIG. 20C is a diagram illustrating another configuration example of the conventional FM-CW radar transmission unit, and illustrates a method of superimposing a triangular wave on a PLL (Phase Locked Loop) circuit. In this method, the center frequency is stabilized by synchronizing the phase of the PLL with the center frequency. On the other hand, for the linearity of the frequency shift applied to the center frequency, the CPU corrects the triangular wave voltage by referring to the data table.

Conventionally, the oscillation frequency is stabilized by using a triangular wave that is phase-synchronized with the crystal oscillator 6a as a modulation signal, and control is performed so as not to exceed the upper and lower limits of the frequency deviation by detecting the frequency of the output RF signal. An oscillation circuit that performs the above is known (Patent Document 1).
JP-A-6-120735

  However, if the above-mentioned data table is used to correct the temperature change and linearity of the oscillation frequency, it is not only necessary to have a separate large data table, but also individual data for each device depending on circuit element variations. It is necessary to create a table, which greatly increases the number of test steps. In the configuration shown in FIG. 20C, feedback from the PLL is applied to the VCO output modulated by the triangular wave, so that the modulation characteristic of the VCO output is deteriorated. Further, it is assumed that the modulation characteristic of the VCO in Patent Document 1 is linear. If it is not linear, it is necessary to perform linearity correction using a data table or the like.

  The present invention has been made in view of the above-described problems of the prior art, and the object of the present invention is to always obtain a highly stable VCO output with a simple configuration and control irrespective of variations in characteristics of the VCO circuit and temperature fluctuations. A phase-locked oscillator and a control method thereof are provided.

  A phase-locked oscillator according to the first aspect of the present invention (VCO calibration) includes a phase comparator that compares the phases of a reference signal and a comparison signal, a low-pass filter that integrates a phase error signal of the phase comparator, and the low-pass filter. A control unit that performs the main control of this device interposed in the subsequent stage of the filter, a VCO circuit that generates a signal having a frequency corresponding to the control voltage of the control unit output, and divides the output signal of the VCO circuit to A phase-locked oscillator including a PLL loop including a variable frequency divider that forms a comparison signal, wherein the control unit locks the PLL loop at a plurality of frequencies and measures a control voltage at each lock. And linearity calibration means for obtaining a modulation sensitivity representing a frequency change in a section connecting the frequencies based on the measured control voltages.

  According to the present invention, the configuration in which the PLL loop is locked at a plurality of frequencies makes it possible to easily and accurately control the voltage for causing the VCO to oscillate at the required frequency even if the modulation sensitivity of the VCO varies or depends on temperature. can get.

  The phase-locked oscillator according to the second aspect of the present invention (VCO drive) locks the PLL loop at a predetermined frequency, and then opens the PLL loop in a state where the PLL circuit is opened based on the obtained modulation sensitivity. VCO driving means for generating and outputting a voltage signal for generating a linearity-corrected frequency change centered on a predetermined frequency is further provided.

  According to the present invention, the configuration in which the VCO circuit is driven by a voltage signal that has been linearly calibrated can always provide stable oscillation characteristics regardless of variations in the characteristics of the VCO circuit and temperature fluctuations.

  In the third aspect (intermittent PLL control) of the present invention, the VCO driving means samples the output of the low-pass filter in synchronization with the timing at which the VCO circuit outputs the center frequency, and the detected phase error signal is within a predetermined range. In the case of exceeding the control voltage, the control voltage is offset in the direction of decreasing the phase error signal. Therefore, the center frequency can be kept constant by intermittent PLL control.

  A phase-locked oscillator according to a fourth aspect (intermittent FLL control) of the present invention is a first frequency divider that divides a reference signal and a first output that divides the output of a VCO circuit to form the comparison signal. The VCO driving means periodically resets the counters of the first and second frequency dividers at a period that is an integral multiple of the signal period applied to the VCO circuit, and the VCO circuit When the phase error signal output from the low-pass filter sampled in synchronization with the output timing of the center frequency exceeds a predetermined range, the control voltage is offset in a direction to reduce the phase error signal.

  In the present invention, both frequency-divided signals are forcibly phase-matched by a configuration in which the counters of the first and second frequency dividers are periodically reset. However, if the frequency of the VCO output is shifted, the phase between both frequency-divided signals will spread quickly. Therefore, in the present invention, by periodically detecting the phase error signal of the low-pass filter output, the rate of change of the phase error signal is monitored to detect whether the frequency of the VCO output is deviated. In the present invention, since the phase is not drawn into a specific absolute phase, phase drawing is fast. Note that the control that determines that the lock state is established if only the frequencies are aligned is referred to as FLL (Frequency Locked Loop) control in this specification.

The phase-locked oscillator according to the fifth aspect of the present invention (PLL high-speed pull-in) is a first variable frequency divider that divides the reference signal, and the output of the VCO circuit is divided to form the comparison signal. 2, and the control unit sets a predetermined frequency dividing ratio in the first and second variable frequency dividers and then forms a PLL loop to form a phase between the reference signal and the comparison signal. When starting the pull-in, a control voltage corresponding to the predetermined frequency division ratio is applied to the VCO circuit, and counters of the first and second variable frequency dividers are reset.

  According to the present invention, when a control voltage corresponding to the set frequency dividing ratio is applied to the VCO circuit from the beginning, a VCO output close to the required frequency can be obtained from the beginning. Further, by resetting the counters of the first and second variable frequency dividers, the initial phases of both frequency-divided signals are forcibly aligned. In this case, since the frequencies of the two frequency-divided signals already substantially coincide with each other, the phase difference between the two signals does not spread thereafter, and the PLL loop quickly converges to the locked state.

  In the sixth aspect of the present invention (using the control control voltage at the time of the previous measurement held), the control unit forms the PLL loop and starts phase pull-in between the reference signal and the comparison signal. The control voltage at the time of lock detection that is detected and held at the previous pull-in to the same frequency is applied to the VCO circuit.

  By the way, even if a control voltage corresponding to a predetermined frequency division ratio is applied to the VCO circuit, the applied control voltage is not constant because the oscillation characteristic of the VCO changes depending on the temperature. In this regard, according to the present invention, the PLL loop can be detected more quickly by the configuration in which the control voltage at the time of lock detection detected and held at the same frequency (same frequency division ratio) at the previous time at substantially the same temperature is applied. It will converge to the locked state.

  In a seventh aspect of the present invention (a configuration including two low-pass filters), the low-pass filter includes a first low-pass filter that integrates a phase error signal when measuring a control voltage, and a center frequency output timing when driving a VCO. And a second low-pass filter that integrates the sampled phase error signal, and the time constant of the first low-pass filter is made smaller than the time constant of the second low-pass filter. Therefore, the control voltage measurement time can be shortened.

  In the eighth aspect of the present invention (holding and reusing the previous phase error signal), the first low-pass filter integrates and holds the phase error signal at the time of the control voltage measurement at the time of the next control voltage measurement. The second low-pass filter holds the phase error signal sampled and integrated and held until the next VCO drive start, and held until the start.

  In the present invention, if the PLL loop start conditions (frequency division ratio, control voltage, etc.) are aligned in the same manner as in the previous time, the determination of the locked state is almost the previous control voltage measurement or VCO drive operation complete state (locked). Because it can be restarted from the environment, the frequency pull-in operation can be completed at high speed regardless of temperature fluctuations.

  The phase-locked oscillator according to the ninth aspect (frequency multiplied output) of the present invention is configured such that one of the VCO circuit outputs is connected to a variable frequency divider and the other can be output to the outside via the frequency multiplier. is there. Therefore, even when a relatively low frequency divider is used, an extremely high frequency (for example, several tens of GHz) output frequency can be easily controlled.

  The phase-locked oscillator according to the tenth aspect (output cutoff control) of the present invention is configured such that one of the VCO circuit outputs is connected to the variable frequency divider and the other can be output to the outside via the switch means. The control unit shuts off the switch means so as not to output the VCO circuit output at the time of control voltage measurement. Therefore, the control voltage can be measured without affecting the external output wave (radar wave).

The phase-locked oscillator according to the eleventh aspect of the present invention (abnormality detection of the behavior of the phase error voltage) detects an abnormality when the phase error signal of the low-pass filter sampled at the time of driving the VCO is out of a predetermined range. Is provided.

  The phase-locked oscillator according to the twelfth aspect (control voltage behavior abnormality detection) of the present invention detects an abnormality when the control voltage for generating the center frequency generated at the time of driving the VCO exceeds a predetermined range. A detection means is provided.

  The phase-locked oscillator according to the thirteenth aspect of the present invention (abnormality inspection at power-on) is measured at the time of factory shipment of the instrument and stored in a memory. In addition, the control voltage for each of the plurality of frequencies is compared, and any one of them is different beyond a predetermined range to detect a malfunction.

  The phase-locked oscillator according to the fourteenth aspect of the present invention (comprising two PLL loops) can control the first and second PLL loops according to the first aspect of the present invention with a single control unit The control unit alternately assigns control voltage measurement control and VCO circuit drive control to the first and second PLL loops, thereby providing a series of control voltage measurement control and VCO. It is apparently performed continuously with the drive control of the circuit.

  A phase-locked oscillator according to a fifteenth aspect of the present invention (comprising a VCO circuit whose modulation sensitivity does not change with temperature) includes a phase comparator that compares the phases of a reference signal and a comparison signal, and a phase error signal of the phase comparator. A low-pass filter that integrates, a control unit that intervenes in the subsequent stage of the low-pass filter, a VCO circuit that generates a signal having a frequency corresponding to the control voltage of the output of the control unit, and the VCO circuit A phase-locked oscillator including a PLL loop including a variable frequency divider that divides an output signal to form the comparison signal, wherein the control unit changes a PLL lock frequency at a predetermined interval, A control voltage measuring means for measuring the control voltage at the time of each lock for a range covering the range, and a modulation feeling representative of each section by dividing the fluctuation range of the measured control voltage into a plurality of sections. And a voltage signal for generating a linearity-corrected frequency change centered on the predetermined frequency in the VCO circuit in a state in which the PLL loop is opened after locking the PLL loop at a predetermined frequency. Is generated based on the control voltage at the time of locking and the modulation sensitivity representing each of the obtained intervals, and is provided with VCO driving means for outputting.

  According to the present invention, once the modulation sensitivity in the required frequency range is obtained in advance, the modulation sensitivity does not change much with temperature. Therefore, when the VCO is driven at an arbitrary temperature, the VCO drive means locks the PLL loop at a predetermined frequency. Then, with the PLL loop open, a voltage signal for causing the VCO circuit to generate a linearity-corrected frequency change centered on a predetermined frequency is obtained as the control voltage (reference voltage) at the time of locking and the determination. By generating and outputting based on the modulation sensitivity representing each section, the VCO circuit can always be driven at the correct frequency regardless of the temperature.

  According to a sixteenth aspect (VCO circuit calibration method) of the present invention, a phase-locked oscillator control method includes a phase comparator that compares the phases of a reference signal and a comparison signal, and a low-pass that integrates the phase error signal of the phase comparator. A filter, a control unit for performing main control of the instrument, being interposed in a subsequent stage of the low-pass filter, a VCO circuit for generating a signal having a frequency corresponding to a control voltage of the control unit output, and an output signal of the VCO circuit A control method of a phase-locked oscillator comprising a PLL loop comprising a variable frequency divider that divides and forms the comparison signal, wherein the control unit locks the PLL loop at a plurality of frequencies, A control voltage measurement step for measuring a control voltage, and a linearity calibration step for obtaining a modulation sensitivity representing a frequency change in each section connecting the frequencies based on the measured control voltages. Is intended to be executed and up, the.

  In the seventeenth aspect (VCO circuit driving method) of the present invention, the control unit locks the PLL loop at the center frequency, and then opens the PLL loop with the center frequency centered on the VCO circuit. A voltage signal for generating a linearity-corrected frequency change is generated based on the obtained modulation sensitivity, and a VCO driving step of outputting is executed.

  In the eighteenth aspect of the present invention (PLL control method), the control unit samples the output of the low-pass filter in synchronization with the timing at which the VCO circuit outputs the center frequency, and the detected phase error signal exceeds the predetermined range. In this case, the control voltage is offset in the direction of decreasing the phase error signal.

  In a nineteenth aspect of the present invention (control voltage measurement and linearity calibration execution timing), the control unit performs the multiple frequency measurement step and the subsequent linearity every time one or more VCO drive steps are executed. A calibration step.

  In a twentieth aspect of the present invention (execution timing of each control voltage measurement), the control unit sequentially executes a single control voltage measurement step every time one or more VCO driving steps are executed. is there.

  According to a twenty-first aspect of the present invention (a PLL loop high-speed pull-in method), a phase-locked oscillator control method includes: first and second variable frequency dividers that divide a reference signal and a comparison signal; A phase comparator that compares the phases of the two variable frequency divider outputs, a low-pass filter that integrates the phase error signal of the phase comparator, and a control unit that performs the main control of the device by interposing the latter stage of the low-pass filter And a phase-locked oscillator control method including a PLL loop including a VCO circuit that generates the comparison signal having a frequency corresponding to the control voltage of the control unit output, wherein the control unit includes the first and second control circuits. When a predetermined frequency division ratio is set in the variable frequency divider, a PLL loop is formed to start phase pull-in between the reference signal and the comparison signal, and the VCO circuit controls the predetermined frequency division ratio. While applying voltage, the first and first It is intended to reset the counter of the variable frequency divider of.

  As described above, according to the present invention, even if a VCO circuit having characteristic variations and temperature changes is used, the output frequency is stabilized by PLL control, and the linearity improvement of the output frequency change by VCO driving with the PLL open is improved. Therefore, it greatly contributes to the improvement of the reliability of the phase-locked oscillator and further the spread of FM-CW radar and the like using the oscillator.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings. Note that the same reference numerals denote the same or corresponding parts throughout the drawings. FIG. 1 is a block diagram of a phase-locked oscillator according to the first embodiment. In the figure, 1 is a clock oscillator that generates a PLL reference clock signal CK, 2 is a phase comparator that constitutes a PLL loop, 11 is a variable frequency divider for the clock signal CK, 12 is a variable frequency divider for VCO output, 13 Is a phase comparator (PD) that compares the phases of both frequency divider outputs φR and φV, 3 is a low-pass filter (LPF) that integrates the phase error signal of the PD 13 output, and 4 is a processor unit corresponding to the controller of the present invention. (PU), 14 is an A / D converter that samples the phase error signal Vpd of the LPF3 output, 15 is a CPU that performs the main control and processing of this oscillator, and 16 is a control voltage output from the CPU 15 that is converted into an analog control voltage Vcont. The D / A converter 5 performs a voltage-controlled oscillator (VCO) that outputs an oscillation signal having a frequency corresponding to the control voltage Vcont, and 6 passes through or shuts off the output of the VCO 5. A switch (SW).

The CPU 15 performs control to stabilize the oscillation frequency of the VCO 5 by configuring the PLL loop continuously or periodically regardless of the characteristic variation of the VCO 5 and temperature fluctuation, and the triangular wave with the PLL loop open during radar operation. Control is performed to generate a signal and to output a frequency modulation output subjected to linearity correction to the VCO 5. Specifically, various functions such as control voltage measurement means, linearity calibration means, and VCO drive means (radar transmission processing) according to the present invention are realized by executing various processes shown in FIGS. To do.

  The control voltage measuring means measures the control voltage Vcont at each lock by locking the PLL loop at a plurality of frequencies. At that time, setting data is output to the phase comparison unit 2 to set the frequency dividing ratios of the variable frequency dividers 11 and 12 as desired. Furthermore, the phase error signal Vpd output from the LPF 5 is periodically sampled, and the control voltage Vcont is updated in the direction of decreasing the phase error signal Vpd in accordance with a known PLL process, so that the PLL loop is sequentially locked at a plurality of frequencies. The control voltage Vcont acquired at the time of each lock is the control voltage Vcont necessary for causing the VCO 5 to oscillate at each predetermined frequency regardless of the characteristic variation of the VCO 5 and the temperature fluctuation.

An inset (a) shows a conceptual configuration diagram of an example PLL loop. Here, the function of the loop filter realized by the LPF 3 and the CPU 15 is represented by a digital filter having a transfer characteristic F (s). By configuring the digital filter with the CPU 15, the filter characteristics can be changed with the gain and the clock cycle. If the input of the digital filter is X (n) and the output is Y (n), the difference equation is
Y (n) = (A + B) .X (n) + Y (n-1) -A.X (n-1)
It is represented by If this is converted to Z,
Y (z) = (A + B) · X (z) + z -1 · Y (z) -A · z -1 · X (z)
And the transfer characteristic F (z) of the filter is
F (z) = Y (z) / X (z) = A + B / (1-Z ⁻¹ )
It is represented by If this is represented by F (s),
F (s) = A + B / (1-e− ^j2πfT )
It becomes.

Further, assuming that the phase of the input in the case of the PLL is θi (s) and the phase of the output is θo (s), the transfer characteristic H (s) of the loop is
H (s) = θo (s) / θi (s)
= K · F (s) / {s + K · F (s)}
However, K = Kd · Kv / N
It is represented by

  Next, the linearity calibration means obtains a modulation sensitivity that represents (for example, linear approximation) a frequency change in a section connecting the frequencies based on the measured control voltages Vcont. Then, the VCO driving (radar transmission) means locks the PLL loop at a predetermined frequency (for example, the center frequency of the triangular wave), and then opens the PLL loop to the VCO circuit based on the obtained modulation sensitivity. A voltage signal for generating a linearity-corrected frequency change centered on the frequency is generated and output. At the time of this radar transmission, since loop control is opened, loop feedback that suppresses the frequency change of the VCO 5 is not applied, so that high fidelity of the frequency change can be maintained. Further, the frequency of the radar transmission wave is also stabilized by intermittently performing loop control for stabilizing the center frequency of the radar transmission for every cycle of the radar transmission. Hereinafter, these controls and processes will be described in detail.

FIG. 2 is a flowchart of the control voltage measurement process according to the embodiment. Each control voltage V0 for obtaining the center frequency f0, the lower limit modulation frequency f1, and the upper limit modulation frequency f2 in the VCO output by changing the frequency division ratio of the PLL. The case where V1 and V2 are measured is shown. In step S11, the output EN to the RF switch SW6 is disabled so as not to output an unnecessary wave when measuring the control voltage Vcont, and the output of the radio wave (RF) is cut off. In step S12, the contents of the register i holding the measurement sequence are initialized (for example, i = 1). In step S13, the frequency division ratios Nr and Nc of the frequency dividers 11 and 12 are set so that the PLL locks at the frequency fi (initially the lower limit frequency f1). As a result, the PD 13 outputs a phase error signal corresponding to the phase error of both the divided signals φR and φV, and integrates (filters) it with the LPF 3.

  In step S14, the CPU 15 periodically acquires the phase error output Vpd of the LPF3 output. In step S15, it is determined whether or not the signal Vpd is within a predetermined range centered on a required center value (for example, 2.5 V). To do. If it is not within the predetermined range, the PLL loop is not in the locked state, so the process proceeds to step S16, and the control voltage Vcont is updated in the direction in which Vpd approaches the center value according to the normal PLL mode.

  Thus, when the phase error output Vpd becomes the center value in the determination in step S15, the PLL loop is in a locked state, so the process proceeds to step S17, and the control voltage Vcont at that time is set to Vi (initially control for the lower limit frequency f1). The voltage V1) is stored in the memory. In step S18, the contents of the register i are updated, and the next measurement object is set to the center frequency f0, for example. In step S19, it is determined whether or not the content of the register i is the measurement end. If the measurement is not completed, the process returns to step S13. Thus, the subsequent center frequency f0 (V0) and upper limit frequency f2 (V2) are measured, and when the measurement is completed in the determination of step S19, this process is exited.

  FIG. 3 shows a timing chart of the control voltage measurement operation according to the first embodiment. The phase error output Vpd of an example changes in the range of 0 to 5V, and is determined to be in the locked state around the middle 2.5V. Initially, the PLL sets the frequency division ratios Nr and Nc so as to lock at the lower limit frequency f1, for example, and performs PLL loop control at predetermined time intervals. The CPU 15 periodically acquires Vpd and updates the control voltage Vcont in a direction in which the phase error output Vpd approaches 2.5 V according to normal PLL loop control. Thus, the loop control is continued, and when Vpd ≈ 2.5 V is reached, it is in a locked state. At this time, the oscillation frequency f of the VCO 5 is accurately the lower limit frequency f 1 regardless of the characteristic variation of the VCO 5 and the fluctuation due to temperature. It has become. The CPU 15 acquires the control voltage Vcont at this time and stores it in the memory as the control voltage V1 for causing the VCO 5 to generate the lower limit frequency f1.

  Next, the PLL is locked at the center frequency f0, and Vcont at that time is stored in the memory as a control voltage V0 for causing the VCO 5 to generate the center frequency f0. Finally, the PLL is locked at the upper limit frequency f2, and Vcont at that time is stored in the memory as a control voltage V2 for causing the VCO 5 to generate the upper limit frequency f2.

  According to the present embodiment, the configuration in which the PLL loop is locked at each predetermined frequency (predetermined frequency division ratio) f0, f1, f2 allows the VCO5 to be controlled at the predetermined frequency f0, f1, regardless of the characteristic variation of the VCO5 or the temperature change. The control voltages V0, V1, and V2 for oscillating at f2 can be obtained automatically and accurately.

  FIG. 4 is a flowchart of the linearity calibration process according to the first embodiment. The section A connecting the frequencies based on the information of the set of (f1, V1), (f0, V0), (f2, V2) obtained above. The process which calculates | requires the control voltage Vcont for changing the VCO output in -D linearly by fixed frequency (DELTA) f is shown. If the control voltage Vcont obtained in this process is actually output to the VCO 5, an output frequency characteristic as shown in FIG. 5B can be obtained.

In step S31 using the information of the control voltage V0~V2 and frequency f0~f2 acquired in the process of FIG. 2, V in each section j (= to D) in which the triangle period _{T 0} example 4 divided
The modulation sensitivity of CO5 is linearly approximated by the characteristic a (j). FIG. 5C shows a timing chart of the linearity calibration operation.
・ By frequency change f1 → f0 and control voltage change V1 → V0 in section A,
Modulation sensitivity a (A) = (f0−f1) / (V0−V1)
・ By frequency change f0 → f2 and control voltage change V0 → V2 in section B,
Modulation sensitivity a (B) = (f2-f0) / (V2-V0)
・ By frequency change f2 → f0 and control voltage change V2 → V0 in section C,
Modulation sensitivity a (C) =-(f2-f0) / (V2-V0) =-a (B)
・ By frequency change f0 → f1 and control voltage change V0 → V1 in section D,
Modulation sensitivity a (D) = − (f0−f1) / (V0−V1) = − a (A)
It becomes.

  In step S32, each time point is determined according to a triangular wave condition (for example, triangular period: 10 ms, frequency deviation from the center frequency f0: ± 25 MHz) and a CPU condition (for example, Vcont time resolution 50 μs, voltage resolution: 0.005 V). A frequency change Δf at (for example, constant 0.5 MHz per 50 μs) is obtained. In step S33, the timing counter is initialized to k = 0 and the area register j = A. In step S34, for example, the control voltage V1 for generating the lower limit frequency f1 is set in the control voltage Vcont.

In step S35, the control voltage increment ΔVcont (k) is set to
ΔVcont (k) = Δf / a (j)
Ask for. In step S36, the control voltage Vcont (k + 1) at the next time point is
Vcont (k + 1) = Vcont (k) + ΔVcont (k)
Ask for. As a result, the control voltage Vcont necessary for changing the output frequency by Δf is updated. During the radar operation, the updated control voltage Vcont is output to the VCO 5 and this calculation process is periodically performed at a cycle of 50 μs.

Step S37 is +1 counter k _{in, k ≧ (T 0/4} ) in step S38 * j determines whether or not the. Here, j = A to D correspond to Equations 1 to 4. If not _{k ≧ (T 0/4)} * j , the process returns to step S35, it obtains the control voltage of the next timing.

Thus, finally, to satisfy the _{k ≧ (T 0/4)} * j is determined at the step S38, the incremented in step S39 in the area counter j, determines whether step S40 in j> 4 (= D). If j> 4 is not true, the process returns to step S35, and the same processing as described above is performed using the modulation sensitivity of the next region. Thus, finally becomes a j> 4 is determined at the step S40, it means that the determined control voltage Vcont of ₀ minutes 1 period T, exit this processing. In the present embodiment, by performing the PLL operation and the VCO linearity calibration process, the linearity of the VCO 5 can be automatically calibrated and used without providing a correction table specific to each device. Become.

  FIG. 5 is a timing chart of the linearity calibration operation according to the first embodiment, and FIG. 5A shows the original frequency modulation characteristics of the VCO 5. The horizontal axis is the control voltage Vcont, and the vertical axis is the oscillation frequency. The modulation sensitivity (Δf / ΔVcont) of the VCO 5 changes nonlinearly. When viewed from the center frequency f0, the modulation sensitivity is high on the low frequency side and low on the high frequency side. With respect to such a modulation characteristic, by adding a control voltage Vcont as shown in FIG. 5C, a characteristic in which the frequency changes linearly as shown in FIG. 5B can be obtained.

FIG. 5B shows a preferable frequency change as the FM-CW radar. The output frequency of the VCO 5 changes linearly between the lower limit f1 and the upper limit f2. The linearity calibration process is a process for obtaining a control voltage Vcont for causing the VCO 5 of FIG. 5A to output a linearly changing frequency as shown in FIG. 5B according to FIG.

FIG. 6 is a flowchart of the radar transmission process according to the first embodiment. In a state where the PLL is opened, the CPU 15 generates a continuous triangular wave with reference to V0, and the center of the triangular wave every one or two or more triangular periods. The case where the loop control for maintaining a frequency at f0 is performed intermittently is shown. In step S51, the PLL is once locked at the center frequency f0. As a result, Vpd≈2.5V and Vcont≈V0 (V0 at this time) are stabilized. In step S52 CPU 15 generates a linearity corrected triangular wave _{T 0} period the V0 as a reference is added to the VCO 5. Since the triangular wave section opens the PLL loop, the frequency of the VCO output changes linearly as shown in FIG. The release of the PLL loop can be easily realized by the CPU 15 not performing the loop control in this section.

  On the other hand, the PD 13 changes the phase error signal as the frequency of the VCO output changes. However, since the LPF 3 has a time constant sufficiently larger than the triangular wave period (for example, about 10 times), even if a triangular wave is added to the VCO 5, The phase error signal in the section is averaged by the LPF 3, and the output phase error signal Vpd is slightly changed every triangular wave period.

In step S53 _3T 0/4 at the timing of (center frequency) to obtain the phase error signal Vpd of LPF 3. When there is no change in the characteristics of the VCO 5, the phase error signals in this section are averaged and are in the vicinity of Vpd≈2.5 V. However, when the VCO characteristics change, the Vpd gradually changes accordingly. In step S54, it is determined whether or not Vpd≈Vref (= 2.5 V). If Vpd≈Vref, since f0 is within the required range, the process proceeds to step S58. If Vpd≈Vref is not satisfied, it is further determined in step S55 whether Vpd> Vref.

Vpd> proceeds to step S56 if not Vref, to increase the Vpd in the next _T 0/4, for example, the Vcont of the next time (e.g., V1) - offset to the side. In the case of Vpd> Vref to reduce Vpd in the next _T 0/4 in step S57, the offset of the next time Vcont (eg V1) to the + side. The CPU 15 determines the offset amount according to the digital filter shown in FIG. The timing for adding the offset to the control voltage may be the timing for adding V1 to the VCO 5, but may be other timing. It should be noted here that an open loop operation is performed within the period of the triangular wave, and the triangular wave characteristic of the VCO output is not deformed. Then, in synchronization with a certain point of the triangular wave cycle, the feedback is performed periodically (intermittently) and the PLL is applied. In step S58 and subsequent steps, a predetermined number of triangular waves without feedback control are output in order to set how many periods of triangular waves are to be fed back. That is, in step S58, it is determined whether or not the number of triangular waves without feedback control has been output a predetermined number of times. If not, the triangular wave without feedback control is output for one cycle in step S59. If it is executed, this process is exited.

  FIG. 7 is a timing chart of the radar transmission operation according to the first embodiment, and shows a case where an offset is added to Vcont (V1) every triangular wave period. According to the present embodiment, since feedback is applied at the moment when the triangular wave ends, the output frequency of the VCO 5 does not become poor. Since the feedback period and the loop gain of the PLL are inversely proportional, there is a method of increasing the feedback period when it is desired to reduce the loop gain and slow down the control response. For example, the control voltage Vcont can be fed back every 10 cycles of the triangular wave and the value of V1 can be offset, or can be fed back every 1000 cycles of the triangular wave and the value of V1 can be offset.

FIG. 8 is a timing chart of the radar operation operation according to the first embodiment, and shows a case where a stable radar operation can always be maintained by interrupting the linearity calibration operation of the VCO between a series of radar operations. Yes. Since the VCO 5 has temperature characteristics, when the temperature changes during the radar operation, the control voltage V0 for outputting the center frequency f0 also changes. In the present embodiment, a stable radar operation can always be maintained by periodically recalibrating the linearity.

  FIG. 8A shows a case where measurement of the control voltages V1, V0, V2 and a linearity calibration associated therewith are performed between a series of radar operations. In addition, when the temperature change is separately detected and the temperature changes more than a predetermined value, the control voltages V1, V0, and V2 may be measured and linearity calibration may be performed. Further, the measurement order of the control voltage is arbitrary, and for example, the center frequency f0 can be measured last. By doing so, since the PLL loop is already locked at the frequency f0, the process of step S51 described above with reference to FIG. 6 can be omitted when the radar operation is continued.

  FIG. 8B shows a case where the control voltages V1, V0, and V2 are measured in sequence between each series of radar operations, and the linearity calibration of the VCO 5 is performed together with the last measurement of V2. In this way, since the measurement time per control voltage is short, there is an advantage that the dead time of the radar operation can be reduced. Although not shown, this method is particularly advantageous when performing finer linearity calibration by increasing the number of control voltage measurement points in addition to the three control voltages V1, V0, and V2.

  FIG. 9 is a block diagram of a phase-locked oscillator according to the second embodiment, and shows a case where two systems of LPFs for radar and VCO calibration are provided to enable high-speed PLL pull-in in each operation. In the figure, the output of PD3 is input to LPFs 3a and 3b via switches 17a and 17b, respectively. The LPF 3a exclusively integrates the phase error signal sampled at the center frequency output timing at the time of driving the VCO, and the LPF 3b is used exclusively for the purpose of integrating the phase error signal at the time of measuring the control voltage. Preferably, the measurement time of the control voltage for each frequency can be shortened by making the time constant of the LPF 3b smaller than the time constant of the LPF 3a.

  Further, the variable frequency dividers 11 and 12 of this example are configured so that the counter can be reset from the CPU 15, and the initial phases of the divided signals φR and φV are forcibly aligned by resetting both counters at the same time. Is possible. Further, the switch SW7a is configured to be able to turn on / off the signal, and the LPF 3a integrates the phase error signal in the section where the SW 7a is ON, and when the SW 7a is turned OFF, the integrated value ( Capacitor charge) can be maintained as it is. The same applies to the switch SW7b and the LPF 3b. In this embodiment, the pull-in time of the PLL loop can be significantly shortened by effectively utilizing such a configuration. Details will be described below.

  FIG. 10 is a flowchart of the high-speed pull-in process of the phase-locked oscillator according to the second embodiment. This process includes, for example, the measurement process of the control voltage V1 in the first half and the radar operation process in the second half. For example, after the previous radar operation is completed, this processing is input. In step S61, the frequency dividing ratio of the variable frequency dividers 11 and 12 is set to f1. In step S62, V1 acquired and stored in the previous measurement of V1 is set as the control voltage Vcont. As a result, the VCO 5 generates the lower limit frequency f1 when locked in the previous measurement of V1 from the beginning regardless of temperature fluctuations. In step S63, the counters of the variable frequency dividers 11 and 12 are reset, so that the initial phases of both frequency divided signals φR and φV are quickly aligned.

In step S64, when the preparation for the V1 measurement is completed, the switch control signal SW2 is turned on to enable the PLL operation via the LPF 3b. At this time, the LPF 3b holds the phase error voltage Vpd2 (≈2.5 V) when the internal capacitor is locked in the previous control voltage measurement. This phase error voltage Vpd2 Regardless of V1, V0 or V2, in the locked state, it is about Vref (for example, about 2.5 V). Therefore, since the current PLL loop can also be started from a state close to the lock, it can converge to the lock state at an earlier time regardless of the time constant of the loop. In step S65, Vpd2 is acquired. In step S66, it is determined whether or not Vpd2≈Vref. If NO, Vcont is updated in the direction in which Vpd2 approaches Vref in step S67, and the process returns to step S65.

  Thus, when Vpd2≈Vref is determined in the determination in step S66, Vcont at that time is acquired and stored in the memory for storing the control voltage V1 in step S68. In step S69, the switch control signal SW2 is turned OFF, so that the phase error voltage Vpd2 at the time of locking this time is held in the capacitor in the LPF 3b.

  Next, the radar operation is started, and in step S71, the frequency dividing ratio of the variable frequency dividers 11 and 12 is set to the center frequency f0. In step S72, a triangular wave signal centered on V0 is superimposed on Vcont. In step S73, the counters of the variable frequency dividers 11 and 12 are reset, and the initial phase between both frequency divided signals φR and φV is quickly adjusted. In step S74, when the radar operation is ready, the switch control signal SW1 is turned on to enable the PLL operation via the LPF 3a. At this time, the LPF 3a holds the phase error voltage Vpd1 (about 2.5 V) when the internal capacitor is maintained in the substantially locked state by the previous radar operation.

  In step S75, the radar transmission control as described above with reference to FIG. 6 is performed, and in step S76, it is determined whether or not triangular wave transmission for a predetermined number of cycles has been performed. If not completed, a triangular wave without feedback control is output for one cycle in step S77. Thus, when the transmission for a predetermined number of cycles is completed in the determination in step S76, the switch control signal SW1 is turned off in step S78, so that the phase error voltage Vpd1 when the lock is maintained in the current radar operation becomes the capacitor in the LPF 3a. Retained.

  FIG. 11 is a timing chart of the high-speed pull-in operation of the phase-locked oscillator according to the second embodiment, and shows a case where the measurement process of the control voltage V1 is interrupted between each series of radar operations. When the previous radar operation is completed, the switch control signal SW1 is turned OFF (L), and Vpd1 of the LPF 3a is held. The CPU 15 sets a frequency division ratio for obtaining f1 in the variable frequency dividers 11 and 12, and outputs the previously measured V1 as Vcont. Further, the counters of the variable frequency dividers 11 and 12 are reset to match the initial phase. Now that the measurement operation is ready, the switch control signal SW2 is turned ON (H), and the PLL operation is performed according to the phase error signal Vpd2 of the LPF 3b. Thus, when it is confirmed that Vpd2 is within the lock range, the CPU 15 stores the current Vcont as a new V1. When the measurement of V1 is completed, the switch control signal SW2 is turned OFF and Vpd2 at that time is held.

  When the next radar operation is started, a frequency division ratio for obtaining f0 is set in the variable frequency dividers 11 and 12. Further, the CPU 15 outputs a triangular waveform centered on V0. Note that the triangular wave wave in this example is calibrated after measuring V2. Further, the counter of the variable frequency divider is reset to match the initial phase. Since the radar operation is ready, the switch control signal SW1 is turned on to operate the PLL with the radar Vpd1. Thereafter, V0 and V2 are acquired in the same manner, and linearity configuration data is updated.

  FIG. 12 is a block diagram of a phase-locked oscillator according to the third embodiment, which includes two PLL circuits, which are controlled by a single CPU 15 and simultaneously execute radar operation using one loop. In this example, linearity calibration of the VCO circuit is performed using the other loop, and these are alternately performed by the PLL circuits of both systems. Thereby, it is possible to eliminate the dead time of the radar operation.

  FIG. 13 shows an operation timing chart of the phase-locked oscillator according to the third embodiment. The radar operation is performed by the PLLa, and the measurement of V1, V0, and V2 and the linearity calibration of the VCO 5b are performed by the PLLb. Next, the radar operation is performed by the PLLb, and the measurement of V1, V0, and V2 and the linearity calibration of the VCO 5a are performed by the PLLa. The switching may be performed periodically, for example, every 5 minutes, or may be performed when the temperature change of the outside air exceeds a certain range.

  FIG. 14 is a diagram for explaining a phase-locked oscillator according to the fourth embodiment. The oscillation frequency of the VCO circuit drifts due to temperature change, but it is suitable for application to a VCO circuit whose modulation sensitivity does not change much with temperature. Shows the case. In practice, there are many VCO circuits having such characteristics. The PLL circuit may be the same as that described in FIG. 1, FIG. 9, or FIG. FIG. 14A shows the modulation characteristics of this type of VCO circuit. Assuming that the modulation curve at room temperature is a, the curve shifts to the curve b side at high temperatures and shifts to the curve c side at low temperatures. In such a VCO circuit, even when the same control voltage V0 is applied, the oscillation frequency changes from f0 ′ to f0 ″ depending on the temperature, but the modulation sensitivity in the vicinity of V0 does not change, so the frequency is changed by Δf. Therefore, ΔVcont does not change with temperature. This is true for the entire control voltage range Vmin to Vmax.

  FIG. 14B shows a flowchart of linearity calibration processing for this VCO circuit. In step S81, by changing the frequency dividing ratios Nr and Nc of the variable frequency divider PLL, the lock frequency is gradually increased and swept, and the control voltage Vcont is measured each time. In step S82, for each of the measured control voltages Vcont, the control voltage possible fluctuation ranges Vmin to Vmax are divided, for example, every 1V, and modulation sensitivities a01, a12, a23,. In step S83, a frequency change Δf (constant in this example) at each time point is obtained based on the triangular wave condition and the CPU condition. Thus, a sensitivity table that can be used in common regardless of temperature fluctuations is obtained.

  Although not shown, at the time of radar transmission, the control voltage V0 at that time is obtained by first locking the PLL to f0. Thereafter, for example, Vcont is increased by Δf from V0 to the upper limit frequency f2. At that time, it is determined in which voltage section the Vcont of each time point is, and the voltage change of the section is obtained by using the modulation sensitivity of each corresponding section. Thus, when f2 is reached, Vcont is then decreased to the lower limit frequency f1 and then increased to f0. Then, such control is repeated. Therefore, according to the present embodiment, it is possible to always transmit a radar wave in an appropriate frequency range regardless of temperature fluctuations. Further, since it is not necessary to perform linearity calibration processing for temperature fluctuations, the radar operation can be operated without interruption.

  FIGS. 15 and 16 are diagrams (1) and (2) for explaining the phase-locked oscillator according to the fifth embodiment. FIG. 15 is replaced with PLL control for aligning the phase between both the divided signals φR and φV. In this example, so-called FLL (frequency locked loop) control is performed in which it is not necessary to align the phases if only the frequencies are aligned. In general, when the control voltage Vcont is D / A converted and applied to the VCO 5, the output frequency of the VCO 5 changes stepwise by at least the 1-bit voltage resolution of the D / A 16 × the magnitude of the modulation sensitivity. On the other hand, the PLL loop (that is, LPF3) operates in an analog manner so that the average frequency of the radar transmission wave driven by the triangular wave becomes f0. Therefore, if the lock detection width of the phase error signal Vpd is made too narrow, offset correction with respect to the control voltage V0 is performed. Will occur frequently. In the fifth embodiment, in order to solve this problem, FLL control is performed instead of PLL control. The circuit configuration may be the same as that shown in FIG. 1, for example, but it is assumed that the counter of the variable frequency dividers 11 and 12 can be reset from the CPU 15.

In general, the phase between both frequency-divided signals φR and φV causes the VCO 5 to free run (ie,
In the state in which the PLL loop is open), even if the frequencies of both frequency-divided signals φR and φV are the same, their phases gradually shift (slip), but this fifth embodiment Thus, by resetting the counters of the variable frequency dividers 11 and 12 every period, it is possible to effectively avoid a significant phase difference within one period of the triangular wave. However, if the oscillation frequency of the VCO 5 deviates from the required value, the phase difference between the two signals φR and φV also spreads quickly in a short time, and in this state, the phase error signal Vpd is observed every period. Can be detected reliably.

  In FIG. 15, in the present embodiment based on FLL control, the frequency of the VCO 5 output only needs to be within a predetermined range even if the phase between both frequency-divided signals φR and φV is not aligned. When the counters of the counters 11 and 12 are reset, for example, every period of the triangular wave, and when it is detected that the Vpd has changed more than a predetermined value within a unit interval (for example, one period), the output frequency is outside the predetermined range. The control voltage Vcont is offset. FIG. 16 shows the operation of the phase comparison unit 2. As a method of realizing the FLL control, it can be easily realized by resetting the counters of the variable frequency dividers 11 and 12 periodically (one or more cycles of a triangular wave).

  FIG. 17 is a diagram for explaining a phase-locked oscillator according to the sixth embodiment, and shows a case where the CPU 15 generates a binary wave signal subjected to linearity calibration instead of generating a triangular wave signal. The configuration of the phase-locked oscillator may be the same as that shown in FIG. 1, FIG. 9 or FIG. In the figure, the VCO 5 in this example periodically outputs frequencies f1 and f2 alternately as time t progresses. The center frequency is f0. Such a phase-locked oscillator is suitable for application to a two-frequency CW radar device.

  18 and 19 are diagrams (1) and (2) for explaining the failure detection operation according to the embodiment. FIG. 18 (A) shows a case where the phase error signal Vpd is in an abnormal level during normal operation. . When this device is used for in-vehicle use, it is necessary to constantly monitor the operation state because it is related to human life. In the present embodiment, the lock error is detected when the phase error signal Vpd is out of the normal voltage range in which the PLL can be pulled in during normal operation.

  FIG. 18B shows a case where the central control voltage V0 during normal operation is at an abnormal level. Under severe use environment, the center frequency f0 (that is, the control voltage V0) may fluctuate significantly due to, for example, water intrusion into the casing or condensation. In the present embodiment, an abnormality in the VCO operation is detected when the control voltage V0 is out of the normal range during normal operation.

  FIG. 9 shows a case where the linearity calibration result when the power is turned on is abnormal. VCO characteristics also deteriorate with time. In this embodiment, when the apparatus is turned on or periodically, a PLL loop is formed and linearity calibration is performed. For example, Vcont measured values V0, V2, and V1 for f0, f2, and f1 when the power is turned on, and factory shipment When it is detected that any one or more of these values have deviated from a predetermined value or more by comparing these values with time, it is determined that there is an abnormality. In this example, it is compared whether the absolute voltage is within the specified range, but it may be compared whether the relative voltage value between the voltages is within the specified range.

  In FIG. 1, FIG. 9, or FIG. 12, when this circuit is used for a millimeter wave band FM-CW radar or the like, the millimeter wave band variable frequency divider 12 is used. When the frequency divider is difficult to obtain or expensive, the variable frequency divider 12 having a lower frequency may be used, and the output of the VCO 5 may be multiplied to the millimeter wave band by the frequency multiplier (MULTI) 7 and output. .

  Further, the signal generated by the CPU 15 can generate various signal waveforms (sine wave, sawtooth wave, etc.) in addition to the triangular wave signal and the binary wave signal.

  In the above embodiment, the modulation sensitivity of the VCO 5 is linearly approximated over the three measurement points f1, f0, and f2. However, the present invention is not limited to this. By increasing the number of measurement points, higher-precision approximation is possible, and the accuracy of linearity calibration can be increased.

  Moreover, in the said embodiment, although the modulation sensitivity in several area was represented by the linear approximation in each area, it is not restricted to this. The curve in each section may be approximated by a higher-order function or an exponential function that can be approximated more faithfully.

  In the above embodiment, the clock signal CK of the phase comparison unit 2 and the CPU 15 is shared, but a clock signal of a different system may be used for the CPU 15.

  Moreover, although several embodiment suitable for the said invention was described, it cannot be overemphasized that the structure of each part, control, a process, and these combination can be variously changed within the range which does not deviate from this invention. .

1 is a block diagram of a phase locked oscillator according to a first embodiment. FIG. It is a flowchart of the control voltage measurement process by 1st Embodiment. It is a timing chart of control voltage measurement operation by a 1st embodiment. It is a flowchart of the linearity calibration process by 1st Embodiment. It is a timing chart of the linearity calibration operation | movement by 1st Embodiment. It is a flowchart of the radar transmission process by 1st Embodiment. It is a timing chart of radar transmission operation by a 1st embodiment. It is a timing chart of radar operation operation by a 1st embodiment. It is a block diagram of the phase locked oscillator by 2nd Embodiment. It is a flowchart of the high-speed drawing-in process of the phase-locked oscillator by 2nd Embodiment. 6 is a timing chart of a high-speed pull-in operation of the phase-locked oscillator according to the second embodiment. FIG. 5 is a block diagram of a phase locked oscillator according to a third embodiment. 10 is a timing chart of the operation of the phase-locked oscillator according to the third embodiment. It is a figure explaining the phase locked oscillator by 4th Embodiment. It is a figure (1) explaining the phase locked oscillator by 5th Embodiment. FIG. 10 is a diagram (2) illustrating a phase locked oscillator according to a fifth embodiment. It is a figure explaining the phase locked oscillator by 6th Embodiment. It is a figure (1) explaining the failure detection operation by an embodiment. It is FIG. (2) explaining the failure detection operation | movement by embodiment. It is a figure explaining a prior art.

Explanation of symbols

1 Clock Oscillator 2 Phase Comparison Unit 3 Low Pass Filter (LPF)
4 Processor unit (PU)
5 Voltage controlled oscillator (VCO)
6 RF switch (SW)
7 Frequency multipliers 11 and 12 Variable frequency divider 13 Phase comparator (PD)
14 A / D converter 15 CPU
16 D / A converter

Claims (21)

A phase comparator that compares the phase of the reference signal and the comparison signal, a low-pass filter that integrates the phase error signal of the phase comparator, and a control unit that performs the main control of the instrument by interposing the latter stage of the low-pass filter; A phase locked loop including a PLL loop including a VCO circuit that generates a signal having a frequency according to a control voltage of the control unit output, and a variable frequency divider that divides the output signal of the VCO circuit to form the comparison signal. An oscillator, wherein the controller is
Control voltage measuring means for locking the PLL loop at a plurality of frequencies and measuring a control voltage at each lock;
A phase-locked oscillator comprising: linearity calibration means for obtaining a modulation sensitivity representing a frequency change in a section connecting the frequencies based on the measured control voltages. A voltage for causing the VCO circuit to generate a linearity-corrected frequency change centered on the predetermined frequency based on the obtained modulation sensitivity in a state where the PLL loop is opened after the PLL loop is locked. 2. A phase-locked oscillator according to claim 1, further comprising a VCO driving means for generating and outputting a signal. The VCO driving means samples the output of the low-pass filter in synchronization with the timing at which the VCO circuit outputs the center frequency, and when the detected phase error signal exceeds a predetermined range, the control voltage is set to decrease the phase error signal. The phase-locked oscillator according to claim 2, wherein the phase-locked oscillator is offset. A first divider that divides the reference signal; and a second divider that divides the output of the VCO circuit to form the comparison signal;
The VCO driving means periodically resets the counters of the first and second frequency dividers at an integer multiple of the signal period applied to the VCO circuit, and is synchronized with the timing at which the VCO circuit outputs the center frequency. 3. The phase locked oscillator according to claim 2, wherein when the phase error signal of the low-pass filter output sampled exceeds a predetermined range, the control voltage is offset in a direction to reduce the phase error signal. A first variable frequency divider that divides the reference signal; and a second variable frequency divider that divides the output of the VCO circuit to form the comparison signal. When a predetermined frequency division ratio is set in the second variable frequency divider, a PLL loop is formed to start phase pull-in between the reference signal and the comparison signal, and the VCO circuit corresponds to the predetermined frequency division ratio. 3. The phase-locked oscillator according to claim 1, wherein the control voltage is applied and the counters of the first and second variable frequency dividers are reset. When the control unit forms the PLL loop and starts the phase pull-in between the reference signal and the comparison signal, the control unit detects the previous pull-in to the same frequency and applies the held control voltage at the lock detection to the VCO circuit. The phase-locked oscillator according to claim 5. The low-pass filter includes a first low-pass filter that integrates a phase error signal at the time of control voltage measurement, and a second low-pass filter that integrates a phase error signal sampled at a center frequency output timing at the time of VCO driving, 4. The phase-locked oscillator according to claim 3, wherein a time constant of the first low-pass filter is made smaller than a time constant of the second low-pass filter. The first low-pass filter holds the phase error signal at the time of lock detection integrated and held at the time of the current control voltage measurement until the next control voltage measurement start, and the second low-pass filter samples at the time of the current VCO drive, 8. The phase-locked oscillator according to claim 7, wherein the phase error signal integrated and held is held until the next VCO drive start. 3. The phase-locked oscillator according to claim 1, wherein one of the VCO circuit outputs is connected to a variable frequency divider and the other can be output to the outside via a frequency multiplier. One of the VCO circuit outputs is connected to the variable frequency divider, and the other is configured to be output to the outside via the switch means, and the control unit switches so as not to output the VCO circuit output during control voltage measurement to the outside. 2. A phase locked oscillator according to claim 1, wherein said means is cut off. 4. The phase-locked oscillator according to claim 3, further comprising detection means for detecting an abnormality when a phase error signal output from the low-pass filter sampled during VCO driving is out of a predetermined range. 4. The phase-locked oscillator according to claim 3, further comprising detection means for detecting an abnormality when a control voltage for generating the center frequency generated when the VCO is driven exceeds a predetermined range. Each control voltage for a plurality of frequencies measured at power-on of the instrument is compared with each control voltage for the plurality of frequencies measured at the time of shipment of the instrument and stored in a memory. 2. The phase-locked oscillator according to claim 1, further comprising detection means for detecting an abnormality by making a difference beyond the range. The first and second PLL loops according to claim 1 are configured to be controllable by a single control unit, and the control unit controls control voltage measurement and VCO with respect to the first and second PLL loops. A phase-locked oscillator characterized in that a series of control voltage measurement control and VCO circuit drive control are apparently continuously performed by alternately sharing circuit drive control. A phase comparator that compares the phase of the reference signal and the comparison signal, a low-pass filter that integrates the phase error signal of the phase comparator, and a control unit that performs the main control of the instrument by interposing the latter stage of the low-pass filter; A phase locked loop including a PLL loop including a VCO circuit that generates a signal having a frequency corresponding to a control voltage of the control unit output, and a variable frequency divider that divides the output signal of the VCO circuit to form the comparison signal. An oscillator, wherein the controller is
A control voltage measuring means for changing a lock frequency of the PLL at a predetermined interval and measuring a control voltage at the time of each lock for a range covering a predetermined frequency range;
A linearity calibration means for dividing the measured variation range of the control voltage into a plurality of sections and obtaining a modulation sensitivity representing each section;
After the PLL loop is locked at a predetermined frequency, a voltage signal for generating a linearity-corrected frequency change centered on the predetermined frequency in the VCO circuit with the PLL loop opened is controlled at the time of the lock. A phase-locked oscillator comprising: a VCO driving unit that generates and outputs a voltage based on a voltage and a modulation sensitivity representing each of the obtained intervals. A phase comparator that compares the phase of the reference signal and the comparison signal, a low-pass filter that integrates the phase error signal of the phase comparator, and a control unit that performs the main control of the instrument by interposing the latter stage of the low-pass filter; A phase locked loop including a PLL loop including a VCO circuit that generates a signal having a frequency corresponding to a control voltage of the control unit output, and a variable frequency divider that divides the output signal of the VCO circuit to form the comparison signal. An oscillator control method, wherein the control unit includes:
A control voltage measurement step of locking the PLL loop at a plurality of frequencies and measuring a control voltage at the time of each lock;
And a linearity calibration step for obtaining a modulation sensitivity representing a frequency change in each section connecting the frequencies based on the measured control voltages. The control unit locks the PLL loop at the center frequency, and then outputs a voltage signal for generating a linearity-corrected frequency change centered on the center frequency in the VCO circuit in a state where the PLL loop is opened. 17. The control method according to claim 16, wherein a VCO driving step that generates and outputs based on the obtained modulation sensitivity is executed. The control unit samples the output of the low-pass filter in synchronization with the timing at which the VCO circuit outputs the center frequency, and when the detected phase error signal exceeds a predetermined range, the control voltage is set in a direction to reduce the phase error signal. The control method according to claim 17, wherein offsetting is performed. 18. The control method according to claim 17, wherein the control unit executes the measurement step of the plurality of frequencies and the linearity calibration step subsequent to the measurement step every time one or more VCO driving steps are executed. 18. The control method according to claim 17, wherein the control unit sequentially executes a single control voltage measurement step every time one or more VCO driving steps are executed. First and second variable frequency dividers that divide the reference signal and the comparison signal, a phase comparator that compares the phases of the first and second variable frequency divider outputs, and a phase error of the phase comparator A low-pass filter that integrates the signal, a control unit that intervenes in the subsequent stage of the low-pass filter, and a VCO circuit that generates the comparison signal having a frequency corresponding to the control voltage of the control unit output A phase-locked oscillator control method including a PLL loop, wherein the control unit includes:
After setting a predetermined frequency dividing ratio in the first and second variable frequency dividers, when the PLL circuit is formed to start the phase pull-in between the reference signal and the comparison signal, the VCO circuit has the predetermined frequency dividing ratio. A control method for a phase-locked oscillator, comprising adding a control voltage corresponding to a frequency ratio and resetting the counters of the first and second variable frequency dividers.

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