JP2008059155A - Information processing apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus and method that prevent memory access collision. <P>SOLUTION: The information processing apparatus has a nonvolatile memory 15 for storing a system program, a processing program and predetermined information; a volatile memory 13; and a CPU 11 which, when simultaneously performing the process of copying the predetermined information to the volatile memory and the process of the processing program in accordance with the system program stored in the nonvolatile memory, accesses the volatile memory to obtain previously used data in the volatile memory and store the data in a cache memory 12 (S33), and which thereafter performs control to read the predetermined information from the nonvolatile memory and copy the information in the volatile memory (S37) and to process by means of the processing program the data stored in the cache memory (S36). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information processing apparatus and an information processing method for simultaneously performing a plurality of information processing.

  Recently, microcomputers have become very popular, and their application range is diverse. A microcomputer system having a plurality of memories such as a flash memory and a main memory is known.

Patent Document 1 shows a microcomputer system having a DMAC (Direct Memory Access Controller) for controlling DMA transfer between a flash memory and a main memory, and performs DMA transfer processing between memories and CPU program processing. The processing to be performed simultaneously is shown.
JP 2004-118544 A

  However, the conventional technique of Patent Document 1 has a problem that access to the main memory resulting from the DMA transfer process and the program process collides during the process of simultaneously performing the DMA transfer process between the memories and the CPU program process. .

  An object of the present invention is to provide an information processing apparatus and an information processing method that do not cause an access collision to a memory by program processing and other transfer processing.

One embodiment of the present application is:
A non-volatile memory (15) for storing a system program (FIG. 5), a processing program, and predetermined information;
Volatile memory (13);
When performing the copying process of the predetermined information to the volatile memory and the processing of the processing program simultaneously according to the system program stored in the nonvolatile memory,
Accessing the volatile memory, obtaining the data in the volatile memory used earlier and storing it in the cache memory (12) (S33),
Thereafter, the predetermined information is read from the nonvolatile memory, copied to the volatile memory (S37),
An information processing apparatus comprising: a CPU (11) that controls to process data stored in the cache memory using the processing program (S36).

  Provided is an information processing system that realizes a plurality of smooth information processings by avoiding a collision of a plurality of accesses by a program process to a volatile memory that is a main memory and another transfer process.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an example of the configuration of an information processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating an example of a configuration of a nonvolatile memory included in the information processing apparatus according to the embodiment of the present invention. FIG. 3 is a flowchart showing an example of read processing of a nonvolatile memory included in the information processing apparatus according to the embodiment of the present invention. FIG. 4 is a flowchart showing an example of a procedure of data copy processing (DMA) and program processing (CPU) in an information processing apparatus having no features of the present invention. FIG. 5 is a timing chart showing an example of a procedure of data copy processing (DMA) and program processing (CPU) in an information processing apparatus having no features of the present invention. FIG. 6 is a flowchart showing an example of a procedure of data copy processing (DMA) and program processing (CPU) in the information processing apparatus according to the embodiment of the present invention. FIG. 7 is a timing chart showing an example of a procedure of data copy processing (DMA) and program processing (CPU) in the information processing apparatus according to the embodiment of the present invention.

<Information processing apparatus according to an embodiment of the present invention>
(Constitution)
An information processing apparatus according to an embodiment of the present invention includes a CPU (central processing unit) 11 that performs calculation and data processing, a main memory 13 for the CPU to store a system program, a processing program, data, and the like, and a nonvolatile memory. And a DMA 14 which is a controller for exchanging data between the main memory 13 and the non-volatile memory 15 or the external input / output unit 16.

  In addition, since the speed difference between the main memory 13 and the CPU 11 is a problem, the CPU 11 has a high-speed and small-capacity cache memory 12 and stores frequently used data in the cache memory 12. The external input / output unit 16 is connected as necessary.

  Due to the speed problem during data access, the system program, processing program, and data are read from the nonvolatile memory 15 to the main memory 13 when the system is started. Also, the calculation result is once stored in the main memory 13 and then written in the nonvolatile memory 15 as necessary. Since the main memory 13 is a volatile memory, the data is erased when the power is turned off.

  Next, an example of the configuration of the nonvolatile memory 15 shown in FIG. 1 will be described with reference to FIG. The non-volatile memory 15 has a controller 21 that performs control during reading and writing, a data buffer 22 that temporarily stores data, and a status that holds a current status (for indicating a state in which a command is not accepted). A register 23 and a data storage unit 24 are included. In the data storage unit 24, data is stored for each page 25 in which fixed-length data is collected.

(Non-volatile memory operation)
First, an example of the read operation of the nonvolatile memory 15 will be described using the flowchart of FIG.

  Note that the steps in the flowcharts of FIGS. 3, 4, and 6 below can be replaced with circuit blocks. Therefore, all the steps of the flowcharts can be redefined as blocks.

  When the nonvolatile memory 15 receives a read command from the CPU 11, the controller 21 starts sequential read processing according to the procedure of the flowchart shown in FIG. First, the non-volatile memory 15 receives the address sent from the CPU 11 and determines the page to be read (step S11). When the nonvolatile memory 15 receives the address, the data is read from the corresponding page and written to the data buffer (step S12). During this time, the nonvolatile memory 15 is in a busy state (a state in which command transmission, data reading, etc. are not accepted) (step S14).

  The nonvolatile memory 15 performs the sequential reading process until all requested data is read (step S13). Note that once the read command and the address are transmitted to the nonvolatile memory 15, the data in the same page can be read. However, when reading the data of different pages, the read command and the address are transmitted to the nonvolatile memory 15 again. There is a need.

(Program processing and copy processing when one of the features of the present invention is not performed)
Next, an example of the operation in the case where access to the main memory collides because the program processing in the CPU 11 and the copy processing by the DMA 14 are not performed in one operation of the present invention will be described with reference to FIG. This will be described with reference to the flowchart and the timing chart of FIG.

  The procedure described below reads data from the non-volatile memory 15, checks the read data (for the purpose of detecting data errors or data tampering caused by noise or the like), and decompressing the compressed data And processing such as decryption of encrypted data.

  The following operation may be realized by copying a system program stored in the nonvolatile memory 15 to the main memory 13 and processing the system program as an example.

  First, the CPU 11 transmits a read command (step S21) and an address (step S22) to the nonvolatile memory 15 according to the system program. Since the CPU 11 is in a busy state for a while until the data can actually be read after the address transmission (step S29), the CPU 11 waits until it becomes a ready state (a state in which command transmission and reading from the data buffer are possible). (Step S23). The ready / busy determination is confirmed by repeatedly reading the status register (step S26).

  In the ready state, the CPU 11 instructs the DMA 14 to read data (step S24) and waits until the reading is completed (step S25). When reading is completed, data check processing is performed on the read data (step S26), and program processing (decoding, decompression, etc.) is performed on the read data (step S27).

  If the necessary reading is not completed (NO in step S28), the process returns to step S21 to read another page, and the processing after address transmission is repeated again.

  In the embodiment described here, since it is assumed that data is encrypted or compressed, it is necessary to separately perform processing such as decryption and decompression in these steps. Also, it is necessary to check the read data before the decryption / decompression process.

  Here, the problem that access to the main memory 13 collides in the above-described process will be described with reference to the timing chart of FIG. That is, in FIG. 5, since the DMA 14 and the CPU 11 can perform processing independently, the page 2 read processing T2 and the page 1 check processing T4 in FIG. 5 can be performed simultaneously.

  However, the page 2 read process T2 and the page 1 check process T4 are performed at the same time, so that the access process from the CPU 11 to the main memory 13 and the access process from the DMA 14 to the main memory 13 collide. Thereby, when there is this simultaneous access, it is necessary to temporarily stop access of either the CPU 11 or the DMA 14. Therefore, there arises a problem that the efficiency of the program processing of the CPU 11 or the copy processing of the DMA 14 is reduced (as an example, the processing efficiency is reduced by several tens of percent).

(Program processing and copy processing according to a procedure which is one of the features of the present invention)
Next, a copy process and a program process by DMA according to a procedure which is one of the features of the present invention in which such a collision of access processes is avoided will be described with reference to the flowchart of FIG.

  The flowchart of FIG. 6 is characterized in that the page data check processing in the main memory in step S33 and the program processing such as decryption and decompression in step S36 are performed at independent timings, whereby the main memory 13 associated with the two processes Access to is completely separated.

  That is, in the flowchart of FIG. 6, the procedure in this case will be described in detail below. The following operation may be realized by copying and processing a system program stored in the nonvolatile memory 15 to the main memory 13 as an example.

  First, the CPU 11 transmits a read command (step S31) and an address (step S32) to the nonvolatile memory 15 according to the system program. Next, the CPU 11 checks the previously read page data in the main memory 13 and stores the data in the cache memory 12 (step S33).

  Thereafter, the CPU 11 waits until it becomes ready (command transmission and reading from the data buffer are possible) (step S34). In the ready state, the CPU 11 instructs the DMA 14 to read data (step S35).

  Then, the CPU 11 performs program processing (decoding, decompression, etc.) on the data of the page read last time according to the processing program (step S36). At the same time, the DMA 14 performs data copying from the nonvolatile memory 15 to the main memory 13 (step S37). Thereafter, the CPU 11 confirms whether or not data copying has been completed (step S38), and if completed (step S39), the processing after step S31 is repeated.

  By taking such a procedure, it is possible to avoid the collision between the access to the main memory 13 from the CPU 11 performed in step S33 and the access to the main memory 13 from the DMA 14 in step S37.

  Such timing will be described with reference to the timing chart of FIG. 7. When the page 1 data is copied from the main memory 13 to the cache memory in the page 1 check process T 13, the CPU 11 transfers it to the main memory 13. Is accessed. Since the access from the DMA 14 to the main memory 13 in the page 2 read process T12 is performed after the check process T13 is completed, the accesses to the two main memories 13 collide as shown in FIGS. Never do. Therefore, all the processes for accessing the main memory 13 can avoid a delay caused by an access collision to the main memory 13.

  With the various embodiments described above, those skilled in the art can realize the present invention. However, it is easy for those skilled in the art to come up with various modifications of these embodiments, and have the inventive ability. It is possible to apply to various embodiments at least. Therefore, the present invention covers a wide range consistent with the disclosed principle and novel features, and is not limited to the above-described embodiments.

The block diagram which shows an example of a structure of the information processing apparatus which concerns on one Embodiment of this invention. The block diagram which shows an example of a structure of the non-volatile memory which the information processing apparatus which concerns on one Embodiment of this invention has. 6 is a flowchart illustrating an example of a read process of a nonvolatile memory included in the information processing apparatus according to an embodiment of the present invention. 6 is a flowchart showing an example of a procedure of data copy processing (DMA) and program processing (CPU) in an information processing apparatus having no features of the present invention. 6 is a timing chart showing an example of a procedure of data copy processing (DMA) and program processing (CPU) in an information processing apparatus having no features of the present invention. 6 is a flowchart illustrating an example of a procedure of data copy processing (DMA) and program processing (CPU) in the information processing apparatus according to the embodiment of the present invention. 6 is a timing chart showing an example of a procedure of data copying processing (DMA) and program processing (CPU) in the information processing apparatus according to the embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Information processing apparatus, 11 ... CPU, 12 ... Cache memory, 13 ... Main memory, 14 ... DMA, 15 ... Nonvolatile memory, 16 ... External input / output part

Claims (8)

A non-volatile memory for storing a system program, a processing program, and predetermined information;
Volatile memory,
When performing the copying process of the predetermined information to the volatile memory and the processing of the processing program simultaneously according to the system program stored in the nonvolatile memory,
Access the volatile memory, obtain the data in the volatile memory used earlier, and save it in the cache memory,
Thereafter, the predetermined information is read from the nonvolatile memory, copied to the volatile memory,
An information processing apparatus comprising: a CPU that controls to process data stored in the cache memory using the processing program.   2. The information processing apparatus according to claim 1, further comprising a direct memory access controller used when the predetermined information is read from the nonvolatile memory and copied to the volatile memory.   According to the system program, before the step of accessing the volatile memory, obtaining the data in the volatile memory used earlier and storing it in the cache memory, a read command from the CPU to the nonvolatile memory, The information processing apparatus according to claim 1, wherein the information processing apparatus is controlled to transmit an address. According to the system program, after accessing the volatile memory, obtaining the data in the volatile memory used earlier and storing it in the cache memory,
2. The information processing apparatus according to claim 1, wherein after waiting until the nonvolatile memory becomes ready, the direct memory access controller is instructed to read data. An information processing method performed in an information processing system having a system program, a processing program, a non-volatile memory for storing predetermined information, and a volatile memory,
When performing the copying process of the predetermined information to the volatile memory and the processing of the processing program simultaneously according to the system program stored in the nonvolatile memory,
Access the volatile memory, obtain the data in the volatile memory used earlier, and save it in the cache memory,
Thereafter, the predetermined information is read from the nonvolatile memory, copied to the volatile memory,
An information processing method comprising controlling to process data stored in the cache memory using the processing program.   6. The information processing method according to claim 5, wherein a direct memory access controller used when the predetermined information is read from the nonvolatile memory and copied to the volatile memory is used.   According to the system program, before the step of accessing the volatile memory, obtaining the data in the volatile memory used earlier and storing it in the cache memory, a read command from the CPU to the nonvolatile memory, 6. The information processing method according to claim 5, wherein an address is transmitted. According to the system program, after accessing the volatile memory, obtaining the data in the volatile memory used earlier and storing it in the cache memory,
6. The information processing method according to claim 5, wherein after waiting until the nonvolatile memory becomes ready, the direct memory access controller is instructed to read data.

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