JP2008051581A - Device test apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the efficiency in a device test and reduce test costs per DUT (Device Under Test) by making effective use of limited hardware resources. <P>SOLUTION: The device test apparatus 100 comprises a test head 120 which is fitted into a performance board 130 on which a plurality of DUTs 140 are mounted and is provided with a plurality of test terminals electrically connected to the device terminals of the plurality of DUTs, a terminal setting section 152 which allows the device terminals to be arbitrarily allocated to the plurality of test terminals without being limited by clusters dividing the test terminals in the test head by a predetermined number and creates device definition files indicating the correspondence relationship between the device terminals and the test terminals, an ATE allocation section 154 for allocating test parameters of the device terminals in a test program to the test terminals on the basis of the device definition files, and a test performing section for performing tests on the plurality of DUTs using the allocated test parameters. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a device test apparatus and a device test method for performing an electrical test of a device under test.

  In recent years, an integrated circuit (IC: Integrated Circuit) has been increased in capacity, speed, and size (high density). With respect to a memory device which is one of integrated circuits, such a need is particularly high, and electrical function tests are required to be performed at high speed and complicated as the density of the memory device increases.

  In a device test apparatus that performs such an electrical function test, an operation margin test (power supply voltage margin, access time, etc.) of a device under test, particularly various memory devices, is performed. In this device test, the number of failures of each device, for example, the number of defective bits, is counted, and the quality of the memory device is determined based on the counting result. Thereafter, if the number of failures of the memory device is greater than a predetermined number, the memory device is determined to be defective, and the test is terminated. If the number is less than the predetermined value, repair repair processing is performed.

  Such an electrical function test involves steps such as memory device refresh, fail bit extraction, and fail count counting. A technology that can reduce the test time by parallel processing of refresh and fail count counting is disclosed. (For example, Patent Document 1).

  In order to further shorten the test time, a device test apparatus capable of simultaneously processing a plurality of devices under test (Device Under Test: hereinafter referred to as “DUT”) in parallel (multi-DUT test) has been devised.

  The device test apparatus includes a test terminal (also referred to as an ATE (Automatic Test Equipment) terminal), a large number of pin modules that perform a test function are mounted, and the test terminals are managed in units of clusters as shown in FIG. To do. In this cluster 10, an error can be extracted by the logical sum of all the test terminals in the cluster 10. Therefore, the cluster 10 is not assigned to two or more DUTs and prohibits assignment of device terminals of other DUTs. Each cluster 10 has the same number of test terminals as the terminal numbers shown in FIG.

  In such a multi-DUT test in units of clusters, the user simply creates a device definition file for one DUT in the device definition file, and test terminals having the same function are developed in other clusters. Therefore, the user does not need to individually set a test terminal for each of the plurality of DUTs.

  In recent years, when creating a device definition file, the user selects the number of DUTs to be tested from powers of 2, such as 1, 2, 4, 8, and the test program control library of the device test apparatus assigns the test terminal to the cluster unit. The technique of assigning to the DUT is also disclosed (for example, Patent Document 2). For example, in a device test apparatus in which 512 test terminals are mounted, as shown in FIG. 10, the test terminals that can be used in each DUT corresponding to the DUT number are determined according to the number of DUTs. The numbers of the test terminals connected to the second and subsequent DUTs are allocated with an offset of 256 for the total number of test terminals (offset) in the cluster allocated to the DUT, for example, when there are two DUTs.

When two DUTs are subjected to a multi-DUT test, the device test apparatus assigns test terminals by adding 256 offsets to four clusters corresponding to the respective DUTs. Therefore, the user can
PIN (1) {VIH = 5V;}
Is described, the test terminal number 1 and the test terminal number 257 are assigned a high level of 5V.
JP 2004-348892 A JP-A-11-64448

  However, in the method of providing the above cluster, the number of DUTs is limited to a power of 2, such as 1, 2, 4 and 8, and when trying to test 3 or 5 DUTs, 4 or 8 DUTs are used. I had to specify it. Further, since at least one cluster is assigned to one DUT, when the total number of device terminals is small, unnecessary test terminals are generated in the cluster, and the utilization efficiency is poor.

  Furthermore, in the method of separating the plurality of clusters, for example, signals common to all the plurality of DUTs such as a clock signal, a data input signal, a power supply signal, and a ground signal are also set for each cluster. It was happening.

  The present invention has been made in view of the above-described problems of the conventional device test apparatus, and an object of the present invention is to effectively use limited hardware resources, increase the efficiency of device testing, and improve the performance per DUT. To provide a new and improved device test apparatus and device test method capable of reducing the test cost.

  In order to solve the above problems, according to an aspect of the present invention, there is provided a device test apparatus for performing an electrical test of a plurality of DUTs, which is fitted with a performance board on which a plurality of DUTs are mounted, A test head provided with a plurality of test terminals electrically connected to the device terminals of the DUT, and a plurality of test of the device terminals without being limited to a cluster in which the test terminals in the test head are divided into predetermined numbers. A terminal setting unit that arbitrarily assigns terminals and generates a device definition file indicating the correspondence between the device terminals and the test terminals, and an ATE that assigns test parameters of the device terminals in the test program to the test terminals based on the device definition file An allocation unit, and a test execution unit that performs a plurality of DUT tests using the allocated test parameters. Characterized Rukoto, device testing apparatus is provided. The cluster is an area in which device terminals of other DUTs can be excluded and only the device terminals of the DUT corresponding to the own cluster can be allocated.

  With this configuration, device terminals of a plurality of DUTs can be freely assigned to a plurality of test terminals on the test head, and a limited number of test terminals can be used effectively. Accordingly, the number of DUTs in one multi-DUT test can be increased, and the efficiency of the device test can be increased.

  In addition, since the correspondence between the device terminals and the test terminals is stored in a database as a device definition file, the correspondence between both terminals can be referred to easily and accurately by any other program.

  When a device terminal having a common signal is provided in any one of the plurality of DUTs, the two or more common device terminals can be assigned to one test terminal. Further, when device terminals having a common signal across two or more DUTs among a plurality of DUTs are provided, the two or more common device terminals can be assigned to one test terminal.

  With this configuration, a plurality of common device terminals can be connected to one test terminal, and the test terminals can be used effectively. Therefore, the number of DUTs in one multi-DUT test can be further increased, and the efficiency of the device test can be increased.

  The common device terminal may be one or more signals selected from the group of a clock signal, a data input signal, a power supply signal, and a ground signal. A terminal corresponding to an input (not an output) in the DUT can be connected across a plurality of DUTs. Therefore, the clock signal, data input signal, power supply signal, ground signal, etc. may be acquired from one test terminal.

  The terminal setting unit may associate and assign a plurality of test terminals to specific device terminals of the plurality of DUTs. In the device definition file, by assigning arbitrary test terminals corresponding to specific device terminals at the same time and juxtaposing them, it is possible to prevent the occurrence of unassigned terminals and to visually confirm confirmation of duplicate terminals etc. It becomes possible.

  The test program may further include a direct setting unit that allows the test parameters to be directly defined at the test terminal. With this configuration, it is possible to operate the test terminal only with the test program without referring to the device definition file, and the work efficiency is increased. In addition, since test parameters can be set for each test terminal, a specific DUT can be independently tested.

  The test head is further provided with a plurality of relay cards for relaying the test signal. The relay card includes a correspondence storage unit that stores the correspondence between the device terminals and the test terminals in the device definition file, and a valid / A signal limiting unit that determines a valid test terminal based on the validity signal indicating invalidity and the correspondence stored in the correspondence storage unit, and that restricts the signal of the test terminal from the test head. .

  By importing the correspondence between both terminals from the device definition file into the relay card, it is possible to determine whether the test terminal is valid or invalid in units of DUT, and it is possible to determine whether the DUT is valid or invalid in units of clusters. The test can be continued or interrupted in units.

  In order to solve the above-described problem, according to another aspect of the present invention, a plurality of DUT device terminals and a plurality of test terminals of a test head are electrically connected, and the plurality of DUTs are electrically tested. A device test method for performing a test, wherein the device terminals are arbitrarily assigned to a plurality of test terminals without being limited to a cluster in which the test terminals in the test head are divided into predetermined numbers, and the device terminals and the test terminals are A device definition file indicating a correspondence relationship is generated, a test parameter of a device terminal in a test program is assigned to the test terminal based on the device definition file, and a plurality of DUT tests are performed using the assigned test parameter. A device test method is provided.

  With this configuration, like the device test apparatus, it is possible to freely assign device terminals of a plurality of DUTs to a plurality of test terminals on the test head, and the limited test terminals can be used effectively. Accordingly, the number of DUTs in one multi-DUT test can be increased, and the efficiency of the device test can be increased.

  The components corresponding to the dependent claims in the device test apparatus described above and the descriptions thereof are also applicable to the device test method.

  As described above, when the test terminal allocation according to the present invention is executed, the test terminal can be effectively used by utilizing the existing circuit, the device test efficiency can be improved, and the test cost per unit DUT can be reduced. .

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  The device test apparatus has a large number of test terminal modules that perform a test function, and can test a plurality of DUTs (devices under test) in parallel and simultaneously (multi-DUT test) via a performance board. Since the plurality of DUTs are conventionally managed in units of clusters, the number of clusters corresponding to the DUTs is also limited to a power of 2 (1, 2, 4, 8), and the remainder of the test terminals of the cluster is different. The DUT could not be used.

  For example, when four DUTs having 100 device terminals are tested with a device test apparatus having 512 test terminals, 28 test terminals in each cluster and 112 test terminals in total remain. Further, since signals common to all the plurality of DUTs are also set for each cluster, useless overlapping terminals are generated.

  Since the test head provided with the test terminal includes expensive equipment such as a high-accuracy timing generator and a pattern memory, it is not an effective use of resources to perform the test with the test terminal remaining. The device test apparatus in the present embodiment effectively uses test terminals having a limited number, increases the number of DUTs in one multi-DUT test, and increases the efficiency of the device test.

(Device test apparatus 100)
FIG. 1 is a functional block diagram showing a schematic configuration of the entire device test apparatus 100 in the present embodiment. The device test apparatus 100 includes a main body 110 and a test head 120. A performance board 130 is mounted on the test head 120, and a DUT 140 is disposed on the performance board 130.

  The main body 110 is provided with a control unit that performs a test process set via the user interface 112. The test head 120 is provided with a relay card (also referred to as a PE (Pin Electronics) card) 122 having 16 or 32 pin modules for performing a test function and belonging to a cluster. The relay card 122 reflects the command from the main body 110 on the test terminal. Invalidation of the signal to the DUT 140 is performed by invalidating all the relay cards 122 connected to the cluster corresponding to the DUT 140. Here, invalidation may be the maintenance of the output state (stop of output change) or the stop of output.

  The performance board 130 can be fitted to the test head 120 and can be mounted with the DUT 140, and electrically connects a plurality of test terminals and device terminals of the DUT 140.

  FIG. 2 is a functional block diagram for illustrating schematic functions of the device test apparatus 100 according to the present embodiment. The device test apparatus 100 includes a central control unit 150, a pin module 160, a pattern generator 162, an address pointer 164, a multiplexer 166, a fail memory 168, a fail bit counter 170, and a controller 172. Is done.

  The central control unit 150 includes a processing device such as a CPU, and also functions as a terminal setting unit 152, an ATE allocation unit 154, and a direct setting unit 156. The central control unit 150 also controls a pattern generator 162 and a controller 172 described later.

  The terminal setting unit 152 arbitrarily assigns each device terminal of the plurality of DUTs 140 to be tested to a plurality of test terminals, and generates a device definition file indicating a correspondence relationship between the device terminals and the test terminals. In this embodiment, since there is no area limitation of the cluster 10 in which the test terminals in the test head are divided every predetermined number, the test terminals can be freely assigned, and the efficiency of the device test can be increased. For example, in the device test apparatus 100 provided with the 512 test terminals described above in the test head 120, it is possible to test five DUTs having 100 device terminals.

  FIG. 3 is an explanatory diagram showing an example of the device definition file. In this device definition file, the number of DUTs 200 and the terminal correspondences defined by the device terminal number 202, the device terminal name 204, and the test terminal number 206 are defined. As described above, since the correspondence between the device terminals and the test terminals is created as a database as a device definition file, the correspondence between both terminals can be easily and accurately referred to by any other program. The device definition file is not limited to the above format as long as device terminals and test terminals are associated with each other.

  Further, when there is a device terminal having a common signal in any one of the plurality of DUTs 140, the terminal setting unit 152 can assign the two or more common device terminals to one test terminal. Further, even when there are device terminals having a common signal across two or more DUTs 140 among a plurality of DUTs, the two or more common device terminals can be assigned to one test terminal.

  By integrating such a plurality of common device terminals into one test terminal, the test terminal can be used more effectively. When a common device terminal is recognized, it may be automatically assigned to an empty test terminal, or may be displayed on the user interface 112 such as a monitor so that the user can determine whether to consolidate to the same test terminal. .

  As such a common device terminal, a terminal corresponding to an input of a clock signal, a data input signal, a power supply signal, a ground signal or the like in the DUT 140 can be applied.

  Based on the device definition file generated by the terminal setting unit 152, the ATE allocation unit 154 allocates device terminal test parameters in a test program to be described later to the test terminals. In this way, the test terminal test preparation for each DUT 140 is completed.

  The direct setting unit 156 causes the device terminal to be used to define test parameters and generates a test program. The test program control library performs a test with reference to the test program. Conventionally, the terminal number in the test program is limited to the number of the device terminal, and the test parameter can be defined only for the device terminal, and the test terminal can be defined only indirectly. In the test program, the direct setting unit 156 according to the present embodiment can directly define the test parameter in the test terminal instead of the device terminal.

For example, in a conventional test program, when defining test parameters for device terminals common to a plurality of DUTs 140,
PIN (1) {V = 5V;}
In such a description, 5 V was output to the first device terminal.

In this embodiment, newly,
PIN (100: ATE) {V = 5V;}
The description is supported.

  The test program is compiled into a format that can be recognized by the system software. At the time of compilation, a flag indicating that the test terminal is specified as the terminal number is added, and when the test program is executed, the system software is targeted for the test terminal. Recognize that. In that case, without referring to the device definition analysis library, a process based on the description of the test parameter is assigned to the designated test terminal, in this case, a process of outputting 5V to the test terminal No. 100 is assigned.

  Previously, it was necessary to rewrite the device definition file even if it was attempted to perform predetermined processing only on a specific test terminal. With this configuration, however, the test terminal can be operated only with the test program without referring to the device definition file. Work efficiency. In addition, since individual test parameters can be set for each test terminal, it is possible to independently test a specific DUT.

  The pin module 160 includes a format controller FC, a driver D, a comparator C, a digital comparator DC, a DC input / output unit DCIO, and the like as functions for device terminals.

  The format controller FC shapes the waveform of a test pattern (signal) received from a pattern generator 162 described later and outputs the waveform to the driver D. The driver D amplifies the signal of the format controller FC so that the voltage amount or the current amount becomes a sufficient amount, and outputs the amplified signal to the DUT 140. The comparator C compares the signal from the DUT 140 with an arbitrary voltage level and outputs the result to the digital comparator DC. The digital comparator DC determines from the output result of the comparator C whether the output of the device terminal is normal (pass) or abnormal (fail). The DC input / output unit DCIO outputs a DC voltage and current, and detects the voltage value or current value of the device terminal.

  The pattern generator 162 generates an address of the DUT 140, outputs it to each test terminal together with a test pattern such as an input pattern and an expected value pattern, and outputs the same address to a multiplexer 166 described later. The address pointer 164 generates an address for counting the number of files independently of the pattern generator 162 and outputs the address to the multiplexer 166.

  The multiplexer 166 selects the address of the pattern generator 162 and the address of the address pointer 164 according to the control signal, and designates the address in the fail memory 168.

  The fail memory 168 stores fail information (for example, “1”) from each test terminal in an area indicated by an address from the multiplexer 166. The fail bit counter 170 counts the number of fail bits in the fail memory 168 according to an instruction from the controller 172.

  The controller 172 controls the address pointer 164, multiplexer 166, fail memory 168, and fail bit counter 170.

  The test execution unit in the present embodiment includes the central control unit 150, the pattern generator 162, the address pointer 164, the multiplexer 166, the fail memory 168, the fail bit counter 170, the controller 172, etc., and is assigned by the ATE assigning unit 154. A plurality of DUTs 140 are tested with test parameters.

  Here, the test of the memory device is specifically described as the DUT. However, the present invention is not limited to this, and various DUTs can be tested and various electrical test methods can be applied. For example, as an electrical test executed by the device test apparatus 100, a power supply voltage margin test for measuring the margin of the operable range by changing the power supply voltage, or a margin for reading and writing data by changing the access time is measured. An access time margin test may be performed.

  Hereinafter, the correspondence between the device terminal and the test terminal by the terminal setting unit 152 of the device test apparatus 100 described above will be described in detail.

(Device definition file, test program)
FIG. 4 is a functional block diagram showing the relationship between the ATE allocation unit 154 and the database 180. The ATE allocation unit 154 refers to the device definition file in the database 180 through the device definition analysis library.

For example, when the number of DUTs in the multi-DUT test is 5, as shown in the device definition file as the number of DUTs 200 in FIG.
MULIT
DUT 5
ENDMULTI
Is described.

  In the method of allocating test terminals in cluster units, only the powers of 2 such as 1, 2, 4, and 8 can be described in the number of DUTs. It can also be defined.

Next, description of the correspondence between the device terminal of the DUT 140 and the test terminal of the test head 120 will be described. For example, the correspondence between terminals is defined as “device terminal number“ ”, device terminal name“ = ”test terminal number”, as shown in FIG. In the conventional method of allocating test terminals in cluster units, the number 100 of test terminals is allocated to the number 1 of any device terminal.
1 PIN1 = 100;
Is defined in the device definition file, the test program control library assigns test terminals for each DUT with a certain offset, here 128.

For example, when the description of the test program is defined as PIN (“device terminal number”) {test parameter to device terminal number}, the description of applying 5 V to No. 1 of the DUT 140 is as follows:
PIN (1) {V = 5V;}
It becomes.

  When the test program control library instructs the device definition analysis library to expand the first terminal of the device terminal to the number of the test terminal based on the description of the PIN (1) {V = 5V;}, the DUT 140 The first is assigned to the test terminal No. 100 from the description of the device definition file, and the second and later are assigned to the 228, 356, and 484th with an offset of 128. Therefore, a voltage output of 5V is output to the test terminals 100, 228, 356, and 484.

The terminal setting unit 152 according to the present embodiment can associate and assign a plurality of test terminals to a correspondence relationship of device definition files, that is, specific device terminals of the plurality of DUTs 140. For example, if there are five DUTs 140 and test terminals are freely assigned to the device terminals of each DUT 140, the device definition file contains
1 PIN1 = 100,500,300,200,400;
2 PIN2 = 250,250,250,250,250;
Can be described.

  Here, the offset can be set freely regardless of the number of test terminals in the cluster. By assigning arbitrary test terminals corresponding to specific device terminals at once in the device definition file, it is possible to prevent the occurrence of unassigned terminals, and it is possible to visually confirm confirmation of duplicate terminals etc. . Further, since the test program is not changed, such an arbitrary allocation can be performed while utilizing the existing program.

  In the description of the device definition file, the same test terminal is assigned to the second terminal of the DUT 140. In the present embodiment, a plurality of common device terminals can be connected to one test terminal in this way, and the test terminals can be used effectively. Therefore, when there are 18 such common terminals, for example, the required number of terminals of the DUT 140 is 100, 82, 82, 82, 82, 82 (total 510) in each DUT 140. The number of DUTs in each multi-DUT test can be increased to 6, and the efficiency of the device test can be increased.

The test program control library is described in the test program.
PIN (1) {V = 5V;}
Based on the description, the device definition analysis library is instructed to convert the first terminal of the device terminal into the test terminal number. In this embodiment, the first terminal of the device terminal of the DUT 140 is the test terminal number. Allocated to the 100th, 200th, 300th, 400th, and 500th. Therefore, a voltage output of 5 V is output to the test terminals 100, 200, 300, 400, and 500.

(Relay card 122)
When executing the test program, the system software can execute a function (DUT sequential test) in which the DUTs 140 are sequentially tested one by one and the subsequent tests of the failed DUTs 140 are not performed. In order to perform such a function, the device test apparatus 100 can designate and operate or stop only hardware resources corresponding to a specific DUT. When a cluster is assigned to the DUT 140, the relay card 122 itself belonging to the cluster is validated or invalidated.

  FIG. 5 is a functional block diagram for explaining a schematic function of the relay card 122 managed in cluster units. The cluster 10 is assigned to each of DUT 1 and DUT 2 in FIG. 5, and the relay card 122 belongs to the cluster 10, and each pin module of the relay card 122 does not straddle the DUT 140 or the cluster 10. In other words, all the pin modules 160 of one relay card are connected to the same DUT 140.

  The system software outputs a valid / invalid validity signal to the firmware operated by the CPU in the relay card when the test program is executed, and the relay card 122 designated as invalid, such as DUT1, is a relay card. All the signals passing through 122 are invalidated, and the relay card 122 designated as valid like DUT2 validates the signal.

  However, when the test terminals are arbitrarily assigned to the DUT 140 as in the present embodiment, the test terminals connected to the plurality of DUTs 140 are mixed in one relay card 122, and in the conventional firmware, the DUT unit is used. Cannot be enabled / disabled.

  FIG. 6 is a functional block diagram for explaining schematic functions of the relay card 300 according to the present embodiment. The relay card 300 includes a correspondence relationship storage unit 302 and a signal restriction unit 304, and operates validity / invalidity for each DUT 140 even when test terminals are arbitrarily assigned to the DUT 140 as in this embodiment. be able to.

  The correspondence relationship storage unit 302 stores the correspondence relationship between device terminals and test terminals in the device definition file. This correspondence relationship is obtained by notifying the firmware of the relay card 300 of the correspondence relationship of each terminal first obtained from the device definition file by the system software when the test program is loaded.

  FIG. 7 is an explanatory diagram for explaining the correspondence 310 between device terminals and test terminals stored in the correspondence storage 302. In this correspondence 310, which DUT 140 is used by each terminal (terminal number) in the relay card 300 (usage = '1') is displayed as a bitmap. For example, in the example of FIG. 7, No. 1 of the relay card is connected to DUT 1 and No. 4 is connected to DUT 2. No. 12 is a common test terminal for DUT1 and DUT3.

  The signal limiting unit 304 determines a valid test terminal based on the validity signal indicating validity / invalidity of the DUT unit from the system software and the correspondence relationship stored in the correspondence relationship storage unit, and the test from the test head Limit the signal at the terminal.

  FIG. 8 is an explanatory diagram for explaining signal restriction by the signal restriction unit 304. FIG. 8A shows the validity signal, in which valid DUT 140 (valid = '1') is bit-set in an 8-bit bitmap format. Here, it can be understood that DUT2 and DUT4 are valid and other DUTs are invalid. FIG. 8B shows the test terminal commands developed by the test program control library in a bitmap format. In this test terminal signal command, it is instructed to output 5 V to the test terminals of the second, fourth, and seventh bits of the relay card 300.

  The signal limiter 304 recognizes that the DUT1 is invalid and the DUT2 is valid based on the validity signal shown in FIG. 8A, and corresponds to the DUT2 based on the correspondence 310 stored in the correspondence storage 302. It can be seen that the test terminal to be activated, for example, the fourth test terminal should be enabled. Then, from the actually developed signal command of FIG. 8B, only the fourth signal related to DUT2 is validated, and 5 V is applied to the fourth test terminal. This can also be derived from the logical product of each terminal of the effective DUT of the correspondence 310 and each terminal in the signal command.

  Thus, by importing the correspondence 310 between the two terminals from the device definition file to the relay card 300, it is possible to determine whether the test terminal is valid or invalid in units of DUT, and whether the DUT is valid or invalid in units of cluster. Even without this, the test can be continued or interrupted in units of DUT. The relay card 300 can also support a conventional cluster system.

(Device test method)
A device test method for testing the DUT 140 using the device test apparatus 100 described above is also provided. In such a device test method, first, the terminal setting unit 152 assigns the device terminals of the plurality of DUTs 140 to the plurality of test terminals of the test head 120, generates a device definition file indicating the correspondence between the device terminals and the test terminals, Thereafter, the ATE allocation unit 154 allocates the test parameters of the device terminals in the test program to the test terminals based on the device definition file, and the test execution unit performs tests on the plurality of DUTs 140 using the allocated test parameters.

  With this configuration, like the device test apparatus, it is possible to freely assign device terminals of a plurality of DUTs to a plurality of test terminals on the test head, and the limited test terminals can be used effectively.

  With the device test apparatus 100 and the device test method described above, the number of DUTs in one multi-DUT test can be increased, manufacturing costs are reduced, and product competitiveness is increased. Further, since the test terminals can be freely assigned to the DUT 140, it is possible to test the influence of the wiring pattern by setting the distance between the device terminal and the test terminal to a predetermined value.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

It is the functional block diagram which showed the schematic structure of the whole device test apparatus in this embodiment. It is a functional block diagram for showing a rough function of a device test apparatus by this embodiment. It is explanatory drawing which showed an example of the device definition file. It is the functional block diagram which showed the relationship between an ATE allocation part and a database. It is a functional block diagram for demonstrating the schematic function of the relay card | curd managed per cluster. It is a functional block diagram for demonstrating the schematic function of the relay card by this embodiment. It is explanatory drawing for demonstrating the correspondence of the device terminal which a correspondence memory | storage part memorize | stores, and a test terminal. It is explanatory drawing for demonstrating the signal restriction | limiting by a signal restriction | limiting part. It is explanatory drawing for demonstrating arrangement | positioning of the cluster in the conventional test head. It is explanatory drawing which showed distribution of the test terminal of the conventional cluster unit.

Explanation of symbols

100 device test apparatus 120 test head 122,300 relay card 140 DUT
152 terminal setting unit 154 ATE allocation unit 156 direct setting unit

Claims (8)

A device test apparatus for performing an electrical test of a plurality of devices under test,
A test head provided with a plurality of test terminals which are fitted with a performance board on which the plurality of devices under test are mounted and electrically connected to device terminals of the devices under test;
A device definition that allows the device terminals to be arbitrarily assigned to the plurality of test terminals without being limited to clusters obtained by dividing the test terminals in the test head into a predetermined number, and indicates a correspondence relationship between the device terminals and the test terminals. A terminal setting unit for generating a file;
An ATE allocation unit that allocates test parameters of the device terminal in the test program to the test terminal based on the device definition file;
A test execution unit for performing a test of the plurality of devices under test with the assigned test parameters;
A device test apparatus comprising:   2. The device according to claim 1, wherein when any one of the plurality of devices under test is provided with a device terminal having a common signal, the two or more common device terminals are assigned to one test terminal. The device test apparatus described.   When a device terminal having a common signal across two or more devices under test among the plurality of devices under test is provided, the two or more common device terminals are assigned to one test terminal. The device test apparatus according to claim 1.   4. The device according to claim 2, wherein the common device terminal is one or more signals selected from a group of a clock signal, a data input signal, a power supply signal, and a ground signal. Test equipment.   The device test apparatus according to claim 1, wherein the terminal setting unit assigns a plurality of test terminals to a specific device terminal of the plurality of devices under test in association with each other.   The device test apparatus according to claim 1, further comprising a direct setting unit that allows the test program to directly define a test parameter in the test program. The test head is further provided with a plurality of relay cards that relay test signals,
The relay card is
A correspondence storage unit that stores the correspondence between device terminals and test terminals in the device definition file;
A signal restriction that determines a valid test terminal based on the validity signal indicating validity / invalidity of the device under test and the correspondence relationship stored in the correspondence relationship storage unit and restricts the signal of the test terminal from the test head And
The device test apparatus according to claim 1, comprising: A device test method for electrically connecting device terminals of a plurality of devices under test and a plurality of test terminals of a test head to perform an electrical test of the devices under test,
A device definition that allows the device terminals to be arbitrarily assigned to the plurality of test terminals without being limited to clusters obtained by dividing the test terminals in the test head into a predetermined number, and indicates a correspondence relationship between the device terminals and the test terminals. Generate a file
Based on the device definition file, assign test parameters of the device terminal in the test program to the test terminal,
A device testing method comprising performing testing of the plurality of devices under test with assigned test parameters.

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