JP2008022513A - Amplifier with distortion control function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier with a distortion control function capable of approximating a distortion compensation amount to that of an AB class amplifier, in the case where doherty amplifier is coupled with a distortion compensator. <P>SOLUTION: A doherty amplifier 20 equipped with a carrier amplification circuit and a peak amplification circuit is coupled with a predistorter 102, for compensating nonlinear distortion of the doherty amplifier 20. An input signal of the doherty amplifier 20 is detected with a directional coupler 162 and a detecting circuit 163, which is inputted in a control part 117 through an A/D converter 164. The intermodulation distortion contained in the output signal of the doherty amplifier 20 is detected with a distortion detecting part 112 and is inputted in the control part 117. The control part 117 controls the predistorter 102 so that a distortion value detected with the distortion detecting part 112 comes smaller. It arbitrarily controls bias of the peak amplification circuit according to the output of the A/D converter 164 and the distortion value detected with the distortion detecting part 112, so that AM-AM conversion characteristics of the doherty amplifier 20 approaches AB class. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an amplifying apparatus used in a base station such as a cellular phone system, and more particularly to an amplifying apparatus with a distortion control function for making constant intermodulation distortion after distortion compensation of a Doherty amplifier (Doherty amplifier).

  Conventionally, when power-amplifying a CDMA signal or a multi-carrier signal, distortion compensation means is added to the common amplifier, and the operation range of the common amplifier is extended to the vicinity of the saturation region to reduce power consumption. Distortion compensation means include feedforward distortion compensation and predistortion distortion compensation. However, distortion compensation alone is approaching the limit of low power consumption. Therefore, in recent years, Doherty amplifiers have attracted attention as high efficiency amplifiers.

  However, as the efficiency of the Doherty amplifier is improved, the AM-AM (input amplitude level to output amplitude level) conversion characteristic and the AM-PM (input amplitude level to output phase rotation amount) conversion characteristic are deteriorated. The feedforward distortion compensation and the predistortion distortion compensation cannot completely compensate for the distortion.

  Further, the AM-AM conversion characteristic of a general Doherty amplifier is not equivalent to that of a conventional AB class amplifier. This is because the Doherty amplifier is configured by combining two amplifiers (carrier amplifier, peak amplifier) having different operation classes. The carrier amplifier is normally in AB class operation, and the peak amplifier is in C class operation. The peak amplifier when the input level is high increases in gain as the input level increases, but is not equivalent to the carrier amplifier. For this reason, when amplifiers having different operation classes are finally combined, the gain near saturation is lowered.

  The distortion compensation when combining such a general Doherty amplifier and a general distortion compensator is compared with the distortion compensation amount of the conventional AB class amplifier, that is, the distortion compensation of the AB class amplifier in the case of the same output. Degraded compared to the amount. This is because the nonlinearity is larger than that of the AB class amplifier because the gain near saturation is lowered. Therefore, the efficiency cannot be brought out to the limit due to the deterioration of the intermodulation distortion after distortion compensation.

  Here, a power amplifying apparatus that performs conventional predistortion distortion compensation will be described with reference to a block diagram shown in FIG.

  In FIG. 13, reference numeral 102 denotes a predistorter that compensates for nonlinear distortion, performs distortion compensation for a signal input from the input terminal 101, and outputs the signal to the D / A converter 103. The D / A converter 103 converts the digital signal into an analog signal in synchronization with the clock signal CLK 1 and outputs the analog signal to the quadrature modulator 104. The quadrature modulator 104 quadrature modulates an input signal with a signal from the oscillator 105. The signal modulated by the quadrature modulator 104 is amplified by the power amplifier 106 and output from the output terminal 107.

  A part of the output signal of the power amplifier 106 is taken out via the directional coupler 108 and input to the mixer 109. The mixer 109 down-converts the signal extracted by the directional coupler 108 to an IF frequency based on the oscillation frequency from the oscillator 110 and outputs it to the A / D converter 111. The A / D converter 111 converts the IF signal into a digital signal in synchronization with the clock signal CLK <b> 2 and outputs the digital signal to the distortion detection unit 112. The distortion detection unit 112 includes a fast Fourier transform circuit (FFT) 113 and an IM (intermodulation) calculation circuit 114, obtains a distortion value of the signal output from the power amplifier 106, and controls the control unit 115. Output to. The control unit 115 adaptively controls the predistorter 102 so that the distortion value detected by the distortion detection unit 112 becomes small.

  In the above configuration, a part of the signal output from the power amplifier 106 is taken out via the directional coupler 108, down-converted to the IF frequency by the mixer 109, and then converted into a digital signal by the A / D converter 111. It is converted and sent to the distortion detector 112. The distortion detector 112 obtains the spectrum of the IF signal by the fast Fourier transform circuit 113, and then IM3 (third-order intermodulation distortion) calculated from the number of carriers of the modulation signal and its detuning frequency by the IM arithmetic circuit 114, A power value at a frequency of IM5 (fifth-order intermodulation distortion) is set as a distortion value. The control unit 115 adaptively controls the predistorter 102 so that the distortion value detected by the distortion detection unit 112 becomes small. The signal whose distortion has been compensated by the predistorter 102 is converted into an analog signal by the D / A converter 103, and then quadrature modulated by the quadrature modulator 104, amplified by the power amplifier 106, and output from the output terminal 107. The

Next, the configuration of the predistorter 102 will be described with reference to the block diagram shown in FIG.
Since the nonlinear characteristic of the power amplifier 106 appears as intermodulation distortion is odd-order distortion, the predistorter 102 to which the nonlinear inverse characteristic of the power amplifier 106 is added can be approximated by [Equation 1].

[Formula 1]
y = α * | x | ² * x + β * | x | ⁴ * x + γ * | x | ⁶ * x
Here, x and y are complex numbers in the input signal and output signal of the predistorter 102. The control unit 115 controls the values of α, β, and γ using a perturbation method so that the strain value obtained by the strain detection unit 112 becomes small. Α, β, and γ are complex numbers.
[Formula 2]
α = A3 * exp (j * φ3)
β = A5 * exp (j * φ5)
γ = A7 * exp (j * φ7)
Where α is determined by A3 and φ3, β is determined by A5 and φ5, and γ is determined by A7 and φ7. These coefficients are changed in the order of φ3 → A3 → φ5 → A5 → φ7 → A7 → φ3... And the values of α, β, and γ are updated so that the distortion value becomes small.

Since the predistorter 102 can be approximated by the above [Equation 1] as described above, it is configured as shown in FIG. That is, for the signal x input to the input terminal 101, a first arithmetic system 120 that performs an operation of “α * x ³ ”, a second arithmetic system 130 that performs an operation of “β * x ⁵ ”, “γ * x ⁷ ”is provided, a third operation system 140 is provided, and the operation results of the first, second, and third operation systems 120, 130, and 140 and the input signal x are added by the adder 150, The addition result y is output from the output terminal 151.

The first arithmetic system 120 includes a multiplier 122 that multiplies the input signal x and the output | x | ² of the constant unit 121, and a multiplier 123 that multiplies the output of the multiplier 122 and the coefficient α.

The second arithmetic system 130 includes a multiplier 132 that multiplies the input signal x and the output | x | ⁴ of the constant unit 131, and a multiplier 133 that multiplies the output of the multiplier 132 and the coefficient β.

The third arithmetic system 140 includes a multiplier 142 that multiplies the input signal x and the output | x | ⁶ of the constant unit 141, and a multiplier 143 that multiplies the output of the multiplier 142 and the coefficient γ.

  As described above, the control unit 115 controls the values of the coefficients α, β, and γ using the perturbation method so that the distortion value obtained by the distortion detection unit 112 becomes small, and the nonlinear inverse characteristic in the power amplifier 106 is obtained. Approximation by the predistorter 102 using a power series enables distortion compensation.

  However, the amplifier that has performed the predistortion distortion compensation is approaching the limit of reducing the power consumption only by the distortion compensation as described above.

FIG. 15 is a block diagram showing a configuration of a conventional Doherty amplifier.
A signal input to the input terminal 1 is distributed by the distributor 2, and one of the signals is input to the carrier amplifier circuit 4. The carrier amplifier circuit 4 includes an amplifier element 42, an input matching circuit 41 that matches the input side of the amplifier element 42, and an output matching circuit 43 that matches the output side of the amplifier element 42. The output of the carrier amplifier circuit 4 is impedance-converted by a λ / 4 transformer 61.

The other signal distributed by the distributor 2 is delayed by 90 degrees in the phase shifter 3 and input to the peak amplifier circuit 5. Like the carrier amplifier circuit 4, the peak amplifier circuit 5 includes an input matching circuit 51, an amplifier element 52, and an output matching circuit 53. The outputs of the λ / 4 transformer 61 and the peak amplifier circuit 5 are synthesized at a node (synthesis point) 62. The λ / 4 transformer 61 and the node 62 are collectively referred to as a Doherty synthesizer 6. The synthesized signal is impedance-converted by the λ / 4 transformer 7 to match the output load Z ₀ and supplied to the load 9 via the output terminal 8. As the amplifying elements 42 and 52, semiconductor devices such as LD-MOS (Lateral Diffused MOS), GaAs-FET, HEMT, and HBT are usually used.

  The carrier amplifying circuit 4 and the peak amplifying circuit 5 are different in that the amplifying element 42 is biased to class AB and the amplifying element 52 is biased to class B or C. Therefore, the amplifying element 42 operates alone until the input at which the amplifying element 52 operates, and when the amplifying element 42 enters the saturation region and the linearity of the amplifying element 42 starts to collapse, the amplifying element 52 starts to operate, and the amplifying element 52 The output of 52 is supplied to the load 9 and drives the load 9 together with the amplifying element 42. At this time, the load line of the output matching circuit 43 moves from a high resistance to a low resistance. However, since the amplifying element 42 is in the saturation region, the efficiency is good. When the input from the input terminal 1 further increases, the amplifying element 52 of the peak amplifying circuit 5 starts to saturate, but both the amplifying elements 42 and 52 are saturated, and at this time, the efficiency is good.

  FIG. 16 is a diagram showing theoretical collector efficiency (%) to drain efficiency (%) in the Doherty amplifier of FIG. The collector efficiency here means the ratio of the radio frequency output power that can be extracted from the collector to the product of the voltage (DC) of the power source applied to the collector and the current (DC) supplied from the power source, The same applies to the drain efficiency.

  The horizontal axis of FIG. 16 is backoff (dB), and the input level to the minimum input terminal 1 where both of the amplifying elements 42 and 52 are saturated, that is, the compression point is 0 dB, and how much the input level is relative to the compression point. It is a numerical value indicating whether there is room.

  In FIG. 16, a solid line indicates the efficiency of the Doherty amplifier in a simple model, and a broken line indicates the efficiency of a general class B amplifier.

When the input level is small and the backoff is in the region A of 6 dB or more, only the carrier amplifier circuit 4 basically operates. The carrier amplifier circuit 4 starts to saturate near the backoff of 6 dB, and the efficiency reaches near the maximum efficiency of the class B amplifier. Assuming that the maximum output of the Doherty amplifier is P ₀ , the output of the carrier amplifier circuit 4 at this time is about P _0/4 .

In the region B where the backoff is 6 dB or less, as the input level increases, the output of the carrier amplifier circuit 4 increases from about P _0/4 to P _0/2 , and the output of the peak amplifier circuit 5 increases from approximately 0 to P _0. Increase to / 2. At this time, the sum of the output powers of the carrier amplifier circuit 4 and the peak amplifier circuit 5 is proportional to the input power to the input terminal 1 with the same proportionality constant as in the region A. When the peak amplifier circuit 5 starts to operate, the efficiency once decreases, but reaches a peak again at the compression point at which the peak amplifier circuit 5 also starts to saturate. At the compression point, the outputs of the carrier amplifier circuit 4 and the peak amplifier circuit 5 are equal.

  In general, a CDMA signal and a multicarrier signal have a high peak factor, that is, a ratio of peak power to average power. However, in a normal amplifier, a point corresponding to 7 to 12 dB is reduced from the compression point. Is the operating point.

Returning to FIG. 15, the impedance of each part will be described. Since the output load Z ₀ is defined to be constant, this is the starting point. The impedance Z ₇ when the λ / 4 transformer ₇ is viewed from the node 62 is Z ₂ , where the characteristic impedance of the λ / 4 transformer 7 is Z ₂ .
Z ₇ = Z ₂ ² / Z ₀
It becomes.

The impedance Z _{4 when the} λ / 4 transformer 61 is viewed from the output matching circuit 43 is obtained in the same manner as described above because the output impedance of the output matching circuit 53 is substantially infinite in the A region, and the input signal level is high. Since the load is equally shared in the C region, the load impedance of the λ / 4 transformer 61 (contribution of the amplifier circuit 4 at the node 62) and the load impedance of the output matching circuit 53 are 2Z ₇ respectively.

It becomes. Where Z ₁ is the characteristic impedance of the λ / 4 transformer 61. Impedances Z ₄ and Z ₅ each transition between a value in the A region and a value in the C region in the B region.

  Further, a case where the Doherty amplifier is applied to a high frequency region will be described below.

That is, the impedance Z ₄ whereas the impedance value when the level of the input signal is small (A region), halved but when the input signal level greater (C region), causing twice the load fluctuation in other words. For example, when Z ₇ = 25Ω and Z ₁ = 50Ω, Z ₄ changes between 100 and 50Ω. Therefore, the load impedance of the amplifying element 42 also varies.

  The Doherty amplifier described above has a drawback that the output power in the saturation region is lower than that of a class AB balanced amplifier as shown in FIG. The balanced amplifier of FIG. 17 distributes the signal input from the input terminal 200 to the two amplifier circuits 210 and 220 by the distributor 201, combines the signals amplified by the amplifier circuits 210 and 220 by the combiner 202, The output is supplied from the output terminal 203 to the output load 204. The amplifier circuit 210 includes an input matching circuit 211, an amplifier element 212 biased to class AB, and an output matching circuit 213. The amplifier circuit 220 has an input matching circuit 221 and an amplifier element 222 biased to class AB, and an output. The matching circuit 223 is used.

  The output power in the saturation region of the Doherty amplifier is smaller than the balanced amplifier biased to class AB. This is because the output power in the saturation region of the Doherty amplifier is a combination of the class AB carrier amplifier circuit 4 and the class C peak amplifier circuit 5, and the class C has a lower gain than the class AB. This reduction in output power in the saturation region can be dealt with by adding and synthesizing more amplifiers. However, more amplifiers are required compared to balanced amplifiers, resulting in higher costs.

  As a method for improving the power reduction in the saturation region of the Doherty amplifier, a Doherty amplifier as shown in FIG. 18 in which the deterioration of characteristics is compensated by controlling the gate bias voltage of the peak amplifier circuit according to the input level is considered. It has been. The difference between this Doherty amplifier and the conventional Doherty amplifier shown in FIG. 15 is that a directional coupler 17 is provided between the input terminal 1 and the distributor 2, and the signal extracted from the directional coupler 17 is peak amplified. This is the point that the bias of the peak amplification circuit 5 is controlled by inputting to the gate bias control circuit 18 of the circuit 5.

  The gate bias control circuit 18 diode-detects the signal obtained from the directional coupler 17 and outputs a gate bias voltage such as a gate bias voltage control characteristic shown in FIG. In the A region where the input level is low, the peak amplifying circuit 5 is operated in class C, so that it is the same as the conventional Doherty amplifier. Because of class operation, saturation power equivalent to that of a class AB balanced amplifier can be obtained. The B region has a characteristic that makes a transition between the value in the A region and the value in the C region. By such gate bias control, it is possible to realize a Doherty amplifier that is highly efficient and does not reduce saturation power.

  The gate bias control circuit 18 may be an analog circuit based on diode detection, but it is difficult to realize the same gate bias characteristics due to variations in individual characteristics of the diodes when the product is commercialized, and the characteristics are substantially adjusted by adjustment. Even if it is fixed, the manufacturing cost increases due to the adjustment man-hours. As a method for solving this problem, it is easily conceivable to realize the gate bias control circuit 18 with a digital circuit.

  FIG. 20 is a block diagram illustrating a configuration when a Doherty amplifier including a gate bias control circuit using a digital circuit is applied to a transmitter. The baseband I-phase signal (in-phase component) and the baseband Q-phase signal (quadrature component) are input from the input terminals 231 and 232 to the digital quadrature modulator 234 via the digital predistorter 233 that performs distortion compensation. The quadrature modulator 234 includes multipliers 235 and 236, an NCO (Numerical Controlled Oscillator) 237 and an adder 238, and modulates the distortion-compensated signal by the predistorter 233. The signal modulated by the quadrature modulator 234 is converted from a digital signal to an analog signal by a D / A converter 239 and input to an up-converter 241 via a low-pass filter (LPF) 240 to be converted into an RF signal (high-frequency signal). Converted. This RF signal is amplified by the driver amplifier 242 and then input to the input terminal 1 of the Doherty amplifier 243. Since this Doherty amplifier 243 has the same configuration as that shown in FIG. 18, a detailed description thereof will be omitted.

The baseband I-phase signal and the baseband Q-phase signal output from the predistorter 233 are input to the power detector 244, and the envelope is calculated by the calculation of “√ (I ² + Q ² )”. The calculation result of the power detector 244 is input to an LUT (Look Up Table) 245 in which gate bias control characteristics are stored. The gate bias control signal output from the LUT 245 is converted from a digital signal to an analog signal by the D / A converter 246, and then the peak amplification circuit of the Doherty amplifier 243 via the low-pass filter (LPF) 247 and the buffer amplifier 248. 5 to control the bias. A signal output from the output terminal 8 of the Doherty amplifier 243 is supplied to the load 9.

  Another advantage of realizing the gate bias control circuit 18 with a digital circuit is that the bias control can be freely set by writing the gate bias control characteristic into the LUT 245.

  A part of the output signal of the Doherty amplifier 243 is branched out by the directional coupler 251 and converted into an IF signal by the down converter 252. This IF signal is input to the A / D converter 254 via the low-pass filter 253, converted from an analog signal to a digital signal, and sent to the distortion detection circuit 255. The distortion detection circuit 255 detects distortion from the signal sampled by the A / D converter 254 and outputs the detection signal to the control circuit 256. The control circuit 256 adaptively controls the predistorter 233 so that the distortion detected by the distortion detection circuit 255 is reduced.

Further, as a known technique related to the present invention, in a Doherty amplifier comprising a main amplifier and an auxiliary amplifier, the bias of the auxiliary amplifier is controlled to reduce the occurrence of distortion, and it is not necessary to widen the bandwidth of the input signal. An amplifier with a distortion control function is known (for example, refer to Patent Document 1).
US Patent Application Publication No. 2006/0049870

  Distortion compensation when a general Doherty amplifier and a general distortion compensator are combined is degraded as compared with the distortion compensation amount of a conventional AB class amplifier. Since the gain near saturation is reduced, the nonlinearity becomes larger than that of the AB class amplifier, and it is difficult to bring out the efficiency to the limit due to the deterioration of the intermodulation distortion after distortion compensation.

  Further, in the conventional Doherty amplifier, as the efficiency is improved, the AM-AM (input amplitude level to output amplitude level) conversion characteristic and the AM-PM (input amplitude level to output phase rotation amount) conversion characteristic deteriorate. Further, the amplifier with the distortion control function has a problem that the distortion is not sufficiently reduced and the efficiency cannot be brought out to the limit.

  In the transmitter shown in FIG. 20, the baseband I-phase signal and Q-phase signal from the input terminals 231 and 232 are branched to the multipliers 235 and 236 via the predistorter 233 and converted into RF signals. The delay time τ1 until the signal is input to the gate terminal of the amplifying element 52 in the peak amplifying circuit 5 (when the amplifying element 52 is configured by an FET) and the signal branched from the predistorter 233 to the power detector 244 are gate biased. If there is a difference in the delay time τ 2 until it becomes a control signal and reaches the gate terminal of the amplifying element 52 in the peak amplifier circuit 5, a timing shift occurs between the RF signal and the gate bias control signal, and in addition to the distortion of the Doherty amplifier 243. There is a problem that distortion due to timing deviation occurs.

  The distortion caused by the timing difference between the RF signal and the gate bias control signal will be described below. For example, FIG. 21 shows an image waveform when the delay time τ1 of the RF signal from the IQ baseband signal to the gate terminal of the amplifying element 52 in the peak amplifier circuit 5 is different from the delay time τ2 of the gate bias control signal. Shown in FIG. 21A is an image waveform when “τ1 = τ2”, and FIG. 21B is an image waveform when “τ1 <τ2”, which are an RF signal envelope and a time waveform of a gate bias control signal, respectively. The horizontal axis represents time, and the vertical axis represents amplitude.

  (A) In “τ1 = τ2”, there is no shift in timing between the RF signal and the gate bias control signal. In (b) “τ1 <τ2,” the RF signal is shifted due to a shift in timing between the RF signal and the gate bias control signal. There is a difference between the gate bias voltage when the envelope amplitude increases with time and the gate bias voltage when it decreases with time. This is because when the RF signal increases and decreases, the operation class of the peak amplifier circuit 5 is different, which causes distortion.

  In general, an amplifier has a difference in gain and distortion characteristics (AM-AM characteristics, AM-PM characteristics) depending on an operation class (gate bias voltage), and therefore, an amplifier is classified into an operation class when an RF signal increases and decreases. If there is a difference, distortion will increase.

  When the gate bias control circuit is realized by a digital circuit, it can be adjusted in units of the clock frequency of the digital circuit in order to correct this timing shift. That is, in “τ1 <τ2” in FIG. 21B, in order to increase the delay time of the RF signal, for example, by adding a flip-flop after the adder 238, τ1 can be brought close to τ2. is there. In addition, a delay line such as a coaxial line is disposed after the D / A converter 239, and the delay times τ1 and τ2 can be matched with an analog signal.

  However, the adjustment of the delay time by the flip-flop of the digital circuit can be adjusted only in units of the clock frequency of the digital circuit. Also, adjusting the delay time with the delay line of the analog circuit generally increases the line length, which is disadvantageous in terms of miniaturization and cost reduction.

  The present invention has been made in order to solve the above-described problem. The distortion compensation amount in the case of combining a general Doherty amplifier and a distortion compensator can be brought close to the distortion compensation amount of the AB class amplifier, thereby limiting the efficiency. An object of the present invention is to provide an amplifying apparatus with a distortion control function that can be pulled out to a maximum.

  In addition, the present invention provides an amplification device with a distortion control function capable of accurately adjusting a timing shift between an RF signal and a gate bias control signal when a Doherty amplifier having a gate bias control function and a distortion compensator are combined. For the purpose.

An amplification device with a distortion control function according to a first aspect of the present invention includes a carrier amplification circuit including an amplification element that operates in class AB, and a peak including an amplification element whose amplification operation is controlled by a control signal input from a control terminal. A Doherty amplifier comprising: an amplifier circuit; and a combining unit that combines and outputs the signals amplified by the carrier amplifier circuit and the peak amplifier circuit;
A predistorter that compensates for non-linear distortion of the Doherty amplifier; a distortion detection unit that detects intermodulation distortion included in an output signal of the Doherty amplifier; and the distortion value detected by the distortion detection unit is reduced. The predistorter is controlled, the bias of the peak amplifier circuit is arbitrarily controlled according to the distortion value detected by the distortion detector and the input signal level of the Doherty amplifier, and the input amplitude level pair of the Doherty amplifier is controlled. And a predistortion distortion compensation circuit including a control unit that controls the output amplitude level conversion characteristics to approach class AB.

An amplifying apparatus with a distortion control function according to a second aspect of the present invention includes a carrier amplifying circuit including an amplifying element that operates in class AB, and an amplifying element whose amplifying operation is controlled by a bias control signal input from a control terminal. A Doherty amplifier comprising a peak amplifying circuit and combining means for combining and outputting the signals amplified by the carrier amplifying circuit and the peak amplifying circuit;
For an input signal to be amplified, a predistorter that compensates for non-linear distortion generated in the Doherty amplifier, and a signal compensated by the predistorter is converted into a high-frequency signal and input to a signal input terminal of the Doherty amplifier. A signal output from the first signal system and the predistorter is branched and extracted, a bias control signal is generated based on the level of the signal and a preset bias control characteristic, and the control terminal of the Doherty amplifier A second signal system that is input to the signal, a delay adjustment circuit provided in at least one of the first signal system and the second signal system, and distortion detection that detects intermodulation distortion included in the output signal of the Doherty amplifier And a signal of the delay adjustment circuit that controls the predistorter so that a distortion value detected by the distortion detector decreases. Characterized in that it has a control unit for controlling the extension amount.

  According to the first aspect of the invention, the predistorter is controlled so that the distortion value detected by the distortion detection unit becomes small, and the peak is determined according to the distortion value detected by the distortion detection unit and the input signal level of the Doherty amplifier. Distortion compensation when combining a general Doherty amplifier and predistorter by arbitrarily controlling the bias of the amplifier circuit and controlling the input amplitude level to output amplitude level conversion characteristic of the Doherty amplifier to approach class AB The amount can be brought close to the distortion compensation amount of the AB class amplifier, and the efficiency can be brought out to the limit. Also, variations in distortion compensation amount can be absorbed by arbitrarily changing the bias.

  According to the second aspect of the present invention, the delay adjustment circuit is provided in at least one of the first signal system that transmits the high-frequency signal to the Doherty amplifier and the second signal system that transmits the bias control signal, and is detected by the distortion detector. By adjusting the signal delay amount of the delay adjustment circuit so as to reduce the distortion value, the timing difference between the high-frequency signal in the first signal system and the bias control signal in the second signal system is eliminated, and the occurrence of distortion is suppressed. be able to.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of an amplification device with a distortion control function according to a first embodiment of the present invention, which is configured by combining a predistortion distortion compensation circuit 100 and a Doherty amplifier 20. FIG. 2 is a block diagram showing a detailed configuration of the Doherty amplifier 20.

  As shown in FIG. 1, the input signal to the predistortion distortion compensation circuit 100 is input from the input terminal 101 to the predistorter 102. The predistorter 102 has the same configuration as that shown in FIG. The predistorter 102 compensates for the nonlinear distortion of the input signal and outputs it to the D / A converter 103. The D / A converter 103 converts the digital signal into an analog signal in synchronization with the clock signal CLK 1 and outputs the analog signal to the quadrature modulator 104. This quadrature modulator 104 performs quadrature modulation on the input signal with the signal from the oscillator 105 and outputs it to the Doherty amplifier 20 via the delay correction circuit 161. The delay correction circuit 161 is for delaying the modulation signal in accordance with the delay of the signal in the control unit 117 described later, and is configured by, for example, a transmission line or a delay filter. The modulated wave subjected to delay correction by the delay correction circuit 161 is amplified by the Doherty amplifier 20 and output from the output terminal 107.

  A part of the output signal of the Doherty amplifier 20 is taken out via the directional coupler 108 and input to the mixer 109. The mixer 109 down-converts the signal extracted from the directional coupler 108 to the IF frequency based on the oscillation frequency from the oscillator 110. The IF signal down-converted by the mixer 109 is converted into a digital signal by the A / D converter 111 and sent to the distortion detector 112. The distortion detection unit 112 includes a fast Fourier transform circuit (FFT) 113 and an IM operation circuit 114, obtains a distortion value of the signal output from the Doherty amplifier 20, and outputs the distortion value to the control unit 117.

  A part of the modulation signal output from the quadrature modulator 104 is extracted via the directional coupler 162 and input to the detection circuit 163. The detection circuit 163 is a general detection circuit configured by, for example, a Schottky diode, and outputs a voltage corresponding to the magnitude of the modulated wave power. The voltage output from the detection circuit 163 is converted from an analog signal to a digital signal by the A / D converter 164 and sent to the control unit 117. The A / D converter 164 converts the voltage (analog signal) output from the detection circuit 163 into a digital signal in synchronization with the clock signal CLK3.

  The control unit 117 adaptively controls the predistorter 102 so that the distortion value detected by the distortion detection unit 112 becomes small, and the intermodulation distortion detected by the distortion detection unit 112 becomes a target value. The signal sent from the detection circuit 163 via the A / D converter 164 is used as it is, or arbitrarily (for example, if the detection voltage in FIG. The bias of the Doherty amplifier 20 is controlled with a voltage changed to make the slope steep, gentle, or move the C region up and down, thereby improving the distortion compensation amount. In this case, a control signal (digital signal) for the Doherty amplifier 20 output from the control unit 117 is converted into an analog signal in synchronization with the clock signal CLK4 by the D / A converter 116 and sent to the Doherty amplifier 20, 2, the signal is input to the gate terminal 11 of the amplifying element 52 in the peak amplifying circuit 5. Further, the control unit 117 controls the bias of the Doherty amplifier 20 based on the signal sent from the detection circuit 163 via the A / D converter 164, and improves the distortion compensation amount.

  That is, the control unit 117 changes the bias voltage of the amplification element 52 in the peak amplification circuit 5 according to the signal level input from the detection circuit 163 via the A / D converter 164 while performing distortion compensation. As a result, a decrease in gain near saturation is compensated for, and non-linearity capable of compensating for distortion equivalent to that of an AB class amplifier is ensured.

Next, a detailed configuration of the Doherty amplifier 20 will be described with reference to FIG.
A signal modulated by the quadrature modulator 104 shown in FIG. 1 is input to the input terminal 1 of the Doherty amplifier 20. The signal input to the input terminal 1 is distributed by the distributor 2, and one of the signals is input to the carrier amplifier circuit 4. The carrier amplifier circuit 4 includes an amplifier element 42, an input matching circuit 41 that matches the input side of the amplifier element 42, and an output matching circuit 43 that matches the output side of the amplifier element 42. The output of the carrier amplifier circuit 4 is impedance-converted by a λ / 4 transformer 61.

  The other signal distributed by the distributor 2 is delayed by 90 degrees in the phase shifter 3 and input to the peak amplifier circuit 5. The peak amplifying circuit 5 includes an amplifying element 52, an input matching circuit 51 that matches the input side of the amplifying element 52, and an output matching circuit 53 that matches the output side of the amplifying element 52. The amplification element 52 includes a gate terminal 11 as a control terminal, and a gate bias voltage output from the D / A converter 116 shown in FIG. As the amplifying elements 42 and 52, semiconductor devices such as LD-MOS (Lateral Diffused MOS), GaAs-FET, HEMT, and HBT are usually used. When an FET is used as the amplifying element 52, the operation is controlled by the gate bias voltage. However, when a transistor is used as the amplifying element 52, the operation is controlled by the base bias voltage.

The outputs of the λ / 4 transformer 61 and the peak amplifier circuit 5 are combined at a node 62. The λ / 4 transformer 61 and the node 62 constitute a Doherty synthesizer 6. The signal synthesized at the node 62 is impedance-converted by the λ / 4 transformer 7 to match the output load Z ₀ , and sent to the output terminal 107 shown in FIG.

Next, the operation of the amplification device with a distortion control function according to the above embodiment will be described.
The signal input from the input terminal 101 is compensated for nonlinear distortion by the predistorter 102, converted to an analog signal by the D / A converter 103, and then orthogonally modulated by the orthogonal modulator 104. The signal modulated by the quadrature modulator 104 is delay-corrected by the delay correction circuit 161 in accordance with the processing time of the control unit 117, amplified by the Doherty amplifier 20, and output from the output terminal 107.

  At this time, a part of the signal amplified by the Doherty amplifier 20 is taken out through the directional coupler 108, down-converted to an IF frequency by the mixer 109, and then converted into a digital signal by the A / D converter 111. It is sent to the distortion detector 112. The distortion detector 112 obtains the spectrum of the IF signal by the fast Fourier transform circuit 113, and then IM3 (third-order intermodulation distortion) calculated from the number of carriers of the modulation signal and its detuning frequency by the IM arithmetic circuit 114, A power value at a frequency of IM5 (fifth-order intermodulation distortion) is set as a distortion value. The control unit 117 adaptively controls the predistorter 102 so that the distortion value detected by the distortion detection unit 112 becomes small.

A control operation for the predistorter 102 by the control unit 117 will be described with reference to a flowchart shown in FIG.
First, initial setting is performed on the update target coefficient, the set number of times, the previous distortion value, the gate bias voltage (a ₀ , b ₀ , c ₀ in FIG. 4) for the amplification element 52 in the peak amplification circuit 5 (step A1). ). For example, the coefficient K to be updated is set to φ3, and the distortion value calculated by the distortion detector 112 is compared with the previous distortion value (step A2). If the distortion value is smaller than the previous value, the coefficient is further updated in the same direction, that is, the coefficient is updated by the process of “K = K + Step” (step A4), and if the distortion value is larger, “ The update direction is reversed by the processing of “Step = Step * (− 1)” (step A3), and then the process proceeds to step A4 to update the coefficient. Next, it is counted how many times the same coefficient φ3 has been continuously updated (step A5), and the detected distortion value is stored (step A6). This stored distortion value is used in the next distortion value comparison. When the stored distortion value becomes a distortion value almost equal to the target value or the AB class, the parameter is fixed. However, when the current distortion value starts to deteriorate, the process starts again from step A2.

Next, the number of updates is compared with a preset number of times (step A7). If the number of updates is equal to or less than the set number, the process returns to step A2 and the coefficient update of φ3 is repeated. When the number of updates exceeds the set number, the update target coefficient is changed (step A8). That is, the coefficient K is changed from φ3 to A3, and the number of updates is cleared (step A9). Then, it returns to step A2 and repeats said operation | movement. Furthermore, when the distortion value is almost converged (the distortion value does not become smaller than the previous distortion value: it can be found by monitoring A2), the gate bias voltage for the amplifying element 52 in the peak amplifying circuit 5 is moved (in the areas A to C). a ₀ , a ₁ , a ₂ , b ₀ , b ₁ , b ₂ , c ₀ , c ₁ , c ₂ are arbitrarily changed) (step A10). Thereafter, the conventional operation is repeated again. The control unit 115 controls the coefficient of the predistorter 102 and the gate bias voltage for the amplifying element 52 in the peak amplifying circuit 5 so that the distortion value is reduced by such a control flow.

  The nonlinear distortion of the Doherty amplifier 20 can be compensated by approximating the nonlinear inverse characteristics of the amplifier by the predistorter 102 using a power series by the perturbation method as described above. Although omitted in FIG. 2 for ease of explanation, a drive amplifier may be provided before the Doherty amplifier 20, or a drive amplifier may be provided after the quadrature modulator 104. In addition, there are other optimal algorithms that are not specified.

  Further, the control unit 117 extracts a part of the modulation signal output from the quadrature modulator 104 via the directional coupler 162 and detects it by the detection circuit 163 in accordance with the magnitude of the power of the modulation wave. The A / D converter 164 converts the analog signal into a digital signal and inputs it. The control unit 117 controls the gate bias voltage of the amplification element 52 in the peak amplification circuit 5 according to the distortion value detected by the distortion detection unit 112 and the signal level input from the detection circuit 163 via the A / D converter 164. As shown in the control characteristic of FIG. 4, the AM-AM conversion characteristic of the Doherty amplifier 20 is brought close to the class AB to compensate for a decrease in gain near saturation, and the nonlinearity capable of compensating for distortion equivalent to the class AB amplifier. Ensure sex.

FIG. 4 shows an example of controlling the gate bias voltage for the amplifying element 52 in the peak amplifying circuit 5 (examples of a ₀ , b ₀ , c _{0 in} FIG. 4), and the horizontal axis represents the input power (dBm). The vertical axis represents the output voltage (V). The control unit 117 maintains the gate bias voltage at a low level as shown in the area A of FIG. 4 until the power of the modulation signal output from the quadrature modulator 104 is in a low level range, that is, until the Doherty amplifier 20 starts to saturate. When the Doherty amplifier 20 begins to saturate, the gate bias voltage is increased according to the input power as shown in the B region, and when the Doherty amplifier 20 reaches the saturation point, the increase in the gate bias voltage is suppressed as shown in the C region. Control characteristics.

  When the gate bias voltage of the amplifying element 52 output from the control unit 117 is changed as shown in the characteristic diagram shown in FIG. 4, the gain near the saturation of the Doherty amplifier 20 is shown in the AM-AM conversion characteristic of FIG. It can be equivalent to an AB class amplifier. FIG. 4 shows an example of gate bias control for the amplifying element 52, which can be converted into an arbitrary control characteristic by the control unit 117.

  FIG. 5 shows an example of AM-AM conversion characteristics of the Doherty amplifier and the AB class amplifier. The horizontal axis represents input (dBm), and the vertical axis represents gain (dB). In FIG. 5, a is the AM-AM conversion characteristic of the Doherty amplifier 20 in the above embodiment, b is the AM-AM conversion characteristic of a general Doherty amplifier, and c is the AM-AM conversion characteristic of the AB class amplifier. In a general Doherty amplifier, when the level of an input signal increases as shown by the characteristic b, the input power is saturated at a relatively low level. On the other hand, the Doherty amplifier 20 shown in the above embodiment controls the gate bias voltage of the amplifying element 52 even when the level of the input signal increases and reaches the vicinity of saturation of a general Doherty amplifier as shown by the characteristic a. By compensating for the decrease in gain, it is possible to obtain a characteristic equivalent to the characteristic c of the AB class amplifier.

FIG. 6 shows an example of distortion compensation characteristics of the Doherty amplifier and the AB class amplifier, where a is the distortion compensation characteristic of the Doherty amplifier 20 in the above embodiment, b is the distortion compensation characteristic of a general Doherty amplifier, and c is the AB class. This is a distortion compensation characteristic of the amplifier. In FIG. 6, f ₀ is the center frequency. As apparent from FIG. 6, the distortion compensation of the Doherty amplifier 20 according to the above embodiment can be equivalent to the distortion compensation of the AB class amplifier.

  As shown in the above embodiment, the predistorter 102 is controlled so that the distortion value of the Doherty amplifier 20 detected by the distortion detection unit 112 becomes small, and the distortion value detected by the distortion detection unit 112 and the directional coupling are controlled. The bias of the peak amplifier circuit 5 is controlled in accordance with the input signal level of the Doherty amplifier 20 detected by the detector 162, the detector circuit 163, and the A / D converter 164, and the AM-AM conversion characteristics of the Doherty amplifier 20 are set to class AB. By controlling so as to approach, the distortion compensation amount when a general Doherty amplifier and a distortion compensator are combined can be brought close to the distortion compensation amount of the AB class amplifier, and the efficiency can be drawn to the limit.

Note that the predistortion distortion compensation circuit 100 in the above embodiment shows an example, and may have other configurations.
The Doherty amplifier 20 is also an example, and may have other configurations.
(Second Embodiment)
Next, an amplifying apparatus with a distortion control function according to a second embodiment of the present invention will be described.
FIG. 7 is a block diagram showing a configuration when the amplifying apparatus with a distortion control function according to the second embodiment of the present invention is applied to a transmitter. In the amplifying apparatus according to the second embodiment, in the transmitter shown in FIG. 20, a first coarse adjustment delay circuit 261 is provided between an adder 238 and a D / A converter 239 in the quadrature modulator 234. , A second coarse adjustment delay circuit 262 and a fine adjustment delay circuit 263 are provided between the LUT 245 and the D / A converter 246, and the first coarse adjustment delay circuit 261, the second coarse adjustment delay circuit 262, and the fine adjustment delay circuit 262 are provided. The delay amount of the adjustment delay circuit 263 is controlled by a control signal from the control circuit 256A. Since other configurations are the same as those of the transmitter shown in FIG. 20, the same parts are denoted by the same reference numerals, and detailed description thereof is omitted.

  The first coarse adjustment delay circuit 261 and the second coarse adjustment delay circuit 262 adjust the delay in units of the clock frequency of the digital circuit, and are configured as shown in FIG. Further, the fine adjustment delay circuit 263 adjusts the clock frequency in units or less, and is configured as shown in FIG.

  As shown in FIG. 8, the first coarse adjustment delay circuit 261 and the second coarse adjustment delay circuit 262 receive a signal input from the previous stage circuit to the input terminal 271 by a plurality of stages of flip-flops 272a to 272n in units of clocks. The outputs of the flip-flops 272a to 272n are input to the selector 273 with delay. The selector 273 is supplied with a control signal from the control circuit 256A via the control terminal 274. The selector 273 selects from the output signals of the flip-flops 272a to 272n a signal delayed by the clock instructed by the control signal from the control circuit 256A, and outputs it from the output terminal 275.

  As described above, the first coarse adjustment delay circuit 261 and the second coarse adjustment delay circuit 262 delay each clock unit by an amount instructed by the control circuit 256A.

  Further, the fine adjustment delay circuit 263 is configured using a FIR (Finite Response Filter) filter. As shown in FIG. 9, a signal input from the preceding circuit to the input terminal 281 is input into a plurality of stages of flip-flops 282a to 282n. The multipliers 284a to 284n multiply the delayed signals by the multipliers 284a to 284n, add the multiplication results by the adder 285, and output the result from the output terminal 286. .

  The operation of the delay circuit using the FIR filter will be described with reference to FIG.

  FIG. 10 shows an impulse response of the low-pass filter. In order to realize this filter characteristic by the FIR filter, for example, a black dot may be set as a coefficient at the coefficient input terminal 283 in FIG.

  In the fine adjustment delay circuit 263, in order to perform delay adjustment in units shorter than the clock frequency unit which is the object here, as shown by the white circles in FIG. Is set to the coefficient input terminal 283 in FIG. Using the black circle in FIG. 10 as a reference, the white circle is delayed by a half cycle of the clock frequency. Here, a half cycle of the clock frequency is taken as an example. However, if a coefficient obtained by sampling a point shifted by a 1/4 cycle from the black circle is set in the coefficient input terminal 283, the clock frequency can be delayed by 1/4. It becomes possible.

  As described above, by changing the sampling phase of the impulse response in the FIR filter, the delay amount can be controlled in units shorter than the clock frequency. The result of sampling with the required accuracy is stored in the memory as a coefficient of the FIR filter, and by switching the coefficient, the delay amount can be controlled in units of clock frequency or less.

  In the embodiment shown in FIG. 7, the fine adjustment delay circuit 263 is arranged after the second coarse adjustment delay circuit 262 on the gate bias control circuit side, but the first coarse adjustment delay on the RF signal side is arranged. You may arrange | position in the back | latter stage of the circuit 261.

  The coarse adjustment delay circuits 261 and 262 and the fine adjustment delay circuit 263 may be arranged anywhere from the branch point of the output of the predistorter 233 to the D / A converters 239 and 246. If it is known in advance whether the delay time τ1 of the RF signal or the delay time τ2 of the gate bias control signal is larger, the coarse adjustment delay circuit having the larger delay time is deleted, and the delay time is decreased. A coarse adjustment delay circuit and a fine adjustment delay circuit may be arranged.

  Next, adjustment of delay times of the coarse adjustment delay circuits 261 and 262 and the fine adjustment delay circuit 26 will be described with reference to FIG. FIG. 11A is an explanatory diagram in the case of τ1 <τ2, and FIG. 11B is an explanatory diagram in the case of τ1> τ2.

  In the case of τ1 <τ2 in FIG. 11A, the delay time τ1 is “3” and the delay time τ2 is “6.5” when the clock cycle is taken as one unit. In order to make τ1 and τ2 coincide with each other, a delay of “4” is generated by the first coarse adjustment delay circuit 261 and “0.5” is generated by the fine adjustment delay circuit 263, so that “τ1 = τ2 = 7”. The distortion due to the timing difference between the RF signal and the gate bias control signal in the gate bias control system of the Doherty amplifier can be suppressed.

  11A to 11G show distortion values when the delay amount D1 of the first coarse adjustment delay circuit 261 is changed. The distortion value decreases as the delay amount D1 of the first coarse adjustment delay circuit 261 is increased (closer to τ1 = τ2), but the distortion value increases when τ1> τ2. At this point, the delay amount D3 of the fine adjustment delay circuit 263 is controlled to perform delay adjustment in units of clocks or less.

  In the case of τ1> τ2 in FIG. 11B, the delay time τ1 is “6.5” and the delay time τ2 is “3”. In order to make τ1 and τ2 coincide with each other, a delay of “3” is generated by the second coarse adjustment delay circuit 262 and “0.5” is generated by the fine adjustment delay circuit 263, thereby “τ1 = τ2 = 6.5. Can be adjusted.

  Further, (b) -g in FIG. 11 shows a distortion value when the delay amount D2 of the second coarse adjustment delay circuit 262 is changed, and when the delay amount D2 is increased from 0 by one. Although the strain value decreases, the strain value increases when τ1 <τ2. Here, in FIG. 11B, after subtracting “1” from the delay amount D2, the delay amount D3 of the second coarse adjustment delay circuit 262 is controlled to perform delay adjustment in units of clocks or less.

  Next, the control operation of the control circuit 256A for the first coarse adjustment delay circuit 261, the second coarse adjustment delay circuit 262, and the fine adjustment delay circuit 263 will be described with reference to the control flow of FIG. The parameters used in this control flow are defined as follows. The delay amount of the first coarse adjustment delay circuit 261 is D1, the delay amount of the second coarse adjustment delay circuit 262 is D2, and the delay amount of the fine adjustment delay circuit 263 is D3. I in I) is an index representing the order of detection, and I = 1 represents the first detected strain value as strain value (1).

  As described with reference to FIG. 11, since the control method is different between (a) τ1 <τ2 and (b) τ1> τ2, it is first determined which of τ1 and τ2 has the larger delay amount.

  In the initial value setting (step B1), for each delay amount D1 to D3, D1 = 0, D2 = 0, D3 = 0 and initial parameter values are set, and the distortion value (1) is read (step B2). = 1 (step B3), the strain value (2) is read again (step B4).

  Next, the distortion value (1) when D1 = 0 and the distortion value (2) when D1 = 1 are compared (step B5). If distortion value (2) <distortion value (1), It is sufficient to increase the delay amount D1 of one coarse adjustment delay circuit 261. Therefore, in this case, the calculation of D1 = D1 + 1 (step B6), reading of the distortion value (I) (step B7), distortion value (I) <distortion value (I-1) (step B8), It repeats until it becomes No in determination of step B8.

  If the determination result in Step B8 is No, the adjustment of the delay amount D1 of the first coarse adjustment delay circuit 261 in units of clocks has been completed, and the process proceeds to the control of the fine adjustment delay circuit 263 from Step B15. .

  If the determination result in Step B5 is No, the delay amount D2 of the second coarse adjustment delay circuit 262 may be increased. However, since D1 = 1 in Step B3, D1 = 0. (Step B9), the distortion value (I) is read (step B10), and then the delay amount D2 of the second coarse adjustment delay circuit 262 is controlled. That is, the calculation of D2 = D2 + 1 (step B11), reading of the distortion value (I) (step B12), distortion value (I) <distortion value (I-1) (step B13) is performed in the determination of step B13. Repeat until No.

  If the determination result in Step B13 is No, the adjustment of the delay amount D2 of the second coarse adjustment delay circuit 262 in units of clocks has been completed, but it is necessary to subtract “1” as described in FIG. Therefore, the process of “D2 = D2-1” is performed in step B14, and the process proceeds to control of the fine adjustment delay circuit 263 from step B15.

  After reading the distortion value (I) in step B15, calculation of D3 = D3 + 0.1 (step B16), reading of the distortion value (I) (step B17), distortion value (I) <distortion value (I -1) The process of (Step B18) is repeatedly executed until No is determined in the determination of Step B18.

  In step B16, D3 = D3 + 0.1 is an example on the assumption that the coefficient of the FIR filter in the fine adjustment delay circuit 263 is set so that it can be controlled in units of 1/10 of the clock. If the determination result in Step B18 is No, it can be said that the previous value is closest to the condition of τ1 = τ2 and the distortion value is small. Therefore, in Step B19, the calculation of D3 = D3-0.1 is performed. The process ends.

  By performing the above processing, it is possible to suppress the occurrence of distortion due to the timing difference between the RF signal and the gate bias control signal. Thereafter, distortion compensation of the Doherty amplifier is performed by the predistorter 233.

  Therefore, according to the second embodiment, the delay adjustment for suppressing the distortion due to the timing shift between the RF signal and the gate bias control signal in the gate bias control system of the Doherty amplifier can be realized with high accuracy and at low cost. Is possible.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage.

1 is a block diagram showing an overall configuration of an amplification device with a distortion control function according to a first embodiment of the present invention. It is a block diagram which shows the detailed structure of the Doherty amplifier in the same embodiment. It is a flowchart which shows the processing operation of the control part in the embodiment. In the same embodiment, it is a figure which shows the example of control of the gate bias voltage with respect to the amplification element in a peak amplifier circuit. It is a figure which shows the AM-AM conversion characteristic example of the Doherty amplifier and AB class amplifier in the same embodiment. It is a figure which shows the example of a distortion compensation characteristic of the Doherty amplifier and AB class amplifier in the same embodiment. It is a block diagram which shows the structure at the time of applying the amplifier with a distortion control function which concerns on 2nd Embodiment of this invention to a transmitter. It is a block diagram which shows the structure of the 1st and 2nd coarse adjustment delay circuit in the embodiment. It is a block diagram which shows the structure of the fine adjustment delay circuit in the same embodiment. It is an impulse response waveform diagram of the low-pass filter for explaining the operation of the delay circuit by the FIR filter in the same embodiment. It is a figure for demonstrating the adjustment operation of the delay time of the 1st and 2nd coarse adjustment delay circuit in the same embodiment, and a fine adjustment delay circuit. 6 is a flowchart showing control operations of the first and second coarse adjustment delay circuits and the fine adjustment delay circuit in the same embodiment. It is a block diagram which shows the structure of the power amplifier which performed the conventional predistortion distortion compensation. It is a block diagram which shows the structure of the predistorter in the power amplification apparatus of FIG. It is a block diagram which shows the structure of the conventional Doherty amplifier. It is a figure which shows the theoretical collector efficiency thru | or drain efficiency in the conventional Doherty amplifier. It is a block diagram which shows the structure of the conventional class AB balanced amplifier. It is a block diagram which shows the structure of the Doherty amplifier by a gate bias control system. It is a characteristic view which shows an example of a gate bias control characteristic. It is a block diagram which shows the structure at the time of applying the Doherty amplifier provided with the gate bias control circuit to a transmitter. 20A is a diagram illustrating an envelope of an RF signal and a time waveform of the gate bias control signal when the delay time τ1 of the RF signal is equal to the delay time τ2 of the gate bias control signal in the transmitter of FIG. FIG. 5 is a diagram illustrating an envelope of an RF signal and a time waveform of a gate bias control signal when the delay time τ1 of the RF signal is smaller than the delay time τ2.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... Divider, 3 ... Phase shifter, 4 ... Carrier amplifier circuit, 5 ... Peak amplifier circuit, 6 ... Doherty synthesis part, 7 ... Transformer, 8 ... Output terminal, 9 ... Load, 11 ... Gate terminal 20 ... Doherty amplifier 41 ... Input matching circuit 42 ... Amplifying element 43 ... Output matching circuit 51 ... Input matching circuit 52 ... Amplifying element 53 ... Output matching circuit 61 ... Transformer 62 ... Node (Composite point), 100 ... predistortion distortion compensation circuit, 101 ... input terminal, 102 ... predistorter, 103 ... D / A converter, 104 ... quadrature modulator, 105 ... oscillator, 106 ... power amplifier, 107 ... output Terminals 108 ... Directional coupler 109 ... Mixer 110 ... Oscillator 111 ... A / D converter 112 ... Distortion detector 113 ... Fast Fourier transform circuit (FFT) 114 ... IM arithmetic circuit 11 Control unit 116 D / A converter 117 Control unit 161 Delay correction circuit 162 Directional coupler 163 Detection circuit 164 A / D converter 231, 232 Input terminal 233 ... Predistorter, 234 ... Digital quadrature modulator, 235, 236 ... Multiplier, 237 ... NCO, 238 ... Adder, 239 ... A converter, 240 ... Low pass filter (LPF), 241 ... Up converter, 242 ... Driver amplifier, 243 ... Doherty amplifier, 244 ... Power detector, 245 ... LUT, 246 ... D / A converter, 247 ... Low pass filter (LPF), 248 ... Buffer amplifier, 251 ... Directional coupler, 252 ... Down converter, 253 ... Low pass filter (LPF), 254 ... A / D converter, 255 ... Strain detection circuit, 256, 256A ... Control circuit, 261: first coarse adjustment delay circuit, 262: second coarse adjustment delay circuit, 263: fine adjustment delay circuit, 271: input terminal, 272a to 272n ... flip-flop, 273 ... selector, 274 ... control terminal 275: Output terminal, 281: Input terminal, 282a to 282n ... Flip-flop, 283 ... Coefficient input terminal, 284a-284n ... Multiplier, 285 ... Adder, 286 ... Output terminal

Claims (2)

Carrier amplification circuit including an amplification element operating in class AB, peak amplification circuit including an amplification element whose amplification operation is controlled by a control signal input from a control terminal, and amplification by the carrier amplification circuit and the peak amplification circuit A Doherty amplifier comprising combining means for combining and outputting the generated signals;
A predistorter that compensates for non-linear distortion of the Doherty amplifier; a distortion detection unit that detects intermodulation distortion included in an output signal of the Doherty amplifier; and the distortion value detected by the distortion detection unit is reduced. The predistorter is controlled, the bias of the peak amplifier circuit is arbitrarily controlled according to the distortion value detected by the distortion detector and the input signal level of the Doherty amplifier, and the input amplitude level pair of the Doherty amplifier is controlled. A predistortion distortion compensation circuit comprising a control unit for controlling the output amplitude level conversion characteristics to approach class AB,
An amplifying device with a distortion control function, comprising: A carrier amplifier circuit including an amplifier element operating in class AB, a peak amplifier circuit including an amplifier element whose amplification operation is controlled by a bias control signal input from a control terminal, and the carrier amplifier circuit and the peak amplifier circuit. A Doherty amplifier comprising combining means for combining and outputting the amplified signals;
For an input signal to be amplified, a predistorter that compensates for non-linear distortion generated in the Doherty amplifier, and a signal output from the predistorter is converted into a high-frequency signal and input to a signal input terminal of the Doherty amplifier. The signal compensated by the first signal system and the predistorter is taken out and a bias control signal is generated based on the level of the signal and a preset bias control characteristic to control the Doherty amplifier. A second signal system that is input to the signal, a delay adjustment circuit provided in at least one of the first signal system and the second signal system, and distortion detection that detects intermodulation distortion included in the output signal of the Doherty amplifier And a signal of the delay adjustment circuit that controls the predistorter so that a distortion value detected by the distortion detector decreases. A control unit for controlling the extension amount,
An amplification device with a distortion control function, comprising:

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