JP2008021040A - Bus master circuit, bus control method and computer program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve processing speed in detecting the status of hardware connected to a bus, and to suppress the increase of the area of this system. <P>SOLUTION: A status detection block 206 detects data quantity in the FIFO of an external communication module 203. A condition decision block 207 decides whether or not the generation conditions of an interrupt signal 217 are satisfied based on the detection result of the status detection block 206. When it is decided that the generation conditions of the interrupt signal 217 are satisfied, an interrupt signal generation block 208 generates an interrupt signal 217, and outputs it to a CPU 201. The CPU 201 performs predetermined processing based on the interrupt signal 217. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a bus master circuit, a bus control method, and a computer program, and is particularly suitable for use in detecting the state of hardware connected to a bus.

In general, in a system LSI having a bus to which a processor and one or more hardware are connected, in order to control the hardware, the processor grasps the state of the hardware, and the hardware according to the state of the hardware. Hardware or other hardware.
As a method for the processor to grasp the hardware state, there is a polling method in which a register indicating the internal state of the hardware is provided in the hardware, and the processor continuously monitors the register to know the internal state of the hardware. . In the following description, monitoring a register is referred to as polling. An interrupt notification method is also used in which the hardware notifies the processor of an interrupt signal when the register state in the hardware reaches a predetermined state. In Patent Document 1, a register setting value for generating an interrupt signal at an arbitrary number of clocks within a communication cycle is compared with a setting value for a cycle timer circuit by a comparator, and an interrupt is issued when a command output from the comparator is received. An interrupt generation circuit for outputting a signal to a CPU is described. This interrupt generation circuit generates an interrupt signal to be given to the host CPU even if noise or the like occurs.

The processor detects the internal state of the hardware using one of the methods described above, and controls the hardware according to the internal state of the hardware.
In the method in which the processor polls a register indicating the internal state of the hardware, the processor continuously issues a command to read the register many times, and thus a heavy load is applied to the processor. Therefore, the interrupt notification method is generally used.

However, the interrupt notification technique cannot be used in all situations. For example, if the hardware cannot notify the processor of an interrupt signal because the hardware internal state has not been assumed at the design stage, the processor performs polling to detect the hardware internal state, You need to control the hardware. Similarly, when the hardware cannot perform the interrupt processing intended by the hardware due to a bug or the like, the processor needs to perform polling to control the hardware.
In order to solve such inconvenience, a sub processor for backup is provided, and the sub processor performs polling to detect the internal state of the hardware, and notifies the main processor of the detected internal state of the hardware. A method for controlling the above has also been adopted.

JP 2002-185469 A

However, the method for detecting the internal state of the hardware using the sub-processor described above has the following disadvantages.
First, after the reset is released, the sub processor needs a boot process for reading the code of the program to be executed from the ROM or the like. Therefore, it takes time to start the system, and a memory area for storing the program is required.

  Further, communication (inter-multiprocessor communication) between the main processor and the sub processor is required. Therefore, a shared memory that can be used by both processors must be secured. The shared memory requires an area for storing a processing request message from the sub processor to the main processor and an area for storing a response message from the main processor to the sub processor in response to the processing request. Further, the shared memory also requires an area for storing a processing request message from the main processor to the sub processor and an area for storing a response message from the sub processor to the main processor in response to the processing request.

  When making a processing request from the sub processor to the main processor, the sub processor writes the processing request message to the main processor in the processing request message storage area (shared memory) to the main processor, and notifies the main processor of an interrupt. I do. Usually the processor does not have a slave interface. Therefore, when clearing this interrupt notification, the main processor writes the processing request message for the sub processor in the processing request message storage area (shared memory) for the sub processor, and notifies the sub processor of the interrupt. Such an interrupt clear sequence takes more processing time than normal processing performed by clearing the interrupt clear register.

  Further, in the system LSI for reducing the cost, for example, even if the area is an 8-bit microcomputer, an increase in the area of the system LSI due to the provision of the sub processor is not preferable. Further, when the sub processor is provided, in addition to the sub processor main body, hardware resources such as a work memory area for the sub processor to execute the program are required. Such hardware resources become a factor that increases the area of the system LSI.

  The present invention has been made in view of such problems, and it is an object of the present invention to improve the processing speed when detecting the state of hardware connected to a bus and suppress an increase in the area of the system.

  The bus master circuit of the present invention is a bus master circuit that is mutually connected via a bus with a processor and one or more hardware, and is connected to each other via the bus by accessing the bus as a bus master. Detection means for detecting a hardware state, determination means for determining the hardware state detected by the detection means, and generation means for generating a control signal based on the hardware state determined by the determination means And output means for outputting the control signal generated by the generating means to the bus.

  The bus control method according to the present invention includes a detection step of accessing a bus as a bus master and detecting a state of hardware connected to each other via the bus, and determining a hardware state detected by the detection step. And a generating step for generating a control signal based on a hardware state determined by the determining step, and an output step for outputting the control signal generated by the generating step to the bus. Features.

  A computer program according to the present invention accesses a bus as a bus master, detects a state of hardware connected to each other via the bus, and determines a hardware state detected by the detection step Causing the computer to execute a determination step, a generation step for generating a control signal based on the hardware state determined in the determination step, and an output step for outputting the control signal generated in the generation step to the bus It is characterized by that.

  According to the present invention, the bus is accessed as a bus master, the hardware state is detected, and the control signal is generated and output based on the detected hardware state. This eliminates the need for the processor to detect the hardware status, thus reducing the load on the processor, improving the operating speed when detecting the hardware status, and suppressing an increase in system area. Can be realized.

  According to another aspect of the invention, based on the state of the hardware, a control signal related to the operation of the second hardware different from the hardware is generated, and the generated control signal is transmitted via the bus. Output to the second hardware. Therefore, it is possible to control the operation of the hardware module without performing interrupt processing to the processor.

  According to another feature of the present invention, a control signal for controlling a clock supplied to the processor is generated based on a hardware state. Therefore, for example, even when the processor is stopped, the hardware operation can be controlled.

In addition, according to another feature of the present invention, the interval for detecting the hardware state is provided, so that the load on the bus can be reduced.
Furthermore, according to the other feature of the present invention, since the interval for detecting the hardware state can be set in a programmable manner, the detection frequency of the hardware state can be adjusted.

  In addition, according to another feature of the present invention, the output destination address of the control signal and the data included in the control signal can be set in a programmable manner, so that various hardware can be controlled in various forms. become.

According to another feature of the present invention, the hardware address for detecting the state can be set in a programmable manner, so that various hardware states can be detected.
According to another feature of the present invention, the condition for determining the hardware state can be set in a programmable manner, so that the hardware state can be determined under various conditions.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
First, the basic configuration of the bus master circuit of this embodiment will be described. FIG. 1 is a diagram illustrating an example of a basic configuration of a bus master circuit.
In FIG. 1, the bus master circuit 101 includes a bus master function block 102, a state detection block 103, a condition determination block 104, a hardware control block 105, a control register group 106, and a bus slave function block 107.

The bus master function block 102 is a master interface block for accessing the system bus 108 as a bus master (bus access) in accordance with the bus protocol of the system bus 108.
The state detection block 103 continuously requests the bus master function block 102 to read the setting of the register that displays the internal state of the hardware connected to the system bus 108. In the following description, this request is referred to as a read request as necessary. The setting of a register that displays the internal state of the hardware connected to the system bus 108 is referred to as read data as necessary. Then, the state detection block 103 receives the read data acquired by the bus master function block 102 based on the read request. The state detection block 103 controls polling performed by the bus master circuit 101, such as the address of a register that displays the internal state of the hardware connected to the system bus 108 and the polling interval.

The condition determination block 104 is a block that receives read data from the state detection block 103 and compares the received read data with a determination condition to determine whether the condition is satisfied. Then, the condition determination block 104 generates a condition determination flag indicating whether or not the determined condition is satisfied.
The hardware control block 105 is a block that receives a condition determination flag from the condition determination block 104 and generates a control signal for controlling a processor and hardware connected to the system bus 108 based on the received condition determination flag. .

The control register group 106 is a register group for setting the operation of the bus master circuit 101. This register group is set in a programmable manner by a CPU connected to the system bus 108, for example.
The bus slave function block 107 is an interface for a CPU or the like connected to the system bus 108 to access the control register group 106. The bus slave function block 107 is a block of a slave interface for accessing (bus access) the system bus 108 as a bus slave according to the bus protocol of the system bus 108.

  Next, a specific example of a method of polling a register that displays the internal state of hardware connected to the system bus 108 using the bus master circuit 101 and controlling the processor and hardware based on the polled result is detailed. In the following. Here, as an example, the hardware control block 105, which is one of the requirements of the bus master circuit 101, is configured by an interrupt signal generation block having a function of generating an interrupt signal for the CPU connected to the system bus 108. explain.

FIG. 2 is a diagram illustrating an example of a configuration of a system LSI including a bus master circuit that generates an interrupt signal for the CPU.
In FIG. 2, the system LSI includes a CPU 201, a bus master circuit 202, an external communication module 203, and a system bus 108. In addition to these, the system LSI also includes, for example, a ROM and a RAM.
The bus master circuit 202 includes a bus master function block 205, a state detection block 206, a condition determination block 207, an interrupt signal generation block 208, a control register group 209, and a bus slave function block 210. The bus master circuit 202 generates an interrupt signal (interrupt) 217 and transmits the generated interrupt signal 217 to the CPU 201 via the system bus 108.

The bus master function block 205 is a master interface block for accessing (bus access) the system bus 108 as a bus master according to the bus protocol of the system bus 108.
The state detection block 206 includes a read request control block 206a that makes a read request to the bus master function block 205, and a register (DataReg) 206b that receives read data from the bus master function block 205. The state detection block 206 receives signals (En, Sts_Addr) 221 and 222 from the control register group 209. Details of the signals (En, Sts_Addr) 221 and 222 will be described later.

  The read request control function block 206 a has an interface with the bus master function block 205. The read request control function block 206a transfers the address signal (addr) 231 and the read data (rdata) 234 by handshaking the read request signal (req) 232 and the access end signal (done) 233.

  When the signal (En) 221 transmitted from the polling control register 211 of the control register group 209 indicates the start of polling (when En = 0x1), the read request control function block 206a reads the bus master function block 205. Make a request. Specifically, the read request control function block 206a reads the address of the register to be polled from the signal (Sts_Addr) 222 output from the target address register 212. Then, the read request control function block 206 a issues a read request signal (req) 232 and an access address signal (addr) 231 to the bus master function block 205.

  Further, the read request control function block 206 a receives the access end signal (done) 233 and the read data (rdata) 234 from the bus master function block 205. The read request control function block 206a stores the received read data (rdata) 234 in the internal register 206b. When the signal (En) 221 transmitted from the polling control register 211 of the control register group 209 does not indicate the start of polling (when En = 0x0), the read request control function block 206a issues a read request. Not performed.

  The condition determination block 207 receives the output signal (data) 241 of the register 206b from the state detection block 206, compares the output signal (data) 241 (that is, read data) with the determination condition, and determines whether the condition is satisfied. This is a block for determining. Then, the condition determination block 207 generates a condition determination flag signal (flag) 242 indicating whether or not the determined condition is satisfied. The condition determination block 207 also receives a signal (Cond_Val) 223 from the determination data register 223 of the control register group 209 and a signal (Cond_Mask) 224 from the determination mask register 214. Details of the signals (Cond_Val, Cond_Mask) 223, 224 will be described later.

FIG. 3 is a diagram illustrating an example of the configuration of the condition determination block 207.
In FIG. 3, the comparator 501 is composed of an exclusive NOR circuit. Signals (raw_flag) 511a to 511c are the results of bit-by-bit comparison between signals (data) 241a to 241c and signals (Cond_Val) 223a to 223c. As a result of the comparison, if the signals (data) 241a to 241c match the signals (Cond_Val) 223a to 223c, “1” is output as the signal (raw_flag) 511. On the other hand, if the signals (data) 241a to 241c and the signals (Cond_Val) 223a to 223c do not match, “0” is output as the signal (raw_flag) 511.

  The selector 502 selects the signal (raw_flag) 511 output from the comparator 501 and the signal (Cond_Mask) 224 that is mask data. When the signal (Cond_Mask) 224 is “1”, the selector 502 outputs the signal (Cond_Mask) 224 and the signal (raw_flag) 511 is masked. On the other hand, when the signal (Cond_Mask) 224 is “0”, the selector 502 outputs a signal (raw_flag) 511. The logical product circuit 503 calculates the logical product of all the bits of the signal output from the selector 502. The AND circuit 503 outputs a condition determination flag based on the calculated result to the interrupt signal generation block 208 as a signal (flag) 242. The condition determination flag is “1” when all the signals (raw_flag) 511 other than the bits masked by the signal (Cond_Mask) 224 are “1”, and “0” otherwise.

  Returning to FIG. 2, the interrupt signal generation block 208 is a block that receives the condition determination flag signal (flag) 242 from the condition determination block 207 and generates an interrupt signal (interrupt) 217. Further, a signal (Polarity) 225 is received from the signal generation control register 215 of the control register group 209, and a signal (Clear) 226 is received from the clear register 216. The details of the signals (Polarity, Clear) 225, 226 will be described later.

FIG. 4 is a diagram illustrating an example of the configuration of the interrupt signal generation block 208.
In FIG. 4, the interrupt signal control unit 601 generates a positive logic interrupt signal (int) 611 from the condition determination flag signal (flag) 242. Specifically, when the signal (Clear) 226 from the clear register 216 is “0”, the interrupt signal control unit 601 generates a positive logic interrupt signal (int) 611 from the condition determination flag signal (flag) 242. Generate (int = 1). On the other hand, when the signal (Clear) 226 from the clear register 216 is “0”, the interrupt signal control unit 601 negates the positive logic interrupt signal (int) 611 (int = 0).

  The selector 602 selects the polarity of the interrupt signal (int) 611 output from the interrupt signal control unit 601. The selector 602 outputs a positive logic interrupt signal (int) 611 as the interrupt signal (interrupt) 217 when the signal (Polarity) 225 is “0”. On the other hand, when the signal (Polarity) 225 is “1”, the selector 602 outputs a negative logic interrupt signal obtained by inverting the positive logic interrupt signal (int) 611 as the interrupt signal (interrupt) 217.

Returning to FIG. 2, the control register group 209 is a block having source registers for signals that control operations of the state detection block 206, the condition determination block 207, and the interrupt signal generation block 208. The CPU 201 performs setting of the registers 211 to 216 in a programmable manner.
The polling control register 211 controls the start and stop of polling, and outputs a signal (En) 221 indicating the start and stop of polling to the state detection block 206. FIG. 5A shows an example of the specification of the polling control register 211. In FIG. 5A, Bits indicates a bit configuration, Name indicates a signal name, Access indicates an attribute, and Function indicates a function. Here, the attribute R indicates read, and W indicates write. When the 0th bit En of the polling control register 211 is set to “1”, polling is started. That is, the polling control register 211 outputs a signal (En) 221 indicating “0x1” to the state detection block 206. On the other hand, when the 0th bit En of the polling control register 211 is set to “0”, the polling is stopped. That is, the polling control register 211 outputs a signal (En) 221 indicating “0x0” to the state detection block 206.

  The target address register 212 sets an address of a polling target register (for example, the FIFO data pointer register 204), and outputs a signal (Sts_Addr) 222 indicating the address to the state detection block 206. FIG. 5B shows an example of the specification of the target address register 212. As shown in FIG. 5B, in this embodiment, the signal (Sts_Addr) 222 has a 32-bit configuration. Further, the bit width of the signal (Sts_Addr) 222 is made the same as the address width of the system bus 108 to be used.

  The determination data register 213 is for setting data as a comparison condition in the condition determination block 207, and outputs a signal (Cond_Val) 223 indicating data as a comparison condition to the condition determination block 207. FIG. 5C shows an example of the specification of the determination data register 213. As shown in FIG. 5C, in this embodiment, the signal (Cond_Val) 223 has a 32-bit configuration. The bit width of the signal (Cond_Val) 223 is the same as the data width of the system bus 108 to be used.

  The determination data mask register 214 is for setting a bit for masking the condition determination for each bit, and outputs a signal (Cond_Mask) 224 indicating the setting to the condition determination block 207. FIG. 5D shows an example of the specification of the determination data mask register 214. As shown in FIG. 5D, in this embodiment, the signal (Cond_Mask) 224 has a 32-bit configuration. The bit width of the signal (Cond_Mask) 224 is the same as the data width of the system bus 108 to be used. As shown in FIG. 3, in this embodiment, a signal (Cond_Mask) 224 is used to mask a bit for masking condition determination for each bit. Further, as described above, when “1” is set in the signal (Cond_Mask) 224 corresponding to the corresponding bit, the condition determination for that bit is masked.

  The signal generation control register 215 is for controlling an interrupt signal (interrupt) 217 to be generated, and outputs a signal (Polarity) 225 to the interrupt signal generation block 208. FIG. 5E shows an example of the specification of the signal generation control register 215. As shown in FIG. 5E, when the 0th bit Polarity of the signal generation control register 215 is set to “0”, a positive logic interrupt signal 217 is generated, and when it is set to “1”, it is negative. A logical interrupt signal 217 is generated (see FIG. 4).

  The clear register 216 is for clearing the interrupt signal 217, and outputs a signal (Clear) 226 to the interrupt signal generation block 208. FIG. 5F shows an example of the specification of the interrupt clear register 216. When the 0th bit Clear of the interrupt clear register 216 is set to “1”, the interrupt signal 217 is cleared. When the interrupt signal 217 is cleared, the 0th bit Clear of the interrupt clear register 216 automatically returns to “0”.

  The bus slave function block 210 is an interface for the CPU 201 to access the control register group 209. The bus slave function block 210 is a slave interface block for accessing (bus access) the system bus 108 as a bus slave in accordance with the bus protocol of the system bus 108.

The external communication module 203 is a block for transmitting and receiving data from the outside, and incorporates a 1-byte, 16-stage FIFO (First-In First-Out) for data reception. In the present embodiment, it is assumed that the data pointer register 204 indicating the number of data existing in the FIFO is mapped to the address “0xA000_0000”.
FIG. 6 is a diagram illustrating an example of the specification of the data pointer register 204. As shown in FIG. 6, the number of data existing in the FIFO is indicated by 4-bit data, and the value of the data pointer register 204 changes from “0x0” to “0xf”. The data pointer register 204 receives data, and when the FIFO becomes full and the value of the data pointer register 204 becomes “0xf”, a positive logic interrupt signal (int_full) 218 is sent to the CPU 201 via the system bus 108. Notice.

  Next, an example of the operation of the system LSI shown in FIG. 2 will be described. Here, the bus master circuit 202 detects the state one step before the FIFO of the external communication module 203 becomes full (that is, the value of the data pointer register 204 becomes “0xe”), and generates the interrupt signal 217. A case will be described as an example.

First, the CPU 201 sets the address “0xA000_0000” of the FIFO data pointer register 204 to be polled in the target address register 212. Accordingly, the signal (Sts_Addr) 222 output from the target address register 212 becomes a signal indicating “0xA000_0000” (Sts_Addr = 0xA000_0000).
Next, the CPU 201 sets “0xe” in the determination data register 213 as data that serves as a comparison condition in the condition determination block 207. As a result, the signal (Cond_Val) 223 output from the determination data register 213 becomes a signal indicating “0xe” (Cond_Val = 0xe).

  Here, since the data to be compared in the condition determination block 207 is 4 bits, it is not necessary to compare other bits. Therefore, the CPU 201 sets “0xffff_fff0” in the determination mask register 214 in order to mask the bits that are not compared. As a result, the signal (Cond_Mask) 224 output from the determination mask register 214 becomes a signal indicating “0xffff_fff0” (Cond_Mask = 0xffff_fff0).

  Next, the CPU 201 sets “0x0” in the signal generation control register 215. As a result, the signal 225 output from the signal generation control register 215 is a signal indicating “0x0” (Porality = 0x0). Then, the CPU 201 sets “0x1” in the polling control register 211. As a result, the signal 221 output from the polling control register 211 to the state detection block 206 becomes “0x1” (En = 0x1), and polling starts.

When polling starts, the state detection block 206 makes a read request to the bus master function block 205. Here, an example of the operation of the state detection block 206 when a read request is made to the bus master function block 205 will be described with reference to the flowchart of FIG.
First, in step S701, the read request control function block 206a determines whether or not the signal (En) 221 output from the polling control register 211 is “1” and whether or not polling is started. Judging. As a result of this determination, if the polling is not started, the process is terminated. On the other hand, if polling is started, the process proceeds to step S702.

  In step S702, the read request control function block 206a sets the set value “0xA000_0000” of the target address register 212 as the address signal (addr) 231. Further, the read request control function block 206a asserts a read request signal (req) 232. That is, a read request signal (req) 232 indicating “1” is output to the bus master function block 205 (req = 1).

  Next, in step S703, the read request control function block 206a determines whether or not the access end signal (done) 233 is asserted. That is, it is determined whether or not the access end signal (done) 233 transmitted from the bus master function block 205 is “1”. As a result of the determination, when the access end signal (done) 233 is not asserted (when the access end signal (done) 233 transmitted from the bus master function block 205 is not “1”), the processing is ended. On the other hand, when the access end signal (done) 233 is asserted (when the access end signal (done) 233 transmitted from the bus master function block 205 is “1”), the process proceeds to step S704.

In step S704, the read request control function block 206a negates the read request signal (req) 232. That is, a read request signal (req) 232 indicating “0” is output to the bus master function block 205 (req = 0).
In step S705, the read request control function block 206a compares the read data (rdata) 234 output from the bus master function block 205 with the read data set in the register 206b. Then, the read request control function block 206a determines whether there is a change in the read data. If the result of this determination is that there is no change in the read data, the process is terminated. On the other hand, if there is a change in the read data, the process proceeds to step S706. In step S706, the read request control function block 206a sets the value of the read data (rdata) 234 output from the bus function block 205 in the register 206b.

Returning to FIG. 2, when data accumulates in the FIFO built in the external communication module 203, the value of the register 206b changes to “0x0, 0x1,...”. Therefore, the signal (data) 241 input by the condition determination block 207 also changes to “0x0, 0x1,...”. Here, the signal (Cond_Mask) 224 output from the determination mask register 214 is “0xffff_fff0” (Cond_Mask = 0xffff_fff0). Therefore, the condition determination flag signal (flag) 242 output from the condition determination block 207 is “0” (flag = 0) while the following expression (1) is satisfied. The signal (flag) 242 of the condition determination flag is “1” while the following expression (2) is satisfied (that is, while the signal (data) 241 indicates “0xe”) (flag = 1 ).
data [3: 0] ≠ Cond_Val [3: 0] (1)
data [3: 0] = Cond_Val [3: 0] (2)

  When the condition determination flag signal (flag) 242 becomes “1” (flag = 1), the interrupt signal control unit 601 of the interrupt signal generation block 208 generates a positive logic interrupt signal (int) 611 (int = 1). . Here, an example of the operation of the interrupt signal generation block 208 will be described with reference to the flowchart of FIG.

  First, in step S801, the interrupt signal control unit 601 determines whether or not the condition determination flag signal (flag) 242 has a rising edge. As a result of this determination, if the condition determination flag signal (flag) 242 does not have a rising edge, the process skips step S802 and proceeds to step S803 described later. On the other hand, if the condition determination flag signal (flag) 242 has a rising edge, the process proceeds to step S802.

In step S802, the interrupt signal control unit 601 asserts a positive logic interrupt signal (int) (int = 1).
In step S803, the interrupt signal control unit 601 determines whether the signal (Clear) 226 from the clear register 216 is asserted (whether the signal (Clear) 226 from the clear register 216 is “1”). Or). As a result of this determination, when the signal (Clear) 226 from the clear register 216 is not asserted (when the signal (Clear) 226 from the clear register 216 is not “1”), the processing ends. On the other hand, when the signal (Clear) 226 from the clear register 216 is asserted (when the signal (Clear) 226 from the clear register 216 is “1”), the process proceeds to step S804.

  In step S804, the interrupt signal generation block 208 negates the positive logic interrupt signal (int) 611 and the signal (Clear) 226 from the clear register 216 (int = 0, Clear = 0).

  Returning to FIG. 2, when the signal (Clear) 226 from the clear register 216 is “0”, the interrupt signal control unit 601 outputs a positive logic interrupt signal (int) 611 (int = 1). ). Here, the signal (Polarity) 225 output from the signal generation control register 215 is set to “0” (Polarity = 0x0). Accordingly, the selector 602 selects the positive logic interrupt signal (int) 611 as the interrupt signal (interrupt) 217. Then, the selector 602 outputs an interrupt signal (interrupt) 217 indicating “1” to the CPU 201 via the system bus 108.

  The CPU 201 receives an interrupt notification from the interrupt signal (interrupt) 217 output from the interrupt signal generation block 208, and performs a predetermined process in a state just before the FIFO built in the external communication module 203 becomes full. . Then, the CPU 201 clears the interrupt. The interrupt is cleared by setting “0x1” in the interrupt clear register 216. When “0x1” is set in the interrupt clear register 216 (Clear = 0x1), the interrupt signal control unit 601 negates the positive logic interrupt signal (int) 611 according to the flowchart of FIG. As a result, an interrupt signal (interrupt) 217 indicating “0” is output and the interrupt is cleared.

  As described above, in the present embodiment, the state detection block 206 detects the data amount in the FIFO of the external communication module 203. Based on the detection result of the state detection block 206, the condition determination block 207 determines whether or not the generation condition of the interrupt signal 217 is satisfied. When the generation condition of the interrupt signal 217 is satisfied, the interrupt signal generation block 208 generates the interrupt signal 217 and outputs it to the CPU 201. The CPU 201 performs predetermined processing based on the interrupt signal 217.

  Therefore, conventionally, even when the CPU 201 has to poll and detect the internal state of the external communication module 203, the bus master circuit 202 can perform polling instead of the CPU 201 and notify the CPU 201 of an interrupt. Thereby, the load on the CPU 201 can be reduced and the processing speed when detecting the internal state of the external communication module 203 can be improved. Furthermore, since it is not necessary to provide a plurality of processors (CPUs), it is possible to prevent the area of the system LSI from increasing due to hardware (for example, shared memory of a plurality of processors) for detecting the internal state of the external communication module 203. In addition, since the hardware address where the state detection block 206 detects the state and the condition determined by the condition determination block 207 are set programmably, various hardware states can be set under various conditions. It becomes possible to discriminate.

In this embodiment, the hardware to be polled by the bus master circuit 202 is the external communication module 203, but the object to be polled by the bus master circuit 202 is not limited to this. That is, any hardware module provided with a register for displaying an internal state inside the hardware can be polled.
In addition, since the CPU 201 performs setting for each of the registers 211 to 216 in a programmable manner, the order of setting for each of the registers 211 to 216 is not limited to that described above.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In this embodiment, a configuration for adjusting the polling timing is added to the first embodiment described above. Therefore, in the description of the present embodiment, the same parts as those in the first embodiment described above are denoted by the same reference numerals as those in FIGS. In this embodiment as well, as in the first embodiment, the hardware control block 105 of FIG. 1 is configured with an interrupt signal generation block having a function of generating an interrupt signal for the CPU 201 connected to the system bus 108. A case will be described as an example.

FIG. 9 is a diagram illustrating an example of a configuration of a system LSI including a bus master circuit that generates an interrupt signal for the CPU.
The bus master circuit 202 includes a bus master function block 205, a state detection block 2206, a condition determination block 207, an interrupt signal generation block 208 as a control signal generation block, a control register group 2209, and a bus slave function block 210.

The state detection block 2206 includes the read request control block 206a and the register (DataReg) 206b described in the first embodiment, and a timer function block 206c that measures a polling period.
The timer function block 206c receives a signal (Cyc_En) 2227b indicating whether or not to perform polling periodically from the polling cycle setting register 2217 of the control register group 2209. When the polling is performed periodically, the timer function block 206c receives a signal (Cyc_Range) 2227a indicating the period. The details of these signals (Cyc_Range, Cyc_En) 2227 will be described later. When the signal (Cyc_En) 2227b output from the polling cycle setting register 2217 indicates “0x1”, the timer function block 206c controls the interval at which the read request signal (req) 232 is asserted with a timer. This makes it possible to make a polling request periodically.

  The control register group 2209 is a block having source registers for signals that control the operations of the state detection block 2206, the condition determination block 207, and the interrupt signal generation block 208. The CPU 201 performs setting of the registers 211 to 216 and 2217 in a programmable manner.

  As described above, the polling cycle setting register 2217 is for setting the polling cycle, and outputs the signal (Cyc_Range) 2227a and the signal (Cyc_En) 2227b to the state detection block 2206. FIG. 10 is a diagram illustrating an example of the specification of the polling cycle setting register 2217. When the 0th bit Cyc_En of the polling cycle setting register 2217 is set to “1”, a cycle polling operation mode in which polling is performed periodically is set. Further, when the 0th bit Cyc_En of the polling cycle setting register 2217 is set to “0”, a normal polling operation mode in which normal non-periodic polling is performed is set. When the 0th bit Cyc_En of the polling cycle setting register 2217 is set to “1” to set the cycle polling operation mode, the 4th to 31st bit Cyc_Range of the polling cycle setting register 2217 is set to the polling cycle. Specifically, in the 4th to 31st bits Cyc_Range of the polling cycle setting register 2217, the number of cycles to be set as the polling interval is set.

  Next, an example of the operation of the system LSI shown in FIG. 9 will be described. Also in this embodiment, the external communication module 203 includes a 16-stage FIFO (First-In First-Out). Further, it is assumed that the data pointer register 204 indicating the number of data existing in the FIFO is mapped to the address “0xA000_0000”. Also, the bus master circuit 2202 detects the state one step before the FIFO of the external communication module 203 becomes full (that is, the value of the data pointer register 204 becomes “0xe”) and generates an interrupt signal 217 And Further, it is assumed that polling performed by the state detection block 2206 is performed at intervals of three cycles.

First, the CPU 201 sets the address “0xA000_0000” of the FIFO data pointer register 204 to be polled in the target address register 212.
Next, the CPU 201 sets “0xe” in the determination data register 213 as data that serves as a comparison condition in the condition determination block 207.

Here, since the data to be compared in the condition determination block 207 is 4 bits, it is not necessary to compare other bits. Therefore, the CPU 201 sets “0xffff_fff0” in the determination mask register 214 in order to mask the bits that are not compared.
Next, the CPU 201 sets “0x0” in the signal generation control register 215.

Further, here, since polling is performed in a cycle of 3 cycles, the CPU 201 sets “0x31” in the polling cycle setting register 2217. As a result, the signal (Cyc_Range) 2227a output from the polling cycle setting register 2217 becomes a signal indicating “0x3” (Cyc_Range = 0x3). The signal (Cyc_En) 2227b is a signal indicating “0x1” (Cyc_En = 0x1).
Then, the CPU 201 sets “0x1” in the polling control register 211 to start polling.

  When polling starts, the state detection block 206 makes a read request to the bus master function block 205. Here, an example of the operation of the state detection block 2206 when making a read request to the bus master function block 205 will be described with reference to the flowchart of FIG.

  First, steps S1101 to S1106 are the same as steps S701 to 706 shown in FIG. That is, the state detection block 206 determines whether or not it is in a state of starting polling (step S1101). When the polling is started, the read request control function block 206a sets the set value “0xA000_0000” of the target address register 212 as the address signal (addr) 231. Further, the read request control function block 206a asserts the read request signal (req) 232 (step S1102).

  Next, the read request control function block 206a determines whether or not the access end signal (done) 233 has been asserted (step S1103). When the access end signal (done) 233 is asserted, the read request control function block 206a negates the read request signal (req) 232 (step S1104).

  Next, the read request control function block 206a determines whether or not there is a change in the read data (step S1105). If the result of this determination is that there is no change in the read data, step S1106 is omitted and processing proceeds to step S1107 described later. On the other hand, when there is a change in the read data, the read request control function block 206a sets the value of the read data (rdata) 234 output from the bus function block 205 in the register 206b.

  In step S1107, the read request control function block 206a refers to the value of the signal (Cyc_En) 2227b output from the polling cycle setting register 2217. Then, the read request control function block 206a determines whether the operation mode is the periodic polling operation mode or the normal polling operation mode. As a result of this determination, when the operation mode is the normal polling operation mode, the process is terminated. On the other hand, when the operation mode is the periodic polling operation mode, the process proceeds to step S1108.

In step S1108, the read request control function block 206a waits until a signal (expired) 2243 is asserted from the timer function block 206c. That is, the read request control function block 206a waits until a signal (expired) 2243 indicating “1” is output from the timer function block 206c (expired = 1).
Here, an example of the operation of the state detection block 2206 when waiting for the next polling request for 3 cycles will be described with reference to the timing chart of FIG.
When the status detection block 2206 receives the access end signal (done) 233 from the bus master function block 205, the following processing is performed. That is, the timer function block 206 c starts decrementing the timer value (timer) 2244 by the number of cycles set in the polling period setting register 2217.

After that, when the timer value (timer) 2244 becomes “0”, the timer function block 206c asserts the signal (expired) 2243 for one cycle. When the signal (expired) 2243 is asserted, the state detection block 2206 asserts the next read request signal (req) 232. This makes it possible to perform polling.
If the signal (Cyc_En) 2227b output from the polling cycle setting register 2217 is “0x0” (Cyc_En = 0x0), the state detection block 2206 does not perform such periodic polling. That is, the state detection block 2206 issues the next polling request continuously as soon as the access end signal (done) 233 is asserted.

  Returning to FIG. 9, when data accumulates in the FIFO built in the external communication module 203, the value of the register 206b changes to “0x0, 0x1,...”. Therefore, the signal (data) 241 input by the condition determination block 207 also changes to “0x0, 0x1,...”. Here, the signal (Cond_Mask) 224 output from the determination mask register 214 is “0xffff_fff0” (Cond_Mask = 0xffff_fff0). Therefore, the signal (flag) 242 of the condition determination flag output from the condition determination block 207 is “0” (flag = 0) while the expression (1) is satisfied. The signal (flag) 242 of the condition determination flag is “1” while the above expression (2) is satisfied (that is, while the signal (data) 241 indicates “0xe”) (flag = 1). .

  When the condition determination flag signal (flag) 242 becomes “1” (flag = 1), the interrupt signal control unit 601 of the interrupt signal generation block 208 generates a positive logic interrupt signal (int) 611 (int = 1). . The detailed operation of the interrupt signal generation block 208 is as described in the first embodiment (see FIG. 8).

  When the signal (Clear) 226 from the clear register 216 is “0”, the interrupt signal control unit 601 outputs a positive logic interrupt signal (int) 611 (int = 1). Here, the signal (Polarity) 225 is set to “0” from the signal generation control register 215 (Polarity = 0x0). Accordingly, the selector 602 selects the positive logic interrupt signal (int) 611 as the interrupt signal (interrupt) 217. Then, the selector 602 outputs an interrupt signal (interrupt) 217 indicating “1” to the CPU 201 via the system bus 108.

  The CPU 201 receives an interrupt notification from the interrupt signal (interrupt) 217 output from the interrupt signal generation block 208, and performs a predetermined process in a state just before the FIFO built in the external communication module 203 becomes full. . Then, the CPU 201 clears the interrupt. The interrupt is cleared by setting “0x1” in the interrupt clear register 216. When “0x1” is set in the interrupt clear register 216 (Clear = 0x1), the interrupt signal control unit 601 negates the positive logic interrupt signal (int) 611 according to the flowchart of FIG. As a result, an interrupt signal (interrupt) 217 indicating “0” is output and the interrupt is cleared.

As described above, in the present embodiment, the timer function block 206c is used to make a polling request at the period set in the polling period setting register 2217. Therefore, in addition to the effect described in the first embodiment, the load on the system bus 108 can be further reduced.
In addition, since the period for performing the polling request is set programmably, the polling request frequency can be adjusted according to the system.
In this embodiment, the polling request is periodically made. However, if the polling request is made at intervals, it is not always necessary to make the polling request periodically (that is, The interval at which polling requests are made may not be constant).

(Third embodiment)
Next, a third embodiment of the present invention will be described. In the first and second embodiments described above, the bus master circuit 202 notifies the CPU 201 of an interrupt signal according to the internal state of the external communication module 203. On the other hand, in the present embodiment, the bus master circuit accesses other hardware that has not been polled according to the internal state of the hardware that has been polled. As described above, this embodiment and the first and second embodiments described above are a part of the configuration of the bus master circuit, hardware that the bus master circuit polls, and hardware that the bus master circuit accesses after polling. Is different. Therefore, in the description of the present embodiment, the same parts as those in the first and second embodiments described above are denoted by the same reference numerals as those in FIGS. . In the present embodiment, the case where the hardware control block 105 shown in FIG. 1 is configured by a bus transfer control block for setting a register of the clock control module will be described as an example.

FIG. 13 is a diagram illustrating an example of a configuration of a system LSI including a bus master circuit for setting a register of the clock control module.
In FIG. 13, the system LSI includes a CPU 201, a bus master circuit 3202, a port control module 1203, and a clock control module 1205.
The bus master circuit 3202 includes a bus master function block 3205, a state detection block 206, a condition determination block 207, a bus transfer control block 1208, a control register group 3209, and a bus slave function block 210. In the present embodiment, the bus transfer control block 1208 sets the registers of the clock control module 1205.

  The bus master function block 3205 is a master interface block for accessing (bus access) the system bus 108 as a bus master according to the bus protocol of the system bus 108.

As described above, the state detection block 206 detects the internal state of the hardware connected to the system bus. In the present embodiment, the state detection block 206 detects the internal state of the port status register 1205.
As described above, the condition determination block 207 determines whether the condition is satisfied based on the detection result of the state detection block 206. In this embodiment, the condition determination block 207 determines whether or not a condition for writing to the clock control register 1206 is satisfied.

  The bus transfer control block 1208 receives the rising edge of the condition determination flag signal (flag) 242 from the condition determination block 207, and issues a write request to the clock control register 1206 to the bus master function block 3205. In the following description, a write request to the clock control register 1206 is referred to as a write transfer request as necessary.

  The bus transfer control block 1208 has an interface with the bus master function block 3205. The bus transfer control block 1208 passes the address signal (addr) 3231 and the write data (wdata) 3234 to the bus master function block 3235 by handshaking the write request signal (req) 3232 and the access end signal (done) 3233. The bus transfer control block 1208 receives signals (Trf_Addr, Trf_Val) 3216 and 3217 from the control register group 209. Details of these signals (Trf_Addr, Trf_Val) 3216, 3217 will be described later. Further, the bus transfer control block 1208 outputs a signal (Clear) 3226 to the polling control register 211 when the polling operation by the state detection block 206 is stopped.

  The control register group 3209 is a block having a source register of signals for controlling operations of the state detection block 206, the condition determination block 207, and the bus transfer control block 1208. The CPU 201 performs setting of the registers 212 to 214 and 1216 to 1218 in a programmable manner.

  The polling control register 1218 is for controlling the start and stop of polling, and outputs a signal (En) 221 indicating the start and stop of polling to the state detection block 206. The specification of the polling control register 1218 is the same as that of the polling control register 211 shown in FIG. However, the polling control register 1218 also stops polling when it receives a signal (Clear) 3226 from the bus transfer control block 1208. That is, the polling control register 1218 outputs a signal (En) 221 indicating “0x0” to the state detection block 206.

As described above, the target address register 212 is for setting the address of a register to be polled, and its specification is as shown in FIG. In the present embodiment, the target address register 212 sets the address of the port status register 1204 shown in FIG.
As described above, the determination data register 213 is used to set data as a comparison condition in the condition determination block 207, and its specification is as shown in FIG.
As described above, the determination data mask register 214 is for setting bits for masking condition determination for each bit, and the specification is as shown in FIG.

  The transfer address register 1216 is a register of a module different from the module that performs polling, and sets the address of a register to be rewritten. The transfer address register 1216 outputs a signal (Trf_Addr) 3216 indicating the address to the bus transfer control block 1208. FIG. 14A shows an example of the specification of the transfer address register 1216. As shown in FIG. 14A, in this embodiment, the signal (Trf_Addr) 3216 has a 32-bit configuration. Further, the bit width of the signal (Trf_Addr) 3216 is made the same as the address width of the system bus 108 to be used.

The transfer data register 1217 sets data to be written in a register to be rewritten. The transfer data register 1217 outputs a signal (Trf_Val) 3217 indicating the data to the bus transfer control block 1208. FIG. 14B shows an example of the specification of the transfer data register 1217. As shown in FIG. 14B, in this embodiment, the signal (Trf_Val) 3217 has a 32-bit configuration. Further, the bit width of the signal (Trf_Val) 3217 is made the same as the data width of the system bus 108 to be used.
As described above, the bus slave function block 210 is an interface for the CPU 201 to access the control register group 209.

  The port control module 1203 controls a port assigned as a general-purpose port at an external terminal of the system LSI. The port control module 1203 has a port status register 1204 indicating the state of the external terminal. In the present embodiment, it is assumed that the port status register 1204 is mapped to the address “0xA010_0000”. FIG. 15A is a diagram illustrating an example of the specification of the port status register 1204. As shown in FIG. 15A, the states of the external terminals P0 to P7 can be read from the port status register 1204 in each of the 0th to 7th bits P0_Sts to P7_Sts. Note that the setting of the port status register 1204 is programmable by the CPU 201, for example.

  The clock control module 1205 controls the clock supplied to each module of the system LSI. The clock control module 1205 has a clock control register 1206 for setting the clock of each module. In this embodiment, it is assumed that the clock control register 1206 is mapped to the address “0xA020_0000”.

FIG. 15B is a diagram illustrating an example of the specification of the clock control register 1206. As shown in FIG. 15B, when “1” is set in the 0th bit CPU_clk, a clock is supplied to the CPU 201. On the other hand, when “0” is set in the 0th bit CPU_clk, the clock is not supplied to the CPU 201. When the system is activated, “0” is set in the CPU_clk of the 0th bit, and a clock is supplied to the CPU 201.
When “0” is set in the CPU_clk_frq for the first and second bits, the clock frequency of the CPU 201 is 1 MHz. Similarly, when “1” is set in the CPU_clk_frq of the first and second bits, 8 MHz is set, 64 MHz is set when “2” is set, and 128 MHz is set when “3” is set.

  Next, an example of the operation of the system LSI shown in FIG. 14 will be described. Here, the case where the clock of the CPU 201 is stopped and the system is shifted to the low power consumption state, and then the state of the external terminal is polled to return to the normal operation state will be described as an example. Note that the return to the normal operation state is performed when both the settings for the external terminals P6 and P7 are "1".

First, the CPU 201 performs setting for the control register group 209 of the bus master circuit 202. Specifically, the CPU 201 sets the address “0xA010_0000” of the port status register 1204 to be polled in the target address register 212. As a result, the signal (Sts_Addr) 222 output from the target address register 212 becomes a signal indicating “0xA010_0000” (Sts_Addr = 0xA000_0000).
Next, the CPU 201 sets “0xc0” in the determination data register 213 as data that serves as a comparison condition in the condition determination block 207. As a result, the signal (Cond_Val) 223 output from the determination data register is a signal indicating “0xc0” (Cond_Val = 0xc0).

  Further, since the data to be compared in the condition determination block 207 is 2 bits of the 6th bit and the 7th bit, it is not necessary to compare other bits. Therefore, the CPU 201 sets “0xffff_ff3f” in the determination mask register 214 in order to mask the bits that are not compared. As a result, the signal (Cond_Mask) 224 output from the determination mask register 214 becomes a signal indicating “0xffff_ff3f” (Cond_Mask = 0xffff_ff3f).

Then, the CPU 201 sets the address “0xA020_0000” of the clock control register 1206 to be rewritten data in the transfer address register 1216. Thus, the signal (Trf_Addr) 3216 output from the clock control register 1206 becomes a signal indicating “0xA020_0000” (Trf_Addr = 0xA020_0000).
Next, the CPU 201 supplies a clock to the CPU 201 and sets data “0x1” for setting the clock frequency to 1 MHz in the transfer data register 1217. As a result, the signal (Trf_Val) 3217 output from the transfer data register 1217 becomes “0x1” (Trf_Val = 0x1).
Then, the CPU 201 sets “0x1” in the polling control register 211. As a result, the signal 221 output from the polling control register 211 becomes “0x1” (En = 0x1), and polling starts.

  Thereafter, after operating the bus master circuit 202, the CPU 201 sets the CPU_clk of the 0th bit of the clock control register 1206 to “0”. Then, the clock is not supplied to the CPU 201 and the state shifts to a low power consumption state.

  When the signal (En) 221 output from the polling control register 211 becomes “0x1” (En = 0x1), the state detection block 206 makes a read request to the bus master function block 205. The operation when the state detection block 206 makes a read request to the bus master function block 205 is as shown in FIG.

Then, the value of the register 206b changes to “0x13, 0x19,...” According to the change of the external terminals P0 to P7 obtained as a result of the polling of the port status register 1204 by the bus master function block 3205. Therefore, the signal (data) 241 input by the condition determination block 207 also changes to “0x13, 0x19,...”. Here, the signal (Cond_Mask) 224 output from the determination mask register 214 is “0xffff_ff3f” (Cond_Mask = 0xffff_ff3f). Accordingly, the signal (flag) 242 of the condition determination flag output by the condition determination block 207 is “0” (flag = 0) while the following expression (3) is satisfied, and while the following expression (4) is satisfied Becomes “1” (flag = 1).
data [7: 6] ≠ Cond_Val [7: 6] (3)
data [7: 6] = Cond_Val [7: 6] (data [7: 6] = b11 (binary number)) (4)

  When the signal (flag) 242 of the condition determination flag becomes “1” (flag = 1), the bus transfer control block 1208 makes a write transfer request to the bus master function block 205 and also sends the signal (Clear) 3226 to the polling control register. To 211. Here, referring to the flowchart of FIG. 16, the operation of the bus transfer control block 1208 when a request for write transfer to the bus master function block 205 and the output of the signal (Clear) 3226 to the polling control register 211 are performed. An example will be described.

  First, in step S1601, the bus transfer control block 1208 determines whether or not the condition determination flag signal (flag) 242 has a rising edge. As a result of the determination, if the condition determination flag signal (flag) 242 does not have a rising edge, the process waits until the condition determination flag signal (flag) 242 has a rising edge. On the other hand, if the condition determination flag signal (flag) 242 has a rising edge, the process advances to step S1602.

In step S1602, the bus transfer control block 1208 outputs a signal (Clear) 3226 to the polling control register 1218 in order to stop the polling operation.
Next, in step S1602, the bus transfer control block 1208 includes the set value “0xA020_0000” of the transfer address register 212 in the address signal (addr). The bus transfer control block 1208 includes the set value “0x1” of the transfer data register in the write data (wdata) 3234. Then, the bus transfer control block 1208 asserts a write request signal (req) 3232 (req = 1). That is, the bus transfer control block 1208 outputs a write request signal (req) 3232 indicating “1” to the bus master function block 3205. As a result, a write transfer request is made from the bus transfer control block 1208 to the bus master function block 205.

  Next, in step S1604, the bus transfer control block 1208 determines whether or not the access end signal (done) 3233 has been asserted. That is, the bus transfer control block 1208 determines whether or not the access end signal (done) 3233 transmitted from the bus master function block 205 is “1”. As a result of this determination, when the access end signal (done) 3233 is not asserted (when the access end signal (done) 3233 transmitted from the bus master function block 3205 is not “1”), the process waits until it is asserted. On the other hand, when the access end signal (done) 3233 is asserted (when the access end signal (done) 3233 transmitted from the bus master function block 3205 is “1”), the process proceeds to step S1605.

  In step S1605, the bus transfer control block 1208 negates the read request signal (req) 3232. That is, the bus transfer control block 1208 outputs a read request signal (req) 3232 indicating “0” to the bus master function block 3205 (req = 0).

  In response to the write transfer request made from the bus transfer control block 1208 to the bus master function block 3205 as described above, the bus master function block 3205 performs write transfer to the clock control module 1205. Then, “0x1” is set in the clock control register 1206, a 1 MHz clock is supplied to the CPU 201, and the normal operation state is restored.

  As described above, in this embodiment, the state detection block 3206 polls the setting of the port status register 1204 and detects the states of the external terminals P0 to P7. Based on the detection result of the state detection block 3206, the condition determination block 207 determines whether or not a condition for returning the system from the low power consumption state to the normal operation state is satisfied. When the condition for returning the system from the low power consumption state to the normal operation state is satisfied, the bus transfer control block 1208 makes a write request (write transfer request) to the clock control register 1206 to the bus master function block 3205. The bus master function block 3205 issues a rewrite instruction (write transfer) to the clock control register 1206 in accordance with the write transfer request made from the bus transfer control block 1208. In the clock control module 1205, the clock control register 1206 changes the set value of the clock control register 1206 according to the write transfer. Then, the CPU 201 returns the system from the low power consumption state to the normal operation state according to the change.

  As a result, the bus master circuit 3202 satisfies the condition that the port status register 1204 is polled instead of the CPU 201 to return to the normal operation state even when the CPU 201 is stopped in the low power consumption state. Can be detected. Then, the bus master circuit 3202 can set the clock control register 1206. Accordingly, the clock control register 1206 can be set without performing interrupt processing to the CPU 201 to return to the normal operation state. Thus, the load on the CPU 201 can be reduced and the processing speed when detecting the internal state of the port control module 1203 (port status register 1204) can be improved. Further, since it is not necessary to provide a plurality of processors (CPUs), it is possible to prevent the area of the system LSI from being increased by hardware for detecting the internal state of the port control module 1203 (port status register 1204). In addition, since the address of the register to be rewritten and the contents of the data are set in a programmable manner, various hardware can be controlled in various forms.

  In this embodiment, the hardware to be polled by the bus master circuit 3202 is the port control module 1203. However, as in the first and second embodiments, the object to be polled by the bus master circuit 3202 is not limited to this. . That is, any hardware module provided with a register for displaying an internal state inside the hardware can be polled.

  In this embodiment, the setting target register is the clock control register 1206 in the clock control module 1205. However, the setting target register is not limited to this. That is, any hardware module having a register that can be set by bus transfer can be set as a register in any hardware module.

In this embodiment, the bus transfer control block 1208 requests write transfer from the bus master function block 3205. However, it is not always necessary to request write transfer. For example, a request for reading the internal state of the hardware module (read transfer request) may be made. In addition, a data write request (read-modify-write transfer request) may be performed by performing an operation on a predetermined bit according to data read by performing read transfer. Further, the CPU 201 may be able to set the clock control register 1206 in a programmable manner during the normal operation state.
A plurality of transfer address registers 1216 and transfer data registers 1217 may be provided so that the bus transfer control block 1208 can perform a write request or the like with a plurality of registers as setting targets.

Similarly to the second embodiment, a polling cycle setting register 2217 and a timer function block 206c may be provided so that polling is requested at a cycle set in the polling cycle setting register 2217. In this way, the load on the system bus 108 can be further reduced.
In this embodiment, a transfer direction register is further provided, and the transfer direction can be set programmable by using this transfer direction register.

(Other embodiments of the present invention)
In order to operate various devices to realize the functions of the above-described embodiments, program codes of software for realizing the functions of the above-described embodiments are provided to an apparatus or a computer in the system connected to the various devices. You may supply. What was implemented by operating said various devices according to the program stored in the computer (CPU or MPU) of the system or apparatus is also included in the category of the present invention.

  In this case, the program code of the software itself realizes the functions of the above-described embodiment. The program code itself and means for supplying the program code to a computer, for example, a recording medium storing the program code constitute the present invention. As a recording medium for storing the program code, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

  Further, the functions of the above-described embodiments are not only realized by executing the program code supplied by the computer. It goes without saying that the program code is also included in the embodiment of the present invention even when the function of the above-described embodiment is realized in cooperation with an operating system or other application software running on the computer. Yes.

Further, after the supplied program code is stored in the memory provided in the function expansion board of the computer, the CPU provided in the function expansion board performs part or all of the actual processing based on the instruction of the program code. Needless to say, the present invention includes the case where the functions of the above-described embodiments are realized by the processing.
Further, after the supplied program code is stored in the memory provided in the function expansion unit connected to the computer, the CPU or the like provided in the function expansion unit performs part or all of the actual processing based on the instruction of the program code. Do. Needless to say, the present invention includes the case where the functions of the above-described embodiments are realized by the processing.

  Note that each of the above-described embodiments is merely a specific example for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. . That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

1 is a diagram illustrating an example of a basic configuration of a bus master circuit according to a first embodiment of this invention. FIG. 1 is a diagram illustrating an example of a configuration of a system LSI including a bus master circuit that generates an interrupt signal for a CPU according to the first embodiment of this invention. FIG. It is a figure which shows the 1st Embodiment of this invention and shows an example of a structure of a condition determination block. It is a figure which shows the 1st Embodiment of this invention and shows an example of a structure of the interrupt signal generation block. It is a figure which shows the 1st Embodiment of this invention and shows an example of the specification of a control register group. It is a figure which shows the 1st Embodiment of this invention and shows an example of the specification of a data pointer register. 5 is a flowchart illustrating an example of an operation of a state detection block when a read request is made to the bus master functional block according to the first embodiment of this invention. 5 is a flowchart illustrating an example of an operation of an interrupt signal generation block according to the first embodiment of this invention. FIG. 10 is a diagram illustrating an example of a configuration of a system LSI including a bus master circuit that generates an interrupt signal for a CPU according to the second embodiment of this invention. It is a figure which shows the 2nd Embodiment of this invention and shows an example of the specification of a polling period setting register. 10 is a flowchart illustrating an example of an operation of a state detection block when a read request is made to a bus master function block according to the second embodiment of this invention. It is a timing chart which shows the 2nd Embodiment of this invention and demonstrates an example of the operation | movement of a state detection block at the time of making the next polling request wait for 3 cycles. FIG. 10 is a diagram illustrating an example of a configuration of a system LSI including a bus master circuit that performs setting of a register of a clock control module according to a third embodiment of this invention. It is a figure which shows the 3rd Embodiment of this invention and shows an example of the specification of a transfer address register, and an example of the specification of a transfer data register. It is a figure which shows the 3rd Embodiment of this invention and shows an example of the specification of a port status register, and an example of the specification of a clock control register. The flowchart which shows the 3rd Embodiment of this invention and demonstrates an example of operation | movement of the bus transfer control block at the time of performing the request | requirement of the write transfer to a bus master functional block, and the output of the signal (Clear) to a polling control register It is.

Explanation of symbols

101, 202, 2202, 3202 Bus master circuit 102, 205, 3205 Bus master function block 103, 206, 2206 Status detection block 104, 207 Condition determination block 105 Hardware control block 106, 209, 2209, 3209 Control register group 107, 210 Bus Slave function block 108 System bus 201 CPU
203 External Communication Module 204 FIFO Data Pointer Register 208 Interrupt Signal Generation Block 1203 Port Control Module 1204 Port Status Register 1205 Clock Control Module 1206 Clock Control Register 1208 Bus Transfer Control Block

Claims (23)

A bus master circuit interconnected with a processor and one or more hardware via a bus,
Detecting means for accessing the bus as a bus master and detecting a state of hardware connected to each other via the bus;
Discriminating means for discriminating the state of the hardware detected by the detecting means;
Generating means for generating a control signal based on the hardware state determined by the determining means;
An output means for outputting the control signal generated by the generating means to the bus. The generation unit generates an interrupt signal for processors connected to each other via the bus based on the hardware state determined by the determination unit;
The bus master circuit according to claim 1, wherein the output unit outputs the interrupt signal generated by the generation unit to the processor via the bus. The generation unit generates a control signal related to the operation of the second hardware different from the hardware based on the hardware state determined by the determination unit;
The bus master circuit according to claim 1, wherein the output unit outputs the control signal generated by the generation unit to the second hardware via the bus.   The generation unit generates a control signal for controlling a clock supplied to processors connected to each other via the bus based on a hardware state determined by the determination unit. The bus master circuit according to claim 3.   5. The bus master circuit according to claim 1, wherein the detection unit detects a state of hardware connected to each other via a bus at an interval. An interval setting means in which an interval for detecting the state of hardware connected to each other via the bus is set in a programmable manner;
6. The bus master circuit according to claim 5, wherein the detection unit detects a state of hardware connected to each other via a bus at an interval set in the interval setting unit.   The bus master circuit according to claim 1, wherein the output unit accesses the bus according to a preset content of a control signal generated by the generation unit. Output destination address setting means in which an output destination address of the control signal is set in a programmable manner;
Data setting means in which data included in the control signal is set in a programmable manner;
The generating means generates a control signal including data set in the data setting means,
8. The bus master circuit according to claim 7, wherein the output unit outputs the control signal generated by the generation unit to the address set in the output destination address setting unit via the bus.   9. The bus master circuit according to claim 8, further comprising: a transfer direction setting unit that programmably sets a data transfer direction set in the data setting unit. A hardware address setting unit in which a hardware address detected by the detection unit is set in a programmable manner;
The bus master circuit according to claim 1, wherein the detection unit detects a hardware state of an address set in the hardware address setting unit. Having condition setting means in which a condition for determining the state of the hardware detected by the detection means is set in a programmable manner;
11. The determination unit according to claim 1, wherein the determination unit determines whether a hardware state detected by the detection unit corresponds to a condition set in the condition setting unit. The bus master circuit according to item. A detection step of accessing the bus as a bus master and detecting the state of hardware interconnected via the bus;
A determination step of determining the state of the hardware detected by the detection step;
A generation step of generating a control signal based on the hardware state determined by the determination step;
A bus control method comprising: an output step of outputting the control signal generated in the generation step to the bus. The generation step generates an interrupt signal for processors connected to each other via the bus based on the hardware state determined by the determination step;
13. The bus control method according to claim 12, wherein the output step outputs the interrupt signal generated by the generation step to the processor via the bus. The generation step generates a control signal related to the operation of second hardware different from the hardware based on the hardware state determined by the determination step;
13. The bus control method according to claim 12, wherein the output step outputs the control signal generated by the generation step to the second hardware via the bus.   The generation step generates a control signal for controlling a clock supplied to processors connected to each other via the bus based on a hardware state determined by the determination step. The bus control method according to claim 14.   The bus control method according to any one of claims 12 to 15, wherein the detecting step detects a state of hardware connected to each other via a bus at an interval. An interval setting step for programmably setting an interval for detecting the state of hardware connected to each other via the bus;
17. The bus control method according to claim 16, wherein the detecting step detects a state of hardware connected to each other via a bus at an interval set by the interval setting step.   18. The bus control method according to claim 12, wherein the output step accesses the bus according to a preset content of the control signal generated in the generation step. An output destination address setting step for programmably setting an output destination address of the control signal;
A data setting step for programmably setting data included in the control signal,
The generation step generates a control signal including the data set by the data setting step,
19. The bus control method according to claim 18, wherein the output step outputs the control signal generated by the generation step to the address set by the output destination address setting step via the bus. .   20. The bus control method according to claim 19, further comprising a transfer direction setting step for programmably setting the transfer direction of the data set by the data setting step. A hardware address setting step for programmably setting a hardware address detected by the detection step;
21. The bus control method according to claim 12, wherein the detecting step detects a hardware state of the address set by the hardware address setting step. A condition setting step for programmably setting a condition for determining the state of the hardware detected by the detection step;
The determination step determines whether or not the hardware state detected by the detection step corresponds to the condition set by the condition setting step. The bus control method according to item. A detection step of accessing the bus as a bus master and detecting the state of hardware interconnected via the bus;
A determination step of determining the state of the hardware detected by the detection step;
A generation step of generating a control signal based on the hardware state determined by the determination step;
A computer program causing a computer to execute an output step of outputting the control signal generated in the generation step to the bus.

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