JP2008015918A - Disk drive and disk controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correctly write write data in a disk even though power failure is generated in the case of further transferring the write data to a cache memory in which valid write data exists. <P>SOLUTION: This disk controller 10 for controlling the writing of data from a host computer 17 into the disk 15 is provided with a nonvolatile cache memory 12 for storing the data from the host computer to be written in the disk, a nonvolatile storage area 11 for storing the data from the host computer and a data transferring means 31. The data transferring means acquires the data from the host computer, writes the acquired data in the storage area, transfers the data written in the storage area to the cache memory, acquires the next data from the host computer and writes the acquired data in the storage area. When data transfer is interrupted because of power failure, the data written in the storage area is transferred again to the cache memory when the power is recovered. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a disk controller for controlling data transfer to a disk device, and a disk device incorporating such a disk controller. More specifically, the present invention relates to a case where a power failure occurs during data transfer from a host computer. The present invention also relates to a disk device and a disk controller for protecting data.

  FIG. 19 shows a disk device 190 for writing data from the host computer 200 to the disk 192. The disk device 190 includes a non-volatile cache memory 191. Before the write data to the disk 192 (all values are 1 in the example shown in FIG. 19) is acquired from the host computer 200 and written to the disk 192. The state once held in the cache memory 191 is shown.

  Normally, after this, write data is written to the disk 192 due to an elapse of a certain time or an event such as a shortage of the cache memory 191. In the unlikely event that a power failure occurs before writing to the disk 192, the data in the cache memory 191 is backed up and held by a battery or the like.

  When power is supplied again, the disk device 190 recognizes that there is data that has not been written to the disk 192 in the cache memory 191 when performing the startup process, and writes write data to the disk 192. Data loss due to power failure is prevented.

  On the other hand, when the host computer 200 further executes another write command to the same disk position 60 in the state shown in FIG. 19, as shown in FIG. 20, new write data (shown in FIG. 20) from the host computer 200 is obtained. In the example, all values 2) are transferred to the cache memory 191 by DMA (direct memory access). FIG. 21 shows a state during the transfer.

  When a power failure occurs in the middle of the transfer as shown in FIG. 21, since the write data is being DMA-transferred, some of the data is new data (value is 2) and some is old data (value is 1). turn into.

  When power is supplied again in this state, the disk device 190 is in a state where new data having a value of 2 and old data having a value of 1 are mixed in order to write these write data to the disk 192.

  In general, in a disk device that does not have a cache memory for delayed writing, writing to one sector (usually 512 bytes), which is the smallest unit, is performed in the following (1) to (3) in response to a power failure It will be in either state.

  (1) Old data (for example, all values are 1) is written in the entire area (512 bytes), and when read, the value 1 can be read.

  (2) New data (for example, all values are 2) is written in the entire area (512 bytes), and when read, the value 2 can be read.

(3) A media error occurs and the entire area (512 bytes) cannot be read.
JP 2003-330627 A JP 2004-342037 A

  However, such a conventional disk device has the following problems.

  That is, in the case shown in FIG. 21, in the conventional disk device, unlike any of the above (1) to (3), for example, old data with a value of 1, for example, and new data with a value of 2, for example. Data mixed with data is read out. This causes a problem that the operation is different from that of the disk for delayed writing, which may cause a problem.

  In the DMA transfer, in the disk device 190 having a mechanism for encrypting or decrypting data from the host computer 200, when the block cipher is adopted as the encryption algorithm, the data is read from the state of FIG. For example, even old data with a value of 1 or new data with a value of 2, for example, is read, which may cause a problem.

  As a technique related to the solution of these problems, for example, there is Patent Document 1, which saves the data in the DMA to a nonvolatile memory at the time when a voltage drop due to a power failure occurs. It does not solve. Further, Patent Document 2 discloses a method of writing back the contents of the cache memory to the disk device before performing DMA transfer, but with this method, DMA transfer cannot be performed immediately.

  The present invention has been made in view of such circumstances. Even when a power failure occurs when the write data is further transferred to a cache memory in which valid write data exists, the write data can be correctly written to the disk. It is an object of the present invention to provide a possible disk device and a disk controller.

  In order to achieve the above object, the present invention takes the following measures.

  That is, the invention of claim 1 is a disk controller for controlling writing of data from the host computer to the disk, and includes a nonvolatile cache memory for storing data from the host computer to be written to the disk, and the host computer. A non-volatile storage area for storing a predetermined amount of data, and a data transfer means.

  The data transfer means acquires a predetermined amount of data from the host computer, writes the acquired predetermined amount of data to the nonvolatile storage area, and then stores the predetermined amount of data written to the nonvolatile storage area. The data is transferred to the memory, and after the transfer, a predetermined amount of next data is acquired from the host computer, and the acquired data is written in the nonvolatile storage area. When data transfer is interrupted due to a power failure, a predetermined amount of data written in the nonvolatile storage area is transferred again to the nonvolatile cache memory at the time of power recovery.

  The invention according to claim 2 is the disk controller according to claim 1, wherein the nonvolatile storage area is provided in a nonvolatile cache memory or data transfer means.

  Furthermore, the invention of claim 3 is a disk controller that controls writing of data from the host computer to the disk, and can store data from the host computer as cache data to be written to the disk. A non-volatile cache memory having two storage areas, and data transfer means for acquiring data from the host computer and transferring the acquired data to the non-volatile cache memory.

  The non-volatile cache memory stores data as cache data in one of the two storage areas when data is transferred from the data transfer means, and stores either of the two storage areas. When data is transferred from the data transfer means in a state where cache data is stored in one of the storage areas, the transferred data is stored in the other storage area of the two storage areas. After the transfer is completed, the data stored in the other storage area is used as new cache data, and the data can be stored in one storage area.

  The fourth to sixth aspects of the present invention are disk devices each including the disk controller of the first to third aspects of the invention.

  According to the present invention, it is possible to realize a disk device and a discontroller capable of correctly writing write data to a disk even if a power failure occurs when the write data is further transferred to a cache memory in which valid write data exists. be able to.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
The disk controller according to the first embodiment will be described.

  FIG. 1 is a functional block diagram showing a configuration example of the disk controller 10 according to the first embodiment.

  That is, the disk controller 10 according to the present embodiment is built in the host computer 17 and is used to write data from the memory 18 of the host computer 17 to the disk 15 in the disk device 16. A cache memory 12, a disk control unit 13, and a cache management table 14 are provided.

  In FIG. 1, with respect to the host computer 17, for simplicity, only the memory 18 and the driver 19, which are components related to the present embodiment, are shown in addition to the disk controller 10.

  The memory 18 stores data to be written to the disk 15 or read from the disk 15.

  The driver 19 transmits a read (read) or write (write) command to the disk controller 13 to the disk controller 10 such as a RAID controller, and mediates access to the disk 15.

  The disk controller 10 such as a RAID controller is built in the host computer 17 and is connected to each part in the host computer 17 via an IO bus such as PCI, PCI-X, and PCI Express.

  The disk control unit 13 performs configuration management of the disk (or RAID) 15, control of the disk 15, and the like. Particularly relevant in the present embodiment is the function of receiving a command from the driver 19, processing it, and returning the result to the driver 19. Further, in the command processing, the DMA controller 11, the cache memory 12, and the cache management table 14 are used.

  The cache memory 12 holds data to be written to the disk 15 and data read from the disk 15. Since the data to be written to the disk 15 is temporarily stored, the contents are not lost even if the power supply to the disk controller 10 is interrupted so that the data is not lost due to interruption of processing due to a power failure or the like. Constitute.

  Similarly to the cache memory 12, the cache management table 14 is arranged on a non-volatile storage medium, and holds management information of data held on the cache memory 12 as shown in FIG. The management information items include a cache block number 14a, a disk number 14b, a disk address 14c, a used / unused state 14d, the presence / absence of write data 14e, and a lock state 14f.

  In this specification, for the sake of explanation, the management unit (cache block) of the cache memory 12 has the same size as the sector of the disk 15. The size of the cache block may be a multiple of the disk sector for performance and management efficiency. In this case, the structure of the cache management table 14 may be partially different from that shown in FIG. Since there is no relationship with the use in the embodiment, no further explanation will be given.

  The cache management table 14 has entries for all cache blocks on the cache memory 12 as the cache block number 14a. That is, one entry corresponds to the cache block on a one-to-one basis. The disk number 14b and the disk address 14c are information indicating the position of the disk corresponding to the data stored in the cache block. The item of used / unused state 14d indicates whether a cache block is used or not used. The presence / absence 14e of the write data indicates whether there is data not written out by the disk 15 on the cache block. The lock state 14f indicates whether this entry is locked.

  The DMA controller 11 is a part that receives a data transfer command from the disk controller 13 and controls data transfer between the host computer 17 and the cache memory 12. A configuration example of such a DMA controller 11 is shown in a functional block diagram of FIG. As shown in FIG. 3, the DMA controller 11 includes a command buffer 30, a transfer control unit 31, first and second transfer engines 32 and 33, a data buffer 34, a transmission pointer 35, and a reception pointer 36.

  The command buffer 30 stores specific instruction commands and parameters for data transfer performed by the DMA controller 11.

  The transfer control unit 31 controls the first and second transfer engines 32 and 33 to transfer data based on a command for performing a specific instruction stored in the command buffer 30, and sends a response to the disk control unit. Return to 13.

  The first and second transfer engines 32 and 33 manage data transfer to the data buffer 34 and the cache memory 12 or the memory 18 of the host computer 17.

  The data buffer 34 is composed of a nonvolatile storage medium and holds data being transferred. The size of the data buffer is larger than the sector size (usually 512 bytes) of the disk 15, which is the minimum unit of data transfer between the host computer 17 and the disk controller 10.

  The transmission pointer 35 and the reception pointer 36 are also on the non-volatile storage medium and are used for data transmission / reception management on the data buffer 34.

  Commands for the DMA controller 11 stored in the command buffer 30 include (1) data transfer (transmission or reception) for transfer from the cache memory 12 of the disk controller 10 to the host computer 17 or in the opposite direction. There is a command. The data transfer command has parameters of a transmission source and a transmission destination and a transfer size as parameters. Other commands include (2) a data retransmission command for the data buffer 34. This command is a command for retransferring data stored in the data buffer 34.

  Next, the flow of processing performed by the transfer control unit 31 using such a command will be described with reference to the flowchart of FIG.

  The command buffer 30 receives the command sent from the disk control unit 13 via the transfer control unit 31 (S41). If this command is a data transfer command (S42: Yes) and the transmission source is the memory 18 of the host computer 17 (S43: Yes), data transfer from the host computer 17 to the cache memory 12 is performed. Processing is performed (S44).

  On the other hand, if the transmission source of the data transfer command is not the memory 18 of the host computer 17 (S43: No), a data transfer process for transferring the data in the cache memory 12 to the memory 18 of the host computer 17 is performed (S45).

  Furthermore, if it is not a data transfer command in step S42 (S42: No), a data retransfer process is performed (S46).

  After the processing of steps S44 to S46, the transfer control unit 31 returns command completion to the disk control unit 13 (S47).

  The data buffer 34 uses a transmission pointer 35 and a reception pointer 36 in data transfer processing performed between the memory 18 of the host computer 17 and the cache memory 12. That is, in the data transfer process, the data buffer 34 is ringed by using the transmission pointer 35 indicating the end of the data that has been transmitted to the cache memory 12 and the reception pointer 36 indicating the beginning of the data from the host computer 17. It is controlled as a buffer. A method of using the transmission pointer 35 and the reception pointer 36 will be described with reference to FIG.

  FIG. 5A shows the initial positions of the transmission pointer 35 and the reception pointer 36 in the data in the data buffer 34. When the data buffer 34 receives data, the received data is accumulated between the transmission pointer 35 and the reception pointer 36, so that the reception pointer 36 moves rightward in the figure as shown in FIG. 5B. That is, the reception pointer 36 indicates the beginning of data received from the host computer 17, and the transmission pointer 35 indicates the end of data that has been transmitted to the cache memory 12.

  Transfer processing from the memory 18 of the host computer 17 to the cache memory 12 performed in step S44 (performed by the first transfer engine 32), and transfer processing from the cache memory 12 to the memory 18 performed in step S45 (first step). 2) is performed in parallel to improve transfer efficiency. FIG. 6 is a flowchart showing a flow of processing in which the transfer control unit 31 sends instructions to the first transfer engine 32 and the second transfer engine 33 when performing the processing in step S44 and the processing in step S45. . In FIG. 6, first, in step S61, the first transfer engine 32 is instructed to start processing. In step S62, the second transfer engine 33 is instructed to start processing. In step S63, the first transfer engine 32 is instructed. Although the processing of the second transfer engine 33 is waited for to be completed, the processing in step S61 and step S62 may be performed simultaneously or in the reverse order.

  FIG. 7 is a flowchart showing details of the flow of processing by the first transfer engine 32 performed in step S61.

  The first transfer engine 32 transfers data corresponding to the command transfer size stored in the command buffer 30 from the memory 18 of the host computer 17 to the data buffer 34. If this data transfer is completed (S71: Yes), the process is terminated.

  If it has not been completed (S71: No), it is confirmed whether or not there is an empty space in the data buffer 34 (S72). As shown in FIG. 8, the data buffer 34 is filled with received data and can receive data until the reception pointer 36 is adjacent to the transmission pointer 35. Therefore, the reception pointer 36 transmits as shown in FIG. If it is adjacent to the pointer 35, there is no space (S72: No), and if it is not adjacent, it is determined that there is a space (S72: Yes). If there is no space, the process of step S72 is repeated, and if there is a space, the process proceeds to step S73. In practice, because of the ring buffer, this condition determination alone may not be sufficient (in the case of straddling the boundary), but the description thereof is omitted.

  In step S73, data is transferred from the memory 18 of the host computer 17 to the data buffer 34 (S73). At this time, the amount of data to be transferred is set to a smaller amount of the free space of the data buffer 34 (which can be calculated from the difference between the transmission pointer 35 and the reception pointer 36) or the remaining amount of data to be transferred, and data transfer is executed. To do. When the transfer is executed, the reception pointer 36 is advanced by the transfer amount (S74).

  FIG. 9 is a flowchart showing details of the flow of processing by the second transfer engine 33 performed in step S62.

  That is, the second transfer engine 33 transfers data corresponding to the command transfer size stored in the command buffer 30 from the data buffer 34 to the cache memory 12. If this data transfer is completed (S91: Yes), the process is terminated.

  If not completed (S91: No), it is confirmed whether or not there is data of 512 bytes or more in the data buffer 34 (S92). If not, the process in step S92 is repeated, and if there is, the process proceeds to step S93.

  In step S93, data is transferred from the data buffer 34 to the cache memory 12 (S93). When the transfer is executed, the reception pointer 36 is advanced by the transfer amount (S94).

  As described above, when 512 bytes of data are accumulated in the data buffer 34, the second transfer engine 33 transfers the data to the cache memory 12 for every 512 bytes of data. By transferring in this way, the cache memory during data transfer can be limited to an area of 512 bytes. Also, since 512 bytes of data are always stored in the data buffer 34, even if the processing is interrupted due to a power failure or the like, 512 bytes of data being transferred to the data buffer 34 at the next execution will not be stored. As shown in the flowchart of FIG. 10, it is determined whether or not data of 512 bytes or more remains in the data buffer 34 (S101). This is determined from the values of the reception pointer 36 and the transmission pointer 35 as described above. If it remains (S101: Yes), data is transferred again from the data buffer 34 to the cache memory 12 by a multiple of 512 bytes (S102). This is completely reflected in the cache memory 12.

  Next, the processing of the disk control unit 13 will be described using the flowchart shown in FIG.

  The disk control unit 13 processes an access command from the driver 19 of the host computer 17 to the disk 15. FIG. 11 shows the flow of processing from the driver 19 of the host computer 17. When the driver 19 of the host computer 17 operates as an OS module and receives an access request to the disk 15 from a file system or an application, it passes it to the disk controller 13 (S111). The disk control unit 13 processes this access request (S112), and returns a response by interrupting the host computer 17, for example (S113). At this time, the memory 18 on the host computer 17 is used as a buffer for data exchange. Then, the interrupt process of the driver 19 operates to complete the request process to the disk 15 (S114).

  In the case of a read request from the disk 15, the data read from the disk 15 is finally read into the memory 18 of the host computer 17. In the case of a write request to the disk 15, data in the memory 18 of the host computer 17 is written to the disk 15.

  Next, a flow in which the disk control unit 13 processes a request will be described with reference to the flowchart of FIG. Since the present invention is effective in the process at the time of a write request to the disk 15, FIG. 12 shows the process at the time of a write request.

  The write request received by the disk control unit 13 is actually composed of the target disk 15 and its offset, the size of the write data, and the memory address of the host computer 17 in which the data to be written is stored. Then, based on the target disk 15, the offset, and its size, processing for securing a corresponding area on the cache memory 12 is performed. Data from the memory 18 of the host computer 17 is stored on the cache memory 12 secured here.

  In the flowchart shown in FIG. 12, in order to secure the cache memory 12 corresponding to the entire write data area, the allocation and locking of the cache memory 12 are repeatedly performed (S120). Allocation of the cache memory 12 can be determined by searching whether the cache management table 14 already has an entry corresponding to the disk 15 and the offset.

  When the cache memory 12 is not assigned to all of the write data (S120: No), the cache memory 12 is already assigned (S126: Yes), and is locked (S127: Yes). Since it cannot be overwritten, it waits until the lock is released. If it is not locked (S127: No), locking is performed (S128), and the process returns to step S120. The lock state is managed by the value of the lock state 14f of the cache management table 14 shown in FIG.

  When the cache memory 12 is not allocated (S126: No), the free space of the cache memory 12 is searched, a corresponding entry is created in the cache management table 14 (S129), and the process proceeds to step S128. As contents, disk number 14b, used / unused (in use) 14d, and offset are set.

  When all the cache memories 12 are secured in this way (S120: Yes), the DMA controller 11 is instructed to transfer data (S121). The DMA controller 11 starts data transfer processing between the host computer 17 and the cache memory 12 shown in FIG. 6 (S122).

  When the data transfer is completed, it is recorded in the cache management table 14 that write data exists for the corresponding entry (S123), and the request 19 is returned to the driver 19 (S124). Is unlocked (S125), and the process is completed.

  Next, data writing from the cache memory 12 to the disk 15 will be described.

  In the write command processing as shown in FIG. 12, the data to be written is copied onto the cache memory 12 but is not actually written on the disk 15. Therefore, the disk control unit 13 performs a process of writing the data on the cache memory 12 to the disk 15 as shown in FIG. 13 at regular time intervals or according to the usage state of the cache memory 12.

  That is, when the cache data continues to be written (S131: No), if valid data exists in the cache memory 12 (S132: No), the cache data is selected (S133), locked (S134), and the disk 15 Is written (S135), no write data is set (S136), the lock is released (S137), and the process returns to step S131.

  As described above, the end of the writing of the cache data is determined depending on whether or not to end the writing based on a certain amount or the ratio of the write data on the cache memory 12. When writing, the cache management table 14 is searched to select an entry that holds write data. The entry is selected using a method such as LRU. The selected data in the cache memory 12 is locked using the cache management table 14 and written to the disk 15.

  Next, a recovery method for writing back the data in the cache memory 12 to the disk 15 upon restart from an unexpected stop such as a power failure will be described using the flowchart shown in FIG.

  The processing shown in the flowchart of FIG. 14 differs from normal cache data write-back in that the DMA controller 11 is instructed to perform retransfer in step S142. As a result, the data being transferred held in the DMA controller 11 is retransferred to the cache memory 12 in units of sectors on the disk 15. As a result of this processing, the cache data in which the data is interrupted in the middle of the transfer on the cache memory 12 becomes correct in units of sectors of the disk 15, and the contents of the cache data are inconsistent due to an unexpected stop due to a power failure or the like. To avoid.

  As described above, in the disk controller 10 according to the present embodiment, even if a power failure occurs when the write data is further transferred to the cache memory 12 having valid write data due to the above-described operation, The cache data in which the data is interrupted in the middle of the transfer on the cache memory 12 becomes correct in units of sectors on the disk 15, and it is possible to avoid inconsistencies in the contents of the cache data.

(Second Embodiment)
FIG. 15 is a functional block diagram including a configuration example of the disk controller 150 according to the second embodiment.

  The disk controller 150 according to the present embodiment is a modification of the disk controller 10 according to the first embodiment. Therefore, the same parts are denoted by the same reference numerals to avoid overlapping explanations, and different points will be described.

  The disk controller 10 according to the first embodiment is built in the host computer 17, but the disk controller 150 according to the present embodiment is built in the disk device 16.

  In addition to being built in the disk device 16 instead of the host computer 17, the difference from the first embodiment is that a SCSI (registered trademark) controller 151 is added as an interface for communicating with the host computer 17. is there.

  Similarly, a SCSI (registered trademark) controller 152 which is an interface for communicating with the disk controller 10 is also added to the host computer 17.

  By connecting the SCSI controller 151 and the SCSI controller 152, the host computer 17 and the disk device 16 can communicate with each other.

  In the first embodiment, as shown in FIG. 1, data is directly exchanged between the DMA controller 11 and the memory 18, but in this embodiment, data between the DMA controller 11 and the memory 18 is transferred. The exchange is performed via the SCSI controllers 151 and 152. Except for this point, the DMA controller 11, cache memory 12, disk control unit 13, and cache management table 14, which are other parts in the disk controller 150, have the same functions as those described in the first embodiment. Have.

  The interface between the disk device 16 and the host computer 17 is not limited to the SCSI controller, and FC (FiberChannel) or other interfaces can be similarly implemented.

  Further, the SCSI controller 151 and the DMA controller 11 may be integrated and the SCSI controller 151 may have the function of the DMA controller 11 in the first embodiment.

  As described above, in the disk controller 150 according to the present embodiment, due to the above-described operation, even if the disk controller 150 is built in the disk device 16 instead of the host computer 17, the first embodiment. As in the case of the disk controller 10, even if a power failure occurs when the write data is further transferred to the cache memory 12 in which valid write data exists, the write data can be correctly written to the disk 15.

(Third embodiment)
FIG. 16 is a functional block diagram including a configuration example of the disk controller 160 according to the third embodiment.

  The disk controller 160 according to the present embodiment is also a modification of the disk controller 10 according to the first embodiment. Therefore, the same parts are denoted by the same reference numerals to avoid overlapping explanations, and different points will be described.

  That is, the disk controller 160 according to the present embodiment is different only in that a data transfer unit 161 is provided instead of the DMA controller 11 in the disk controller 10 according to the first embodiment shown in FIG.

  Unlike the DMA controller 11, the data transfer unit 161 performs only data transfer and does not include a nonvolatile storage medium such as the data buffer 34, the transmission pointer 35, and the reception pointer 36. Further, neither the command buffer 30 nor the transfer control unit 31 is provided.

  The disk controller 160 according to the present embodiment having such a configuration differs from the first embodiment in the management method of the cache memory 12 during data transfer.

  In other words, in the disk controller 160 according to the present embodiment, when the write data is transferred again to the cache memory 12 that already holds the write data, a temporary area is secured on the cache memory 12 and the data is transferred. . When the data transfer is completed, the temporary area is set as the original cache data, and the cache area up to that point is released. By doing so, it is possible to avoid an overwriting state due to data transfer to write data on the cache memory 12, and to prevent data inconsistency due to interruption of data transfer.

  A cache management method at the time of write request processing by the disk controller 160 according to the present embodiment having such a configuration will be described with reference to the flowchart shown in FIG.

  In the flowchart shown in FIG. 17, steps that perform the same processing as the flowchart shown in FIG. 12 are given the same step numbers. Therefore, step S170 thru | or step S172 are demonstrated here.

  In step S170, if there is already write data on the cache memory 12, a temporary area is secured on the cache memory 12 to avoid overwriting.

  In step S171, the temporary area secured in step S170 is designated as the data transfer destination from the memory 18 of the host computer 17 to the data transfer unit 161.

  In step S172, the temporary area is set as a cache area, and the cache area that has been holding data is released.

  As described above, the disk controller 160 according to the present embodiment includes the DMA controller 11 having nonvolatile storage areas such as the data buffer 34, the transmission pointer 35, and the reception pointer 36 due to the above-described operation. Even if there is no data, the data transfer unit 161 having a data transfer function is used, and a temporary cache area is secured on the cache memory 12 to further write data to the cache memory 12 where valid write data exists. Even if a power failure occurs when transferring the write data, the write data can be correctly written to the disk 15.

(Fourth embodiment)
FIG. 18 is a functional block diagram including a configuration example of the disk controller 180 according to the fourth embodiment.

  The disk controller 180 according to the present embodiment is a modification of the disk controller 10 according to the first embodiment. Therefore, the same parts are denoted by the same reference numerals to avoid overlapping explanations, and different points will be described.

  That is, the disk controller 180 according to the present embodiment has a configuration in which the encryption device 181 is added between the DMA controller 11 and the cache memory 12 in the disk controller 10 according to the first embodiment.

  The encryption device 181 receives the data in the memory 18 of the host computer 17 from the DMA controller 11, encrypts the data, and stores it in the cache memory 12. On the contrary, when data is stored from the cache memory 12 to the memory 18 of the host computer 17 via the DMA controller 11, the data is decrypted and passed to the DMA controller 11. The encryption algorithm executed by the encryption device 181 is assumed to be a block cipher such as AES or DES, but these are examples and are not limited.

  In such an implementation, all data from the host computer 17 is encrypted on the cache memory 12. Accordingly, all data from the host computer 17 is encrypted and stored in the disk 15.

  In this case, when the transfer is interrupted due to a power failure or the like, as already described in [Background Art], the data first transferred from the host computer 17 and the encrypted data of the data being DMA-transferred are stored in the cache memory. 12 is mixed up. In FIG. 21, as an example, the cache memory 191 shows a state in which data having only a value of 1 or 2 is stored. Instead, data in which the value is encrypted is stored. .

  If the operation is started again from this state and the contents of the cache memory 12 are written to the disk 15, the contents of the disk 15 are read from the host computer 17, and the ciphertext of the old data and the new data is read. Is read from the disk 15 to the cache memory 12, and the data is decoded. In the subsequent read access, data that is neither old data nor new data is read out.

  When ciphertexts are mixed in this way, decryption cannot be performed correctly, and data that is neither old data nor new data may be decrypted and returned to the host computer 17.

  In this embodiment, by performing the same processing as in the first embodiment for the portions other than the encryption processing, the ciphertext of the data being transferred to the cache memory 12 is completely transferred. Therefore, avoid the situation where ciphertext is mixed.

  As described above, in the disk controller 180 according to the present embodiment, due to the above-described operation, even if data encryption is involved, the first part is not applied to the part other than the encryption process. By performing the same processing as in the embodiment, the ciphertext of the data being transferred to the cache memory 12 can be completely transferred.

  As a result, a mixed state of ciphertexts is avoided, and even if a power failure occurs when the write data is further transferred to the cache memory 12 where valid write data exists, the write data can be correctly written to the disk 15. It becomes.

  The best mode for carrying out the present invention has been described above with reference to the accompanying drawings, but the present invention is not limited to such a configuration. Within the scope of the invented technical idea of the scope of claims, a person skilled in the art can conceive of various changes and modifications. The technical scope of the present invention is also applicable to these changes and modifications. It is understood that it belongs to.

1 is a functional block diagram showing a configuration example of a disk controller according to a first embodiment. The data block diagram which shows an example of a cache management table. The functional block diagram which shows the structural example of a DMA controller. The flowchart which shows the flow of the transfer process by a transfer control part. The figure which shows the data buffer used as a ring buffer by the transmission pointer and the reception pointer. The flowchart which shows the flow of the process in which a transfer control part sends an instruction | indication to the 1st and 2nd transfer engine. The flowchart which shows the detail of the flow of a process by the 1st transfer engine performed by step S61. The figure which shows the data buffer of the state filled with reception data. The flowchart which shows the detail of the flow of a process by the 2nd transfer engine performed by step S62. The flowchart which shows the flow of a process in the case of restarting a data transfer process. The flowchart which shows the flow of a process of a disk control part. The flowchart which shows the flow of the process which a disk control part requires. 6 is a flowchart showing a flow of processing in which the disk control unit writes data on the cache memory to the disk. The flowchart which shows the flow of the restoration process which writes the data of cache memory in a disk at the time of restart. FIG. 6 is a functional block diagram including a configuration example of a disk controller according to a second embodiment. FIG. 9 is a functional block diagram including a configuration example of a disk controller according to a third embodiment. 15 is a flowchart showing a flow of cache management processing at the time of a write request processing by a disk controller according to a third embodiment. FIG. 10 is a functional block diagram including a configuration example of a disk controller according to a fourth embodiment. The figure which shows the state in which the cache memory acquires write data from the host computer and temporarily holds it before writing it to the disk. The figure which shows the state of the cache memory in the middle of the transfer of the new write data from a host computer. The figure which shows the state of the data written in a disk after a power failure when a power failure occurs in the middle of transfer of the write data from a host computer.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Disk controller, 11 ... DMA controller, 12 ... Cache memory, 13 ... Disk control part, 14 ... Cache management table, 15 ... Disk, 16 ... Disk apparatus, 17 ... Host computer, 18 ... Memory, 19 ... Driver, 30 ... Command buffer, 31 ... Transfer controller, 32 ... First transfer engine, 33 ... Second transfer engine, 34 ... Data buffer, 35 ... Send pointer, 36 ... Receive pointer, 150 ... Disk controller, 151, 152 ... SCSI controller, 160 ... disk controller, 161 ... data transfer unit, 180 ... disk controller, 181 ... encryption device, 190 ... disk device, 191 ... cache memory, 192 ... disk, 200 ... host computer

Claims (6)

A disk controller that controls the writing of data from the host computer to the disk.
A non-volatile cache memory for storing data from the host computer to be written to the disk;
A non-volatile storage area for storing a predetermined amount of data from the host computer;
A predetermined amount of data is acquired from the host computer, the acquired predetermined amount of data is written to the nonvolatile storage area, and then the predetermined amount of data written to the nonvolatile storage area is stored in the nonvolatile cache memory. A data transfer means for acquiring a predetermined amount of next data from the host computer after the transfer and writing the acquired data in the nonvolatile storage area;
The data transfer means is a disk configured to transfer a predetermined amount of data written in the non-volatile storage area to the non-volatile cache memory again upon power recovery when the data transfer is interrupted due to a power failure. controller.   The disk controller according to claim 1, wherein the nonvolatile storage area is provided in the nonvolatile cache memory or the data transfer unit. A disk controller that controls the writing of data from the host computer to the disk.
A non-volatile cache memory having two storage areas capable of storing data from the host computer as cache data written to the disk;
Data transfer means for acquiring data from the host computer and transferring the acquired data to the nonvolatile cache memory;
When the data is transferred from the data transfer means, the non-volatile cache memory stores the cache data in one of the two storage areas as the cache data, and stores the data in the two storage areas. When data is transferred from the data transfer means in a state where cache data is stored in any one of the storage areas, the transferred data is stored in the other storage area of the two storage areas. A disk controller that stores data in an area and, after the transfer is completed, uses the data stored in the other storage area as new cache data and stores the data in the one storage area. A disk device comprising a disk and writing data from a host computer to the disk,
A non-volatile cache memory for storing data from the host computer to be written to the disk;
A non-volatile storage area for storing a predetermined amount of data from the host computer;
A predetermined amount of data is acquired from the host computer, the acquired predetermined amount of data is written to the nonvolatile storage area, and then the predetermined amount of data written to the nonvolatile storage area is stored in the nonvolatile cache memory. A data transfer means for acquiring a predetermined amount of next data from the host computer after the transfer and writing the acquired data in the nonvolatile storage area;
The data transfer means is a disk configured to transfer a predetermined amount of data written in the non-volatile storage area to the non-volatile cache memory again upon power recovery when the data transfer is interrupted due to a power failure. apparatus.   The disk device according to claim 4, wherein the nonvolatile storage area is provided in the nonvolatile cache memory or the data transfer unit. A disk device comprising a disk and writing data from a host computer to the disk,
A non-volatile cache memory having two storage areas capable of storing data from the host computer as cache data written to the disk;
Data transfer means for acquiring data from the host computer and transferring the acquired data to the nonvolatile cache memory;
When the data is transferred from the data transfer means, the non-volatile cache memory stores the cache data in one of the two storage areas as the cache data, and stores the data in the two storage areas. When data is transferred from the data transfer means in a state where cache data is stored in any one of the storage areas, the transferred data is stored in the other storage area of the two storage areas. A disk device that stores data in an area, makes the data stored in the other storage area new cache data at the completion of the transfer, and stores the data in the one storage area.

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