JP2008010912A - Motion picture decoding apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a motion picture decoding apparatus capable of smooth reproduction and cost reduction by eliminating the necessity of a PLL function, even if transfer jitters are included in a reception signal connected to a network. <P>SOLUTION: The motion picture decoding apparatus is provided with a network IF section 10 for receiving a digital stream data compressed in conformity with MPEG standards via a network; a stream buffer 11 for storing digital data from the network IF section 10; a decoder section 12 for decoding the digital data from the stream buffer; a stream buffer output control section for controlling an output timing of the stream buffer from the display timing maximum delay quantity from the decoder section; and a video display section 14 for displaying video images from the decoder section. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an MPEG data receiver, and more particularly to a receiver that receives MPEG data via a network.

  As a conventional video decoding device, in order to lock synchronization between the encoder side and the decoding side, the clock is corrected by the clock information included in the received stream and the buffer data amount in the decoder, and the decoder is synchronized with the encoder. There is something. (For example, see Patent Document 1).

  FIG. 4 shows a conventional video decoding device described in Patent Document 1.

  FIG. 5 shows a schematic configuration of a PLL of a conventional moving picture decoding apparatus described in Patent Document 1.

  As a conventional video decoding device, a receiver used for digital satellite broadcasting will be described with reference to FIG.

  FIG. 4 shows a receiver used for digital satellite broadcasting. The receiver is roughly divided into a tuner module 40, a descrambler 41, an MPEG transport decoder 42, an MPEG2 video decoder 43, an MPEG1 audio decoder 45, an NTSC. It comprises an encoder 44, a D / A converter 46, and a control CPU 47.

  Here, the MPEG transport port decoder 42 is also called a system decoder or a transport demultiplexer (DMUX). The signal processing in the receiver will be described. First, the satellite wave received by the satellite broadcast receiving antenna is input to the tuner module 40.

  The tuner module 40 performs switching of the reception transponder, demodulation, decoding of error correction, and the like, and extracts an MPEG2 transport stream in which individual data strings (streams) are multiplexed. This transport stream (hereinafter referred to as TS) is input to the descrambler 41 and descrambled (descrambled) using key data for descrambling supplied from an IC card (not shown). And transferred to the MPEG transport decoder 42.

  The MPEG transport decoder 42 receives program specification information (hereinafter referred to as PSI) based on the viewer's channel selection operation, extracts necessary video data and audio data from the TS, and MPEG2 video decoder 43 And to the MPEG1 audio decoder 45.

  The MPEG2 video decoder 43 releases the compression of the video data, converts it into an NTSC signal by the NTSC encoder 44, and outputs it to the television receiver.

The MPEG1 audio decoder 45 releases the compression of the audio data, converts it to an analog signal by the D / A converter 46, and outputs it to the television receiver. The control CPU 47 controls these series of processes. The MPEG transport decoder 42 includes an MPEG transport decoder 42, an MPEG2 video decoder 43, an MPEG1 audio decoder e,
It also has a function of performing reproduction processing of a clock signal used in the NTSC encoder 44.

  The clock signal reproduction processing includes an MPEG encoder (encoding device) that encodes and compresses broadcast waves such as satellite waves on the broadcaster side, and an MPEG that releases compression of video data and audio data on the viewer side. This is common time management, that is, synchronization processing with the decoder (decoding device). Next, the clock signal reproduction process will be described with reference to FIG.

FIG. 5 is a block diagram showing a schematic configuration of a phase locked loop (hereinafter referred to as PLL) used for clock signal reproduction processing. As shown in FIG. 5, the PLL includes a subtraction unit (phase comparison unit) 50, a clock adjustment unit 51, a digital / analog conversion unit (hereinafter referred to as D / A conversion unit) 52, a low-pass filter (hereinafter referred to as LPF). ) 53, a voltage control oscillation unit (hereinafter referred to as VCO) 54, and a feedback closed circuit including a counter unit 55. The subtraction unit 50 compares the counter value from the program clock reference (hereinafter referred to as PCR) information extracted from the specific stream with the counter value from the counter unit, and the clock adjustment unit 51 Based on the comparison result and the amount of data in the buffer memory, the difference is converted into a voltage signal via the D / A converter 52 and the low-pass filter 53 and applied to the VCO 54. The phase of the clock signal CLK is corrected by this voltage signal and output, and the counter unit is written.
JP 11-112982 A

  However, in the conventional configuration, it is necessary to transmit and receive clock information between the encoder side and the decoder side, and to lock the decoder to the encoder using a PLL, which has a problem that the apparatus becomes complicated. On the other hand, when the received signal is connected through a network, there are cases where the transfer timing varies greatly due to the influence of the traffic of the network, but this is not particularly considered in the conventional configuration.

  The present invention solves the above-described conventional problems, and enables smooth reproduction even when transfer jitter is present in a reception signal connected to the network, and enables cost reduction by eliminating the PLL function. An object of the present invention is to provide a moving picture decoding apparatus.

  In order to solve the above-described conventional problems, a moving picture decoding apparatus according to the present invention stores a digital data stream compressed by the MPEG standard via a network and a digital data from the network IF part. A stream buffer; a decoder unit for decoding digital data from the stream buffer; a stream buffer output control unit for controlling the output timing of the stream buffer from a display timing maximum delay amount from the decoder unit; And a video display unit for displaying the video.

  This configuration records the maximum value of the deviation between the time information contained in the storm and the time information managed by the decoder unit, and controls the output timing with the same deviation for the subsequent streams. To do.

  According to the moving picture decoding apparatus of the present invention, video can be displayed smoothly even when there is transfer jitter in the network unit. In addition, since the PLL function is unnecessary, the cost can be reduced.

Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.
(First embodiment)

  FIG. 1 is a block diagram of a moving image receiving apparatus according to the first embodiment of the present invention. FIG. 2 is a processing timing diagram before improvement in the first embodiment of the present invention. FIG. 3 is a process timing chart after the improvement in the first embodiment of the present invention. In FIG. 3, the same components as those in FIG.

  In FIG. 1, the moving image receiving apparatus includes a network IF 10, a stream buffer 11, a decoding unit 12, a stream buffer output control unit 13, and a video display unit 14.

  According to such a configuration, the decoding unit 12 records the time information included in the stream and the maximum value of the time difference counted inside the decoder unit 12, and the stream buffer output timing control unit 13 sets the maximum value of the time difference. By controlling the output timing from the stream buffer so as to maintain the above, smooth video display becomes possible.

  In FIG. 2, F1 to F17 represent data streams of odd frames. T1 to T17 represent the display timing of the decoder.

  The input timing a to the buffer is the data timing between the network IF and the stream buffer, and shows that the timing between the frames is different due to the influence of the network unit. At this time, the maximum delay is between F3 and F5, which is delayed by 3 frames compared to the display timing of the decoder.

  The input timing b to the buffer is the data timing between the stream buffer 11 and the decoding unit, and the input timing c to the buffer is the data timing between the decoding unit and the video display unit.

  As shown in FIG. 2, the video is displayed with the transfer jitter from the network IF, so that the video looks strange. FIG. 3 controls the output timing from the stream buffer while maintaining 3 frames, which is the maximum delay from the timing of F7 to the display timing of the decoder, at the input timing b to the buffer. For this reason, the timing between the frames becomes uniform at the video display timing at the input timing c to the buffer, and smooth display is possible.

  The moving picture decoding apparatus according to the present invention is useful as a receiving apparatus or the like for receiving MPEG data via a network because smooth video display is possible even when there is network transfer jitter.

Block diagram of moving picture receiving apparatus in Embodiment 1 of the present invention Processing timing chart before improvement in Embodiment 1 of the present invention Process timing chart after improvement in Embodiment 1 of the present invention Block diagram of a conventional video receiver A schematic block diagram of a PLL of a conventional video decoding device

Explanation of symbols

10 Network IF
DESCRIPTION OF SYMBOLS 11 Stream buffer part 12 Decoding part 13 Stream buffer output control part 14 Video display part 40 Tuner module 41 Descrambler 42 MPEG transport decoder 43 MPEG2 video decoder 43
44 NTSC encoder 45 MPEG1 audio decoder 46 D / A converter 47 CPU for control
50 Subtraction unit 51 Clock adjustment unit 52 Digital-analog conversion unit 53 Low-pass filter 54 Voltage control transmission unit 55 Counter unit

Claims (1)

A network IF unit that receives a digital data stream compressed in accordance with the MPEG standard via a network, a stream buffer that stores digital data from the network IF unit, a decoder unit that decodes digital data from the stream buffer, and the decoder unit In a video decoding device comprising: a stream buffer output control unit that controls the output timing of the stream buffer from a display timing maximum delay amount; and a video display unit that displays video from the coder unit,
A moving picture decoding apparatus characterized by correcting a difference between time information included in a stream and time information managed by the decoder unit and smoothly displaying a video.

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