JP2008009520A - Data transfer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide data transfer whose transmission delay is small between blades in an ATCA device. <P>SOLUTION: In this data transfer circuit 10 installed in each blade in the ATCA device, a clock signal CLK for synchronous data transfer is generated by a PLL part 12 on the basis of clock signals CLK1 or a CLK2 applied from common clock wiring 6a and 6b. Meanwhile, clock wiring 6c for a clock signal CLK3 which is not yet defined by the ATCA device is used as a data line for performing synchronous data transfer by time-division between blades. A communication frame FRM is configured of synchronous codes, control codes, and 16 pieces of time slots, and at most 16 pieces of blades are fixedly assigned to 16 pieces of time slots. The transmission blade designates a destination blade by the time slot of the first communication frame in starting transmission, and successively outputs data by each byte by using the following communication frames. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention provides, for example, a clock bus wiring for a common clock in an apparatus conforming to PICMG 3.0 Revision 2.0 AdvancedTCA Base Specification (Peripheral Component Interconnect Industrial Computer Manufacturers 3.0 Advanced Telecommunications Computing Architecture Group standard, hereinafter simply referred to as “ATCA standard”). The present invention relates to a data transfer circuit for transferring data between a plurality of electronic circuit boards using the above-mentioned.

FIG. 2 is a conceptual diagram of a conventional ATCA device conforming to the ATCA standard.
The ATCA standard is a standard mainly defining a platform for communication equipment, and an ATCA device is used as a telecommunication equipment.

  As shown in FIG. 2 (a), the ATCA apparatus includes up to 16 electronic circuit boards called blades 1a, 1b,..., 1n and one control circuit board called a shelf manager 2 in a chassis (casing). ) And mounted on a wiring board called a back plane 3 provided in the inside. The main wiring on the backplane 3 includes power wiring, management bus wiring 4 according to the IPM (Intelligent Platform Management) interface standard for the shelf manager 2 to manage the operation state of each blade 1a to 1n, blade A LAN (Local Area Network) wiring 5 for inter-communication, and a clock wiring 6 for distributing a common clock signal to all broad.

  Data transfer between the blades is performed using the LAN wiring 5 or the management bus wiring 4. Of these, the LAN wiring 5 is wired in a star shape to each blade and the shelf manager 2 around the switch blade (for example, blade 1b) constituting the hub (HUB), and data between blades other than the switch blade. The transfer is always performed via this switch blade.

  On the other hand, the management bus wiring 4 is composed of one data line and one clock line, and the shelf manager 2 and the IPM controllers (IPMC) of the blades 1a to 1n are parallel to the management bus wiring 4. It is connected to the. The main function of the IPM controller of the shelf manager 2 is to monitor the hardware status in the shelf manager, collect information from each blade 1a to 1n connected to the IPM bus, and download firmware to each blade 1a to 1n. Etc. The main functions of the IPM controllers of the blades 1a to 1n are monitoring the hardware state in the blades, transferring event messages to the shelf manager 2 at the time of abnormality, and the like.

PICMG “PICMG 3.0 Revision 2.0 AdvancedTCA Base Specification”, 2005.3.18

However, the ATCA apparatus has the following problems.
When data is transferred between arbitrary blades using the LAN wiring 5, wiring via the switch blade must be used. For this reason, the LAN protocol is used to perform two-link LAN communication in which data is transferred from the transmitting blade to the switch blade, and further transferred from the switch blade to the receiving blade. Become. Since the LAN protocol is generally realized by software processing, transmission delay increases.

  When data is transferred between arbitrary blades using the management bus wiring 4, the management bus 4 is shared by the data between the blades and the management data. For this reason, traffic increases and transmission delay increases.

  An object of the present invention is to perform data transfer with a small transmission delay between blades in an ATCA apparatus.

  The present invention is provided in each electronic circuit board in a telecommunication device configured by mounting a control circuit board and a plurality of electronic circuit boards on a wiring board, and data for transferring data between these electronic circuit boards The transfer circuit is configured as follows.

  That is, the data transfer circuit includes a clock receiving unit that receives a common clock signal supplied from one of a plurality of clock lines provided on the wiring board and converts the common clock signal to a predetermined electrical level; A clock generation unit for generating a transfer clock signal for data transfer at a predetermined frequency synchronized with the common clock signal based on the common clock signal converted into an electrical level; and the common clock signal among the plurality of common clock lines A frame receiving unit that converts a clock line signal that is not used for transmission to a predetermined electrical level, and frame synchronization is detected from the clock line signal converted by the frame receiving unit, and the common clock signal is transmitted. The data from the plurality of electronic circuit boards is time-divided based on the transfer clock signal using a clock line that is not used for And a frame synchronization unit for generating a timing signal for transmission and reception to transmission.

  Further, the data transfer circuit extracts data from the clock line signal converted by the frame receiving unit according to the reception timing signal, and analyzes the data extracted by the data extracting unit. A data analysis unit that receives data addressed to the electronic circuit board, a data generation unit that generates data to be transmitted to another electronic circuit board, and a timing for transmitting the data generated by the data generation unit A data output unit configured to output a signal according to a signal; and a data transmission unit configured to convert the data output from the data output unit into a predetermined electrical level and transmit the data to a clock line not used for transmitting the common clock signal. .

  The data transfer circuit according to the present invention time-divides data from the plurality of electronic circuit boards using a clock line that is not used for transmission of a common clock signal among the plurality of clock lines provided on the wiring board. A clock reception unit, a clock generation unit, a frame reception unit, a frame synchronization unit, a data extraction unit, a data analysis unit, a data generation unit, a data output unit, and a data transmission unit. Thereby, there is an effect that data transfer with a small transmission delay can be performed between the electronic circuit boards of the telecommunication equipment.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a configuration diagram of a data transfer circuit showing an embodiment of the present invention.
The data transfer circuit 10 is provided in each blade of the ATCA apparatus, and performs data transfer by time division between the blades using the three clock wirings 6a, 6b, 6c on the backplane. Of the three clock wirings 6a to 6c, the first clock wiring 6a and the second clock line 6b receive the clock signal CLK1 of 8 kHz and the clock signal CLK2 of 19.44 MHz from the specific blade, respectively. The ATCA standard defines that it is used for supplying. On the other hand, the third clock wiring 6c can be freely defined and used by each ATCA device. In the present invention, the data between the blades is transferred by transferring the communication frame FRM through the clock wiring 6c. I am trying to transfer.

  The data transfer circuit 10 has a clock receiving unit 11 connected to clock wirings 6a and 6b. The clock receiving unit 11 receives either the 8 kHz clock signal CLK1 supplied from the clock wiring 6a or the 19.44 MHz clock signal CLK2 supplied from the clock wiring 6b, performs electrical level conversion, and performs a PLL (phase (Synchronous circuit) section 12.

  The PLL unit 12 generates a clock signal CLK for inter-blade data transfer based on the clock signal supplied from the clock receiving unit 11. When the clock signal CLK1 of 8 kHz is supplied from the clock receiver 11, the PLL unit 12 divides the output signal of the built-in VCXO (voltage controlled crystal oscillator) and generates the 8 kHz phase of the received clock signal CLK1. By matching the phase, a clock signal CLK of, for example, 64 kHz synchronized with the lock signal CLK1 is generated. Further, when a 19.44 MHz clock signal CLK2 is given from the clock receiving unit 11, the PLL unit 12 divides the clock signal CLK2, and divides the output signal of the built-in VCXO to generate the phase of the signal generated. By matching with the phase of the clock signal CLK2, for example, a 19.44 MHz clock signal CLK is generated.

  Further, the data transfer circuit 10 includes a frame receiving unit 13 connected to the clock wiring 6c. The frame receiving unit 13 receives a communication frame FRM transmitted and received in a time division manner between the blades using the clock wiring 6c, performs electrical level conversion, and provides the received frame signal RF to the frame synchronization unit 14. is there. The frame configuration of the communication frame FRM will be described later.

  The frame synchronization unit 14 uses the clock signal CLK provided from the PLL unit 12 to detect a synchronization code in the reception frame signal RF provided from the frame reception unit 13 and to perform frame synchronization. As a synchronization method, for example, it is determined that frame synchronization has been established when the synchronization code is detected three times in succession, and it is determined that frame synchronization has been lost when the synchronization code cannot be detected three times in succession. A general method such as three steps or three steps in the rear is used. The frame synchronization unit 14 generates a reception timing signal RT indicating the timing of data sent from each blade and a transmission timing signal ST indicating the timing at which the blade transmits data based on the detected synchronization code. It is supposed to be. The reception frame RF and the reception timing signal RT are given to the data extraction unit 15.

  The data extraction unit 15 extracts data sent from each blade in accordance with the reception frame RF and the reception timing signal RT given from the frame synchronization unit 14 and outputs the data to the data analysis unit 16 as reception data RD. Note that the data extraction unit 15 can select only necessary information according to the selection signal SEL provided from the data analysis unit 16 and output the reception data RD. The data analysis unit 16 analyzes the reception data RD extracted by the data extraction unit 15 and extracts information addressed to the own blade. It is also possible to give a selection signal SEL to the data analysis unit 16 in order to select only necessary information.

  On the other hand, the data transfer circuit 10 includes a data generation unit 17 for generating transmission data SD to be transmitted to other blades. Further, in the blade set to output the clock signal CLK1 and the clock signal CLK2, the data generation unit 17 generates a synchronization code and a control code that are components of the communication frame FRM. The transmission data SD, the synchronization code, and the control code generated by the data generation unit 17 are given to the data output unit 18.

  The data output unit 18 outputs the transmission data SD and the like given from the data generation unit 17 to the data transmission unit 19 as a transmission signal TD in accordance with the transmission timing signal ST given from the frame synchronization unit 14. The data transmission unit 19 converts the transmission signal TD given from the data output unit 18 into a predetermined electrical level, and outputs it from the open drain type output circuit to the clock wiring 6c.

  FIG. 3 is an explanatory diagram showing the configuration of the communication frame FRM in FIG. The operation of FIG. 1 will be described below with reference to FIG.

  The clock signals CLK1 and CLK2 sent via the clock wirings 6a and 6b are received by the clock receiving unit 11 and one of them is selected and given to the PLL unit 12. In the PLL unit 12, a clock signal CLK having a predetermined frequency (for example, 64 kHz) synchronized with the clock signal supplied from the clock receiving unit 11 is generated and output to the frame synchronization unit 14.

  On the other hand, on the clock wiring 6c, a signal constituting the communication frame FRM is output at a constant period by a transmission signal TD output in a time division manner from each blade. As shown in FIG. 3 (a), the communication frame FRM is composed of a synchronization code, a control code, and 16 time slots TS0 to TS15. These synchronization code, control code, and 16 time slots TS0 to TS15. Each TS15 has a size of 1 byte. Therefore, the communication frame FRM has a configuration of 18 bytes per frame, and is continuously output repeatedly on the clock wiring 6c.

  The synchronization code and control code of the communication frame FRM are transmitted from the data transfer circuit of the blade that outputs the clock signals CLK1 and CLK2 on the clock wirings 6a and 6b. Further, the 16 time slots TS0 to TS15 are fixedly assigned as time slots for data transmission to up to 16 blades constituting the ATCA apparatus.

  The communication frame FRM on the clock wiring 6c is received by the frame reception unit 13, subjected to electrical level conversion, and given to the frame synchronization unit 14 as a reception frame signal RF. The frame synchronization unit 14 detects a synchronization code in the received frame signal RF in accordance with the clock signal CLK supplied from the PLL unit 12, and establishes frame synchronization by a general method such as front three steps or rear three steps.

  The frame synchronization unit 14 generates a reception timing signal RT and a transmission timing signal ST based on the established frame synchronization, supplies them to the data extraction unit 15 and the data output unit 18, respectively, and sends the reception frame RF to the data extraction unit 15. Output.

  The data extraction unit 15 extracts the control code and the data of the 16 time slots TS0 to TS15 according to the reception frame RF and the reception timing signal RT given from the frame synchronization unit 14, and outputs them to the data analysis unit 16 as reception data RD. To do. Note that when data to be extracted is designated by the selection signal SEL, the data extraction unit 15 extracts only the designated data.

  The data analysis unit 16 analyzes the control code given from the data extraction unit 15 and analyzes the information of each time slot TS0 to TS15 to check whether there is data addressed to the own blade.

  The information of each time slot TS0 to TS15 includes two types of TS control information shown in FIG. 3B and TS data shown in FIG.

  The TS control information is output when each blade does not have data to be transmitted and when data to be transmitted is generated. As shown in FIG. This flag VAL indicates whether or not there is valid data after the frame. When this flag VAL is set to “1”, the address of the blade that is the destination of the data is stored in bits b3 to b0. ADR is set. Bits b7 to b5 are undefined (“0”).

  TS data is transmitted using a pre-assigned time slot in the communication frame RFM after the data transmission blade sets the flag VAL to “1” by the TS control information and declares data transmission. The data for the addresses ADR are sequentially transmitted. As shown in FIG. 3C, in the TS data of the first communication frame FRM after the flag VAL is set to “1”, a 1-byte fixed value indicating that data transfer is started is transmitted. The In the second and third communication frames FRM, the data length (2 bytes) of the transmission data is divided into upper digits and lower digits and transmitted. Thereafter, transmission data is sequentially transmitted byte by byte, and finally a CRC (error detection) code is transmitted, and data transmission to the corresponding address ADR is completed.

  When the data analysis unit 16 detects the presence of reception data addressed to its own blade, the data analysis unit 16 receives data that is sequentially transmitted byte by byte for each communication frame FRM in the above procedure.

  On the other hand, when transmission data for responding to data received from other blades or data to be transmitted spontaneously to other blades is generated, the data generation unit 17 generates transmission data SD to generate data. This is given to the output unit 18. The data output unit 18 transmits the transmission data SD given from the data generation unit 17 to the data transmission unit 19 as a transmission signal TD according to the transmission timing signal ST of the time slot assigned to the blade given from the frame synchronization unit 14. Output.

  In this case, in order to send data to the destination blade, the time slot assigned to the own blade is used, the flag VAL is set to “1” in the first communication frame FRM, and the destination blade is set to the address ADR. As described above, the fixed value, the data length, and the transmission data indicating that data transfer is started in the subsequent communication frame FRM are sequentially output byte by byte, and finally the CRC code is output.

  The transmission signal TD output from the data output unit 18 is supplied to the data transmission unit 19, converted to a predetermined electrical level by the data transmission unit 19, and output from the open drain type output circuit to the clock wiring 6c. .

  The open drain type output circuit of the data transmission unit 19 connects the clock wiring 6c to the ground potential when outputting the level “L”, and enters a high impedance state when outputting the level “H”. It is configured. Accordingly, the clock wiring 6c is pulled up to “H” with a high resistance or the like, and the transmission data is output at the timing of the time slot assigned to the own blade. Otherwise, the output of the data transmission unit 19 is set to “H”. By setting to, it is possible to perform time-sharing data transfer between a plurality of blades.

  As described above, in the data transfer circuit according to the present embodiment, communication between arbitrary blades can be performed using the time-division-type communication frame FRM by using the clock wiring 6c for the unused clock signal CLK3. . Therefore, by using not only the management bus wiring 4 and the LAN wiring 5 but also the undefined clock wiring 6c, the data transfer capacity in the ATCA device is increased, and data transfer with a small transmission delay is performed between the blades. There is an advantage that can be.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) The frequency of the clock signal CLK generated by the PLL unit 12 is not limited to 64 kHz or 19.44 MHz.
(B) The formats shown in FIGS. 3B and 3C are examples, and the information transmitted and received in each time slot TS0 to TS15 is not limited to this format.

It is a block diagram of the data transfer circuit which shows the Example of this invention. It is a conceptual diagram of the conventional ATCA apparatus. It is explanatory drawing which shows the structure of the communication frame FRM in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Blade 2 Shelf manager 3 Backplane 4 Management bus wiring 5 LAN wiring 6 Clock wiring 10 Data transfer circuit 11 Clock receiving part 12 PLL part 13 Frame receiving part 14 Frame synchronizing part 15 Data extracting part 16 Data analyzing part 17 Data generating part 18 Data output unit 19 Data transmission unit

Claims (1)

A data transfer circuit provided in each electronic circuit board in a telecommunication device configured by mounting a control circuit board and a plurality of electronic circuit boards on a wiring board, and for transferring data between these electronic circuit boards. And
A clock receiver for receiving a common clock signal supplied by one of a plurality of clock lines provided on the wiring board and converting it to a predetermined electrical level;
A clock generator for generating a transfer clock signal for data transfer at a predetermined frequency synchronized with the common clock signal based on the common clock signal converted to the predetermined electrical level;
A frame receiving unit that converts a signal of a clock line that is not used for transmission of the common clock signal among the plurality of common clock lines to a predetermined electrical level;
The plurality of electronic circuit boards based on the transfer clock signal using a clock line that is not used for transmission of the common clock signal, detecting frame synchronization from the signal of the clock line converted by the frame receiver A frame synchronization unit for generating timing signals for reception and transmission for transferring data from the time-division,
A data extraction unit for extracting data from the clock line signal converted by the frame reception unit according to the timing signal for reception;
A data analysis unit for analyzing the data extracted by the data extraction unit and receiving data addressed to the electronic circuit board;
A data generator for generating data for transmission to other electronic circuit boards;
A data output unit that outputs the data generated by the data generation unit according to the timing signal for transmission;
A data transmission unit that converts data output from the data output unit to a predetermined electrical level and transmits the data to a clock line that is not used for transmission of the common clock signal;
A data transfer circuit comprising:

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