JP2007529815A - Signal transmission apparatus and method for signal transmission - Google Patents

Abstract

  A communication device is implemented for tag field type communication signal transmission. In accordance with an embodiment of the present invention, a communication device, such as a PCI Express type device, is configured to communicate over a communication link using a tag (or similar) available field. In accordance with embodiments of the present invention including PCI Express communication, the first PCI Express endpoint device (150) has posted selected information (eg, a synchronization event signal) to the PCI Express communication link (130). The tag field of data is used to communicate to the second PCI Express endpoint device (152). The tag field is set to indicate the characteristics of the synchronization event and is transmitted from the first PCI Express endpoint device to the second PCI Express endpoint device.

Description

  The present invention relates generally to the transmission of information, and more particularly to the transmission of information including the use of tag (or similar) fields to communicate information.

  Many different types of electronic communication are performed using different types of devices and systems for different purposes. One type of electronic communication system includes electronic communication related to bus-type communication between two or more different components. For example, a computer typically includes a central processing unit (CPU) that communicates with peripheral devices via a bus. Instructions and other information are transmitted between the CPU and peripheral devices over a communication bus or other link.

  One type of communication technique involves the use of a Peripheral Component Interconnect (PCI) system. PCI is an interconnection system between a microprocessor and connected devices in which expansion slots are densely arranged for high speed operation. By using PCI, a computer can support a new PCI card, while continuing to support an older standard ISA (Industry Standard Architecture) expansion card. PCI is designed to be independent of the design of the microprocessor and is designed to be synchronized with the clock speed of the microprocessor. PCI uses an active path (on a multi-drop bus) to transmit both address and data signals, and addresses in one clock cycle and in the next cycle Send data. PCI buses are adapters that require fast access to each other and / or to system memory and that can be accessed by the host processors at a speed close to the host processor's native full bus speed. Can be arranged using. Read and write transmissions over the PCI bus are implemented in burst transmissions, starting with an address in the first cycle and sending a sequence of data transmissions in a certain number of subsequent cycles. The length of the burst is negotiated between the initiating side and the target device, and may be of any length. PCI type architectures are widely implemented and are installed on most desktop computers today.

  The PCI Express architecture shows similarities to the PCI architecture with certain changes. The PCI Express architecture utilizes a switch that replaces the PCI architecture multi-drop bus with a switch that provides fan-out for an input / output (I / O) bus. The fan-out function of the switch facilitates a series of connections for additional high performance I / O. The switch is a logic element that can be implemented in a component that also includes a host bridge. A PCI switch is logically a PCI-, for example, an upstream bridge in which one bridge is connected to a private local bus to the upstream side through the downstream side of a group of additional PCI-PCI bridges. It can be considered as a PCI bridge.

  In some examples, information such as information indicating a synchronization event is desirably signaled to a device, such as a PCI Express endpoint device, communicatively coupled to each other. In general, the signaling involves the use of interrupts that require multiple packets, vendor specific message processing or other processing that tends to slow down the processing of the communication. These interrupts typically involve periodic communication interruptions on the bus, thus interfering with streaming data such as write data. These interruptions tend to increase the communication overhead of synchronization events (eg, by increasing latency and slowing communication bandwidth).

  These and other limitations pose challenges for the implementation of combined devices that use various communication techniques, including PCI Express communication techniques.

  Various aspects of the invention include communication techniques for various computer circuits, such as circuits including communication bus type structures (eg, PCI type structures) and others. The present invention is illustrated in several implementations and applications, some of which are summarized below.

  According to an embodiment of the present invention, information is included in a tag field of data posted to a communication link, such as posted request data. The posted data is communicated between devices coupled to the link and can be utilized, for example, to signal a synchronization event. By using this approach, it is fully compliant with any field usage related requirements, such as those implemented using the PCI Express requirements, while being more relevant to signaling interrupts and other types of synchronization events. Restrictions, including those discussed, are reduced and / or eliminated.

  According to another embodiment of the invention, a synchronization event is signaled to the PCI Express device by setting the posted write request tag field to a "true" value. For example, in order to transmit data regarding the synchronization event from a PCI Express endpoint device to another PCI Express endpoint device using a common PCI Express link to which these devices are communicably connected, PCI Express communication is performed. The tag field can be used according to a technique. When implemented with posted write request data that does not require a response (eg, completion), the tag is subject to a PCI Express requirement that allows the tag field for such requests to contain any value. Fields can be implemented. The information in the tag field can be transferred through hubs and switches and is therefore compliant with PCI Express protocol requirements and checkers.

  The above summary of the present invention is not intended to describe each embodiment or every implementation of the present invention. The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The following figures and detailed description illustrate these embodiments in more detail.

  The present invention may be more fully understood in view of the following detailed description of various embodiments of the invention in conjunction with the accompanying drawings.

  While the invention is applicable to various modifications and alternative forms, details of the invention are shown by way of example in the drawings and are described in detail below. It should be understood, however, that the intention is not to limit the invention to the embodiments described. On the contrary, the invention is intended to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

  The present invention is applicable to various circuits and techniques including electronic communication, and is particularly applicable to those including communication between endpoint type devices coupled to a common link. While the invention is not necessarily limited to such applications, an understanding of the various aspects of the invention is best obtained by discussing examples in such an environment.

  In accordance with an embodiment of the present invention, a communication device includes a communication link with at least two endpoint-type devices, wherein the endpoint-type device (e.g., via a posted write data tag field). The link is configured to transmit information using a tag (or similar) field of communication. The communication link may include, for example, a PCI Express bus, a switch, and / or other components. By using this technique, tag field communication can be performed while facilitating transmission of selected communication involving other communication (ie, communication that does not necessarily require or prohibit use of the tag field). .

  In one embodiment, the approach discussed above is implemented using a PCI Express configuration. The tag field is identified by the requester function and returned by the completer function. Further, in some embodiments, the requester function includes posted writes that do not require completion. The requester function is implemented by a requestor (request or a logical unit that introduces a logical conversion to a PCI Express domain) that implements a packet, and the completer function is a Completion or Implemented by a completer (logic unit addressed by the Requester) that generates packets and terminates or partially terminates the sequence. For certain PCI Express applications where the completer does not respond to the data in the tag field (ie, the completer function does not process the tag field), the requester function may be in any manner, such as for a signal synchronization event. Is used.

  For more information on the above functions (and others) implemented in connection with “PCI Express compliant” applications, see “PCI Express Base Specification Revision 1.0a” (April 2003, PCI-SIG (PCI-special See interest group), Portland, Oregon). A technique based on the “PCI Express Base Specification” is considered as “PCI Express compatible”.

  Referring now to the drawings, FIG. 1 illustrates a PCI Express communication system 100 implemented to transmit a synchronization event using a tag field of a posted write packet according to another embodiment of the present invention. Although shown and discussed using a PCI Express type approach, the communication system 100 may be implemented using PCI Express or using other communication types and protocols that are different from PCI Express.

  Communication system 100 includes a PCI Express switch 110 configured to transmit communications between a host 105 and a plurality of endpoint devices including endpoint devices 150 and 152. A host 105 (eg, CPU, network-based chipset, host bridge or other PCI Express type link) transmits data to and receives data from upstream port 120. Upstream port 120 is coupled to a virtual (eg, implemented in software) PCI Express bus 130. A plurality of downstream ports including downstream ports 140, 142, 144, and 146 are also coupled to virtual PCI Express bus 130. Each downstream port is configured to send data to the PCI Express endpoint device and receive data from the PCI Express endpoint device.

  Each of the endpoint devices 150 and 152 is configured to communicate synchronization event information using the tag field of posted write packets transmitted over the virtual bus 130. For example, when the endpoint device 150 communicates information in the form of a packet via the virtual bus 130, a tag field in a part of the packet may be set using data related to a synchronization event. Endpoint device 152 then parses the packet and uses the information in the tag field to confirm the synchronization event information.

  In one embodiment, the endpoint device 150 operates as a requester when posting write data, and write requests are posted to the virtual PCI Express bus 130 in the form of packets. The write request includes a “tag in” signal (eg, one or more bits) in the header of the write request to alert the receiver of the write request about the synchronization event status. The tag-in data is set when the synchronization event is “true” and is removed (or not set) when the synchronization event is not true.

  An endpoint device (eg, endpoint device 152) that parses the posted write request uses the tag-in data to identify the synchronization event and responds to the synchronization event signal from the endpoint device 150 with appropriate action. To do. The endpoint device now operates as a completer device that does not respond to endpoint device 150 (i.e., using a request that includes signaling a tag field that does not require completion).

  In some embodiments, the intended recipient of posted write data is not necessarily the intended recipient of a synchronization event signal. In this regard, another endpoint device coupled to the completer device 152 and / or one of the downstream ports 140-146 processes the synchronization event data, and another endpoint device other than the posted write data. Process the part.

  In other implementations, adapters are utilized to generate packets for transmission on the virtual PCI Express bus 130 in response to requests by each endpoint device. Each adapter may be implemented, for example, in connection with a PCI Express endpoint device that generates posted writes, or may be implemented in a PCI Express switch 110. Each adapter has an input and a corresponding output (eg, a single bit or a bit extended to about 8 bits wide) that is used to provide a synchronization event signal in the tag field.

  In one embodiment, the adapter is utilized with input and output signals to provide a synchronization event signal as follows. An input signal is sampled using an address at an input interface with the adapter (eg, a DTL (dynamic termination logic) target interface). The input signal (eg, one or more bits) drives the most significant bit of the tag field in the header for memory write instructions. An output signal (eg, one or more bits) corresponding to the input signal is provided with an address at an interface (eg, a DTL initiator interface). The output signal is driven from the header of all memory write instructions at the timing when the most significant bit (bit 7 of byte 6) of the tag field for writing the memory coincides with the timing of address out of the memory To do. The output signal is zero in all other cycles (i.e. cycles in which no synchronization event signaling is performed) and is valid only when address out is valid.

  In some embodiments, synchronization signal transmission is disabled when connected to non-user PCI Express components and / or systems. For example, if endpoint devices 150 and 152 are of different types and endpoint device 152 is implemented using a non-user PCI Express component and / or system, signal transmission from endpoint device 150 Is disabled. The disable may be implemented using, for example, a switch or gate type technique. In addition, the approach may be implemented in connection with selective use of synchronization event signaling with an endpoint device compliant manufacturer, as discussed above.

  The techniques discussed above in connection with FIG. 1 and discussed herein can be implemented for various applications and in various ways. For example, in another embodiment, the tag field for write data posted in a PCI Express configuration is implemented such that each outstanding transaction that requests completion (an unposted action that requests a response) has a unique tag. Is defined. These salient transactions are not implemented to communicate synchronization event data in the tag field, and are compliant with PCI Express type communication. When implemented with an 8-bit data field, the read operation utilizes four least significant bits (LSBs) with four MSBs that are not utilized and thus implemented with a value of “0”. As discussed above, the completion logic is set to ignore the posted write tag field, typically implemented for PCI Express type communication. In this regard, the tag field is implemented for synchronous event communication using posted write data (ie, data that does not require completion).

  The length of the tag field is tailored for the specific application for which the PCI Express configuration is used and is further implemented according to the available bits. For example, in many PCI Express implementations, typically 5 bits may be reserved for the tag field. In other implementations, the tag field is implemented using 8 or more bits (eg, if an extension tag is available), as discussed in the previous section.

  In another embodiment, a JetStream PCI Express core marketed by Perle Systems (Nashville, Tennessee) is utilized in connection with the tag field synchronization approach. When the JetStream core is implemented, the most significant bit (MSB) is not used for cycles that require completion, and the entire 8-bit field is fixed to all zeros for writing. Optionally, the 8-bit field is implemented for synchronous event signal transmission. The approach may also be implemented differently for different vendors' PCI Express core types.

  In a more specific embodiment, endpoint devices implemented for synchronous event signal transmission using tag fields are configured to limit event signal transmission to selected device types. For example, if a synchronization event is to be signaled for reception by a device that meets a particular manufacturer's criteria, the endpoint device that receives the synchronization event signal meets that criteria (eg, a particular manufacturer A code or other recognition technique is implemented to verify that it was manufactured by. Synchronization event signaling can be enabled after the code or other recognition technique identifies that the criteria are met. For example, if synchronous event signaling is to be performed for two PCI Express endpoint devices with a common manufacturer, signal transmission by one PCI Express endpoint device may be performed by the other PCI Express endpoint device. Enabled after determining that they are from the same manufacturer.

  A tag (eg, a single bit or multiple bits) in the signal is added to the tag field using, for example, an adapter that places the tag signal in the communication header. The tag in the signal is arbitrarily mounted at almost the same timing for any address line, and the “Synchronization Event” is true, for example, the last write or vertical sync pulse is true. Set if. If a synchronization event is implemented, a tag out signal (eg, a single bit or multiple bits) is used to remove synchronization event information from additional communications performed via the adapter. It is added to the tag field. The tag-out may be implemented in a manner similar to the tag-in signal implementation discussed above. For example, an adapter may be used to extract bits from the tag field of the header in a manner similar to the extraction of address bits from the header, thereby providing a new signal with the same timing as the address out timing. May be.

  FIG. 2 shows a flow diagram for synchronous event signal transmission according to another embodiment of the present invention. At block 210, write data is generated at the first PCI Express endpoint device for posting to the PCI Express communication link. If, at block 220, a sync event is active, the write data tag field header is set at block 230 to indicate the active nature of the sync event. In block 240, the write data is posted with a synchronization event signal (eg, data indicating a synchronization event, such as a “true” bit). If the synchronization event is not active at block 220, the write data is posted at block 225 without a synchronization event signal.

  The posted write data is accessed at block 250 (eg, received at another PCI Express endpoint device). If, at block 260, the posted write data has a synchronization event signal, the data is processed at block 270 using the synchronization event signal. If the posted write data does not have a synchronization event signal at block 260, the data is processed at block 280 (without reference to synchronization). In some embodiments, the write data is processed if, for example, a particular synchronization event is applicable to a PCI Express endpoint device that is not necessarily the intended recipient of other posted write data. The synchronization event signal is processed without any processing.

  The techniques discussed herein may be implemented using various PCI Express type configurations and techniques. In some embodiments, the present technique provides a PCI Express type protocol (described above) that does not define a value in the tag field for requests that do not require completion (posted requests) and may contain any value. (See PCI Express Base Specification Revision 1.0a). The approach further complies with the PCI Express protocol for posted requests, indicating that the value in the tag field does not affect the processing of the request at the receiver, and therefore non-zero tag bits are valid. In addition, the approach can be implemented such that the tag field does not affect the receiver that processes the request.

  The various embodiments described above and illustrated in the figures are provided for purposes of illustration only and should not be construed as limiting the invention. Based on the above discussion and description, one of ordinary skill in the art will readily recognize that various modifications and changes can be made to the present invention without strictly following the examples and applications described and described herein. I will. For example, data other than synchronous event type data can be applied to transfer using a similar method. In addition, one or more of the above-described embodiments and implementations may be implemented using various PCI Express devices and other techniques including chips and printed circuit boards (PCBs). The above-described embodiments and implementations may also be combined with various circuits, devices, systems, and techniques, including those for use in connection with storage devices, displays, networks, and mobile communications. Further, the various embodiments discussed in the PCI and PCI Express type application environments may be implemented using various devices and communication techniques, including those not necessarily applicable to PCI or PCI Express. These approaches are implemented in connection with various embodiments of the present invention. Such modifications and changes do not depart from the true spirit and scope of the present invention as set forth in the claims.

FIG. 3 is a diagram for communication including signaling of synchronization events between devices communicatively coupled to a link, according to an embodiment of the present invention. FIG. FIG. 6 is a flow diagram for a technique for signaling synchronization events between endpoints on a PCI Express link according to another embodiment of the present invention.

Claims (20)

  A PCI Express communication link and the PCI Express communication link communicatively coupled to the PCI Express communication link and using the tag field of the posted data transmitted by the PCI Express communication link with the selected information. And a PCI Express endpoint device configured to communicate to another PCI Express endpoint device communicatively coupled to the PCI Express endpoint device.   The PCI Express communication link communicatively couples selected information including asynchronous event information with the PCI Express communication link using a posted write data tag field transmitted by the PCI Express communication link. The device of claim 1, configured to communicate to another configured PCI Express endpoint device.   The apparatus of claim 2, wherein the PCI Express endpoint device is further configured to communicate the selected information using only the tag field of the posted write data.   The apparatus of claim 2, wherein the PCI Express endpoint device is further configured to assign a unique tag to data transmitted by the PCI Express communication link that does not include the selected information.   The PCI Express endpoint device is further configured to assign the unique tag to data transmitted by the PCI Express communication link that requests a response from another PCI Express endpoint device. The device described in 1.   The PCI Express endpoint device is further configured to communicate information using only the tag field of posted data that does not require a response from another PCI Express endpoint device. The device described.   The apparatus of claim 1, wherein the PCI Express endpoint device is configured and configured to communicate information utilizing a tag field of a posted data packet transmitted over the PCI Express communication link.   The apparatus of claim 1, wherein the PCI Express endpoint device is configured and configured to communicate the selected information using a tag field in a header of a posted data packet.   The PCI Express endpoint device communicates selected information including synchronization event information to other PCI Express endpoint devices using the posted data tag field transmitted by the PCI Express communication link. The apparatus of claim 1, configured to:   The apparatus of claim 9, wherein the PCI Express endpoint device is configured to utilize the tag field to communicate a logical "true" signal indicating that a synchronization event is true.   The PCI Express endpoint device is configured to detect characteristics of other PCI Express endpoint devices and communicate the selected information using the tag field according to the detected characteristics. The apparatus of claim 1.   The PCI Express endpoint device detects a manufacturer characteristic of another PCI Express endpoint device and communicates the selected information using the tag field according to the detected manufacturer characteristic. The apparatus of claim 11, configured as follows.   The apparatus of claim 1, wherein the PCI Express endpoint device is configured to communicate the selected information using the tag field in a manner that is compliant with PCI Express.   Receiving a request from the PCI Express endpoint device to post the selected information to the PCI Express communication link, and in response to the request, passing the selected information to another PCI Express endpoint device; The apparatus of claim 1, further comprising an adapter configured and configured to generate a data packet including a tag field having information for communicating with.   A PCI Express system having a PCI Express communication link and at least two PCI Express endpoint devices communicatively coupled to the PCI Express communication link, the first of the at least two PCI Express endpoint devices Is configured to include synchronization event information in a tag field of write data posted to the PCI Express communication link, and the posted write data requests a completion response from the other PCI Express endpoint device. Rather, a second one of the at least two PCI Express endpoint devices is configured to receive and process the synchronization event information in the tag field   The system of claim 15, wherein the PCI Express communication link includes a PCI Express switch.   The PCI Express switch includes a virtual PCI Express bus, a switch upstream port communicatively coupled to the PCI Express bus, a PCI Express bus, and a first PCI Express endpoint device coupled to the first PCI Express endpoint device. The system of claim 16, comprising: one downstream port, and a plurality of downstream ports of the switch communicatively coupled to a second downstream port of the switch coupled to the second PCI Express endpoint device. .   A method of communicating information in a PCI Express device, including a PCI Express endpoint device communicatively coupled to a PCI Express communication link, wherein selected information is transmitted by the PCI Express communication link. To communicate to another PCI Express endpoint device communicatively coupled to the PCI Express communication link.   Communicating the selected information to another PCI Express endpoint device communicatively coupled to the PCI Express communication link using a tag field of data transmitted by the PCI Express communication link; 19. The method of claim 18, comprising communicating selected information utilizing a tag field of posted write data that does not require a completion response.   The step of communicating the selected information to another PCI Express endpoint device is a step of communicating synchronization event data to another PCI Express endpoint device using a tag field of the posted write data. 20. The method of claim 19, comprising:

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