JP2007306545A - Semiconductor device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that facilitates incorporation of a serial interface circuit, and electronic equipment. <P>SOLUTION: The semiconductor device includes a first semiconductor chip and a second semiconductor chip which has a high-speed serial I/F circuit transferring serial data to an external device through a serial bus and is stacked on the first semiconductor chip. A pad area 81 where a pad (electrode) for connecting the external device to the high-speed serial I/F circuit is disposed is provided along a side SB1 which is the short side of the second semiconductor chip. A pad area 82 where a pad for connecting an internal circuit that the first semiconductor chip includes to the high-speed serial I/F circuit is disposed is provided along a side SB2 which is the long side of the second semiconductor chip. Transmitter circuits TX0 to TX2 (or receiver circuits) for data transfer that a physical-layer circuit 40 includes and a transmitter circuit TCK (or a receiver circuit) for clock transfer are disposed along the side SB1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and an electronic apparatus.

  In recent years, high-speed serial transfer such as LVDS (Low Voltage Differential Signaling) has attracted attention as an interface for the purpose of reducing EMI noise. In this high-speed serial transfer, the transmitter circuit transmits serialized data as a differential signal, and the receiver circuit differentially amplifies the differential signal to realize data transfer.

  A general mobile phone includes a first device portion provided with buttons for inputting a telephone number and characters, a second device portion provided with an LCD (Liquid Crystal Display) and a camera device, and first and first devices. It is comprised by connection parts, such as a hinge which connects two apparatus parts. Therefore, data transfer between the first circuit board provided in the first device part and the second circuit board provided in the second device part is performed by serial transfer using a small amplitude differential signal. This is advantageous because the number of wires passing through the connecting portion can be reduced.

  In order to realize high-speed serial transfer with a mobile phone or the like, a BBE / APP (BaseBand Engine / Application Processor) or image processing controller is provided with a transmitter circuit for high-speed serial transfer, and a display driver is a receiver for high-speed serial transfer. It is necessary to provide a circuit or the like.

However, transmitter circuits and receiver circuits for high-speed serial transfer are configured by analog circuits. Therefore, when the manufacturing process is changed, the analog characteristics change, and the circuit needs to be redesigned. On the other hand, in BBE / APP, image processing controller, and display driver, it is necessary to actively adopt a fine process in order to realize cost reduction. Therefore, when trying to shrink the chip size of BBE / APP, image processing controller, and display driver by adopting a fine process, it is not necessary to redesign the transmitter circuit and receiver circuit for high-speed serial transfer. It becomes necessary, leading to a prolonged development period.
JP 2001-222249 A

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide a semiconductor device and an electronic apparatus that can easily incorporate a serial interface circuit.

  The present invention has a serial interface circuit for transferring serial data between a first semiconductor chip and an external device via a serial bus, and a second semiconductor stacked on the first semiconductor chip. And a first electrode region including an electrode for connecting the external device and the serial interface circuit is provided along a first side which is a short side of the second semiconductor chip. And an electrode for connecting the internal circuit included in the first semiconductor chip and the serial interface circuit is disposed along a second side which is a long side of the second semiconductor chip. The present invention relates to a semiconductor device provided with an electrode region.

  According to the present invention, the serial interface circuit included in the second semiconductor chip transfers serial data to and from an external device. In the present invention, the second semiconductor chip including such a serial interface circuit is stacked on the first semiconductor chip. Therefore, for example, even if the manufacturing process and circuit configuration of the first semiconductor chip are changed, it is not necessary to change the manufacturing process and circuit configuration of the second semiconductor chip. Therefore, it is possible to facilitate the incorporation of the serial interface circuit into the semiconductor device while maintaining the transmission quality of the serial transfer.

  In the present invention, a first electrode region in which an electrode for connecting an external device and a serial interface circuit is disposed is provided along the first side which is the short side of the second semiconductor chip. By doing so, it becomes possible to minimize the skew and signal delay of the serial transfer signal and maintain the transmission quality of the serial transfer. In the present invention, a second electrode in which an internal circuit included in the first semiconductor chip and the serial interface circuit are connected is disposed along the second side which is the long side of the second semiconductor chip. An electrode region is provided. Accordingly, a large number of electrodes necessary for interfacing with the internal circuit of the first semiconductor chip can be arranged in the second electrode region, and the incorporation of the serial interface circuit into the semiconductor device can be facilitated.

  In the present invention, the electrode for connecting the internal circuit included in the first semiconductor chip and the serial interface circuit along the third side facing the first side of the second semiconductor chip. There may be provided a third electrode region in which is disposed.

  In this way, the number of electrodes that can be used for interfacing with the internal circuit can be further increased.

  In the present invention, serial transfer serial data electrodes may be arranged in the first electrode region.

  In this way, for example, it is possible to connect the transmitter circuit or receiver circuit for data transfer and the electrode for serial data with a short path.

  In the present invention, an electrode for serial transfer serial data and an electrode for serial transfer clock may be arranged in the first electrode region.

  In this way, for example, it becomes possible to connect the transmitter circuit or receiver circuit for data transfer and the electrode for serial data with a short path, and at the same time, the transmitter circuit or receiver circuit for clock transfer and the clock circuit It is possible to connect the electrodes with a short path.

  In the present invention, the serial interface circuit includes a physical layer circuit that transmits and receives data to and from the external device via a serial bus, and an internal circuit included in the first semiconductor chip. A first logic circuit having at least one of a parallel / serial conversion circuit for converting parallel data into serial data and a serial / parallel conversion circuit for converting serial data from the external device into parallel data; and the first semiconductor And a second logic circuit having an internal interface circuit that transfers parallel data to and from an internal circuit included in the chip.

  In this way, the physical layer circuit transmits and receives serial data via the serial bus, and the first logic circuit converts parallel data to serial data, or serial data to parallel data. It becomes possible to do. The second logic circuit can transfer parallel data to and from the internal circuit included in the first semiconductor chip.

  In the present invention, the physical layer circuit is disposed on a first side which is a short side of the second semiconductor chip, and the second logic circuit is provided on the first side of the second semiconductor chip. You may arrange | position on the 3rd edge | side side which opposes an edge | side.

  In this way, signal transmission in the serial interface circuit can be made efficient.

  In the present invention, the serial interface circuit includes an internal interface circuit that transfers parallel data to and from an internal circuit included in the first semiconductor chip, and the internal interface circuit is in the first interface mode, A second interface mode that is set when the second semiconductor chip is placed on the first semiconductor chip by transferring K-bit parallel data to / from an internal circuit included in the first semiconductor chip. Then, parallel data transfer of J bits (J <K) may be performed with the internal circuit included in the first semiconductor chip.

  According to this configuration, when the second semiconductor chip is stacked on the first semiconductor chip, the second interface mode is set so that the signal line to the internal circuit included in the first semiconductor chip is set. The number can be reduced.

  According to the present invention, an electrode for J-bit parallel data is disposed along a second side which is a long side of the second semiconductor chip, and an electrode for parallel data of K-J bit is provided on the first side. The second semiconductor chip may be arranged along a fourth side facing the second side.

  In this way, for example, in the first interface mode, parallel data can be transferred using the KJ-bit parallel data electrodes arranged along the fourth side.

  In the present invention, in the first interface mode, the internal interface circuit samples parallel data at one of the rising edge and the falling edge of the parallel data sampling clock, and performs the second interface mode. Then, parallel data may be sampled at both the rising edge and falling edge of the sampling clock.

  In this way, in the second interface mode, parallel data is sampled at both the rising edge and falling edge of the sampling clock. Accordingly, a large amount of information can be transferred using a small number of parallel data signal lines.

  In the present invention, the first semiconductor chip may include a stack prohibiting circuit in which stacking is prohibited, and the second semiconductor chip may be stacked in an area other than the area of the stack prohibiting circuit.

  In this way, it is possible to prevent the circuit reliability and circuit characteristics of the first semiconductor chip from deteriorating.

  In the present invention, the stack prohibition circuit may be a DRAM.

  However, the stack prohibition circuit is not limited to the DRAM.

  In the present invention, the serial interface circuit includes a physical layer circuit that transmits and receives data to and from the external device via a serial bus, and the physical layer circuit is a transmitter for data transfer. A circuit or receiver circuit, a transmitter circuit or receiver circuit for clock transfer, and the transmitter circuit or receiver circuit for data transfer and the transmitter circuit or receiver circuit for clock transfer are short circuits of the second semiconductor chip. You may arrange | position along the 1st edge | side which is an edge | side.

  In this way, signal skew and signal delay can be minimized.

  In the present invention, the physical layer circuit includes first to Nth transmitter circuits or receiver circuits for data transfer of the first to Nth channels, and the first to Nth transmitter circuits for data transfer. Alternatively, the receiver circuit may be arranged along the first side of the second semiconductor chip.

  This makes it possible to minimize signal skew and signal delay even when transferring data for one or more channels.

  In the present invention, the clock transfer transmitter circuit or receiver circuit is disposed between the data transfer first transmitter circuit or receiver circuit and the data transfer second to Nth transmitter circuits or receiver circuits. May be.

  This makes it possible to minimize data and clock signal skews and signal delays even when transferring data for one or more channels.

  In the present invention, the length of the second side of the second semiconductor chip is LB, and the second side of the first semiconductor chip is parallel to the second side of the second semiconductor chip. And LM is the maximum length in a plan view on the design rule from the electrode to the end of the first semiconductor chip for the wiring connected to the electrode of the second semiconductor chip. In this case, LB ≧ LA-2 × LM may be satisfied.

  In this way, the second semiconductor chip can be stacked on the first semiconductor chip while observing the design rule regarding the maximum wiring length LM.

  The present invention also relates to an electronic device including any of the semiconductor devices described above and a display panel that performs a display operation based on data serially transferred by the semiconductor device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Stack Arrangement As shown in FIG. 1A, in this embodiment, semiconductor devices 2 and 4 (integrated circuit devices) include high-speed serial I / F (interface) circuits 6 and 8, respectively. Data transfer (at least one of data transmission and reception) is performed via the serial bus using the high-speed serial I / F circuits 6 and 8. Specifically, for example, data transfer is performed using a differential signal. More specifically, data transfer is performed using a small amplitude differential signal (LVDS). The serial bus may have a single channel configuration or a multi-channel configuration. Further, instead of differential transfer, single end transfer may be performed.

  Taking a mobile phone as an example, the semiconductor device 2 in FIG. 1A is a BBE / APP or an image processing controller (display controller), and is the first mobile phone provided with buttons for inputting a telephone number and inputting characters. It is mounted on the first circuit board of one device part. The semiconductor device 6 is a display driver (LCD driver) and is mounted on the second circuit board of the second device portion of the cellular phone provided with a display panel (LCD) and a camera device.

  Conventionally, data transfer between these semiconductor devices 2 and 4 has been realized by parallel transfer at a CMOS voltage level. For this reason, the number of wirings that pass through a connecting portion such as a hinge connecting the first and second device portions increases, which causes problems such as hindering the degree of freedom in design and generating EMI noise.

  On the other hand, in FIG. 1A, data transfer between the semiconductor devices 2 and 4 is realized by serial transfer with a small amplitude. Therefore, it is possible to reduce the number of wires passing through the connection portions of the first and second device portions, and to reduce the generation of EMI noise.

  The high-speed serial I / F circuits 6 and 8 include analog physical layer circuits (transmitter circuit and receiver circuit) for performing small-amplitude serial transfer. In such a physical layer circuit, if the manufacturing process is changed, the characteristics of the analog circuit change, and the circuit needs to be redesigned. On the other hand, in the semiconductor devices 2 and 4, a fine process is positively employed in order to realize cost reduction. Therefore, if it is attempted to shrink the chip size of the semiconductor devices 2 and 4 by employing a fine process, the high-speed serial I / F circuits 6 and 8 need to be redesigned even though they are not originally necessary. Increases design man-hours and costs.

  Therefore, in the present embodiment, as shown in the plan view of FIG. 1B, the first and second semiconductor chips 10 and 20 (first and second) are added to the semiconductor device (2 or 4 in FIG. 1A). Chip). Here, the first semiconductor chip 10 (main chip) includes an internal circuit 12 (memory, logic circuit, processor, driver circuit, or the like). The second semiconductor chip 20 (subchip) includes a high-speed serial I / F circuit 30 (6 or 8 in FIG. 1A).

  Specifically, the high-speed serial I / F circuit 30 (serial interface circuit in a broad sense) transfers serial data to / from an external device (for example, an external semiconductor device) via a serial bus. As shown in FIG. 1B, in this embodiment, the second semiconductor chip 20 including such a high-speed serial I / F circuit 30 is stacked on the first semiconductor chip 10 that is the main chip.

  Further, in the present embodiment, as shown in FIG. 1B, a pad (for connecting the external device and the high-speed serial I / F circuit 30) along the side SB1, which is the short side of the second semiconductor chip 20, is provided. A first pad region 81 (first electrode region in a broad sense) in which an electrode is disposed in a broad sense is provided. Further, pads (electrodes) for connecting the internal circuit 12 included in the first semiconductor chip 10 and the high-speed serial I / F circuit 30 are arranged along the side SB2 which is the long side of the second semiconductor chip 20. A second pad region 82 (second electrode region in a broad sense) is provided.

  FIG. 2 shows an example of a schematic cross-sectional view of the stack structure of the first and second semiconductor chips 10 and 20. As shown in FIG. 2, the first semiconductor chip 10 is bonded to a substrate 500 (wiring substrate) by a die bonding material 510 (adhesive). The second semiconductor chip 20 is mounted on the first semiconductor chip 10 and bonded to the first semiconductor chip 10 with a die bonding material 512 (adhesive material).

  Electrodes 520 (pads, bumps, etc.) formed on the first semiconductor chip 10 are electrically connected to a wiring pattern 502 (land portion) of the substrate 500 via wirings 522 (bonding wires, etc.). Further, the electrodes 530 (pads, bumps, etc.) formed on the second semiconductor chip 20 are electrically connected to the wiring pattern 503 (land portion) of the substrate 500 through the wirings 532 (bonding wires, etc.). The wiring patterns 502 and 503 are electrically connected to external terminals 506 and 507 (solder balls or the like) through through holes 504 and 505.

  In FIG. 2, the substrate 500 may be formed of an organic material or an inorganic material. Or these composite structures may be sufficient. Examples of the substrate 500 formed of an organic material include a flexible substrate made of a polyimide resin. Moreover, you may use the tape used by TAB technique as a flexible substrate. Examples of the substrate 500 formed of an inorganic material include a ceramic substrate and a glass substrate. As a composite structure of organic and inorganic materials, a glass epoxy substrate can be mentioned.

  The first and second semiconductor chips 10 and 20 may be arranged face-up with the active surface (circuit surface) up, or face-down with the active surface down. In FIG. 2, a two-stage stack structure is used, but a three-stage or more stack structure may be used. Various materials can be used as the die bonding materials 510 and 512. The electrodes 520 and 530 may be provided with bumps by solder balls, gold wire balls, gold plating, or the like, and the electrodes 520 and 530 themselves may have a bump shape. The wirings 522 and 532 may be wirings formed of gold bonding wires, or wirings formed of a conductive paste or the like. Further, the external terminals 506 and 507 are not limited to a ball shape, and may be a flat land shape.

  When the electrode 520 of the first semiconductor chip 10 and the electrode 530 of the second semiconductor chip 20 are connected, the electrodes 520 and 530 are electrically connected via the wiring 522, the wiring patterns 502 and 503, and the wiring 532. The electrodes 520 and 530 may be directly connected by wiring (bonding wire or the like).

  As described above, in the present embodiment, the second semiconductor chip 20 including the high-speed serial I / F circuit 30 is stacked on the first semiconductor chip 10 (vertically stacked). This facilitates the incorporation of the high-speed serial I / F circuit 30 into the semiconductor device.

  For example, as a comparative example, a method of incorporating the high-speed serial I / F circuit 30 as the internal circuit 12 of the first semiconductor chip 10 (method of incorporating in the same chip) is conceivable. However, in the method of this comparative example, if the manufacturing process is changed due to version upgrade of the first semiconductor chip 10 which is the main chip, the high-speed serial I / F circuit 30 is not necessary even though it is originally necessary. Design becomes necessary.

  On the other hand, according to the present embodiment, even if the manufacturing process or the like of the first semiconductor chip 10 is changed, it is not necessary to change the manufacturing process or the like for the high-speed serial I / F circuit 30. Can be greatly reduced. Also, since the analog circuit characteristics do not change, the transmission quality can be maintained.

  In the present embodiment, as shown in FIG. 1B, a pad region 81 in which pads for serial transfer with an external device are arranged is provided along the short side SB1 of the second semiconductor chip 20. In this way, when the data transfer transmitter circuit 44 (or receiver circuit) is arranged along the side SB1 as shown in FIG. 3A, for example, the serial transfer pads DP and DM The transmitter circuit 44 can be connected by a short path. Therefore, signal skew and signal delay can be minimized, and transmission quality of serial transfer can be improved. Further, as shown in FIG. 3B, when the transmitter circuit 44 (or receiver circuit) for data transfer and the transmitter circuit 46 (or receiver circuit) for clock transfer are arranged along the side SB1, DP, DM and The transmitter circuit 44 can be connected by a short path, and the serial transfer clock pads CKP and CKM and the transmitter circuit 46 can also be connected by a short path. Therefore, the skew of the data and clock signals and the signal delay can be minimized, and the serial data sampling error can be prevented from occurring on the receiving side. If the serial transfer pads DP, DM, CKP, and CKM are disposed along the side SB1 as shown in FIGS. 3A and 3B, the first and second signal lines ( For example, DP and DM, CKP and CKM) can be easily made equal in length, and deterioration of transmission quality can be prevented.

  In the pad area 81 (first electrode area), only the serial transfer pads DP and DM may be arranged, or DP and DM and the serial transfer clock pads CKP, Only CKM may be arranged. Alternatively, only DP, DM, CKP, CKM and analog circuit (physical layer circuit) power supply pads may be arranged. In this way, the length of the short side SB1 of the second semiconductor chip 20 can be shortened, and the second semiconductor chip 20 can be formed into an elongated shape. Therefore, when the first semiconductor chip 10 has a stack prohibition circuit in which stack placement is prohibited, the elongated second semiconductor chip 20 can be placed in a stack while avoiding the area of the stack prohibition circuit. .

  In the present embodiment, as shown in FIG. 1B, a pad for interfacing with the internal circuit 12 of the first semiconductor chip 10 is arranged along the long side SB2 of the second semiconductor chip 20. A region 82 (second electrode region) is provided. If the pad region 82 is provided along the long side SB2 in this way, a large number of pads necessary for the interface with the internal circuit 12 of the first semiconductor chip 10 can be arranged in the pad region 82. Therefore, connection of interface signals between the high-speed serial I / F circuit 30 and the internal circuit 12 is facilitated, and incorporation of the high-speed serial I / F circuit 30 into the semiconductor device can be facilitated. When the high-speed serial I / F circuit 30 and the internal circuit 12 are connected by a parallel bus, a bus having a sufficient bit width can be used as the parallel bus.

  As shown in FIG. 3C, the internal circuit 12 of the first semiconductor chip 10 and the high-speed serial I / F circuit 30 are connected along the side SB3 facing the side SB1 of the second semiconductor chip 20. A pad region 83 (a third electrode region in a broad sense) in which pads (electrodes) for the purpose are arranged may be further provided. In this way, the number of pads used for interfacing with the internal circuit 12 can be further increased, and connection of interface signals between the high-speed serial I / F circuit 30 and the internal circuit 12 can be further facilitated. When the high-speed serial I / F circuit 30 and the internal circuit 12 are connected by a parallel bus, the bit width of the parallel bus can be further increased.

2. Configuration and Arrangement of High-Speed Serial I / F Circuit FIG. 4A shows a configuration example of the high-speed serial I / F circuit 30. Note that the high-speed serial I / F circuit 30 is not limited to the configuration shown in FIG. 4A, and some of the components shown in FIG. 4A may be omitted or may be components other than those shown in FIG. May be included. For example, the high-speed serial I / F circuit 30 may be configured not to include the high-speed logic circuit 50 or the logic circuit 60.

  The physical layer circuit 40 (analog circuit, analog front end circuit, transceiver) is an analog circuit that performs at least one of data transmission and reception with an external device (external semiconductor device or the like) via a serial bus. The physical layer circuit 40 may include a transmitter circuit 42, for example. The physical layer circuit 40 may include a transmitter circuit or a receiver circuit. Or the structure containing both a transmitter circuit and a receiver circuit may be sufficient. Further, a transmitter circuit and a receiver circuit for data transfer may be provided as a transmitter circuit and a receiver circuit, or a transmitter circuit and a receiver circuit for data transfer and clock (strobe) transfer may be provided.

  The high-speed logic circuit 50 (first logic circuit in a broad sense) is a logic circuit that operates with a high-speed clock. Specifically, it operates with a clock having the same frequency as the transfer clock of the serial bus. The high-speed logic circuit 50 can include, for example, a parallel / serial conversion circuit 52. Here, the parallel / serial conversion circuit 52 converts the parallel data from the internal circuit 12 included in the first semiconductor chip 10 (parallel data received by the logic circuit 60 via the parallel bus to the internal circuit 12) into serial data. It is a circuit to convert to. The serial data obtained by the conversion is transmitted to the external device via the serial bus.

  The high-speed logic circuit 50 may include a parallel / serial conversion circuit, or converts serial data from an external device (serial data received by the physical layer circuit 40 via the serial bus) into parallel data. A configuration including a serial / parallel conversion circuit may be used. Alternatively, the configuration may include both a parallel / serial conversion circuit and a serial / parallel conversion circuit. The high-speed logic circuit 50 may include other logic circuits (for example, a FIFO, an elasticity buffer, a frequency divider circuit, etc.) that operate with a high-speed clock corresponding to the transfer clock of the serial bus.

  The logic circuit 60 (second logic circuit in a broad sense) is a logic circuit that operates with a clock slower than the operation clock of the high-speed logic circuit 50. Specifically, for example, it operates with a clock having a frequency equivalent to a sampling clock for parallel data. The logic circuit 60 includes an internal I / F circuit 62 (host I / F circuit, parallel I / F circuit) that performs an interface process with the internal circuit 12 included in the first semiconductor chip 10. Specifically, the internal I / F circuit 62 transfers (receives and transmits) parallel data to and from the internal circuit 12 included in the first semiconductor chip 10.

  If the circuit configuration as shown in FIG. 4A is adopted, data transfer is performed with an external device by high-speed serial transfer, while it is compared with serial transfer with the first semiconductor chip 10. Data transfer is performed by low-speed parallel transfer. As for serial transfer, the transmission quality can be maintained by optimizing the circuit arrangement and pad arrangement in the high-speed serial I / F circuit 30. On the other hand, since parallel transfer with the first semiconductor chip 10 is slower than serial transfer, the configuration and arrangement of the internal circuit 12 of the first semiconductor chip 10 may be changed according to product specifications. Can easily cope with this.

  In particular, there are various standards for high-speed serial transfer, and it is desirable that high-speed serial transfer of such various standards can be easily handled. In this regard, according to the configuration of FIG. 4A, a general-purpose parallel I / F can be adopted for the interface with the semiconductor chip 10. Therefore, there is an advantage that it is possible to easily cope with high-speed serial transfer of various standards only by changing the physical layer circuit of the high-speed serial I / F circuit 30. If the interface with the semiconductor chip 10 is a general-purpose parallel I / F, high-speed serial transfer with different standards can be handled without changing the configuration of the internal circuit 12 of the first semiconductor chip 10. Therefore, it is possible to provide a semiconductor device that can easily incorporate high-speed serial I / F circuits of various standards. Furthermore, the package size can be reduced by stacking the first and second semiconductor chips 10 and 20.

  In the present embodiment, as shown in FIG. 4B, the physical layer circuit 40 is disposed on the side SB <b> 1 that is the short side of the second semiconductor chip 20. On the other hand, the logic circuit 60 (second logic circuit) is disposed on the side SB3 facing the side SB1 of the second semiconductor chip 20. The high-speed logic circuit 50 (first logic circuit) is disposed between the physical layer circuit 40 and the logic circuit 60. That is, the circuits are arranged in the order of the physical layer circuit 40, the high-speed logic circuit 50, and the logic circuit 60 from the side SB1 to the side SB3.

  With the circuit arrangement as shown in FIG. 4B, signal lines between the physical layer circuit 40 and the high-speed logic circuit 50 and between the high-speed logic circuit 50 and the logic circuit 60 can be connected by a short path. Become. Therefore, signal skew and signal delay between these circuits can be optimized, and efficient and high-quality signal transmission becomes possible.

  4B, the length of the side SB1 can be shortened, while the length of the side SB2 can be increased. Therefore, the second semiconductor chip 20 can be slim and elongated. Therefore, for example, when the first semiconductor chip 10 has a stack prohibition circuit (for example, a DRAM or an analog circuit) in which stack arrangement is prohibited, the second semiconductor chip having an elongated shape avoiding the area of the stack prohibition circuit. 20 can be stacked. Further, if the second semiconductor chip 20 is formed in an elongated shape, the bonding length of the wiring from the second semiconductor chip 20 can be shortened, so that the mounting quality can be secured. In addition, when the bonding length is shortened, it is possible to minimize the deterioration of transmission quality.

  Note that the stack position of the second semiconductor chip 20 is not limited to the position shown in FIG. For example, in FIG. 4B, the second semiconductor chip 20 is stacked so that one side of the internal circuit 12 and one side (SB2) of the second semiconductor chip 20 substantially coincide with each other. The second semiconductor chips 20 may be stacked in positions that do not match. Further, the circuit arrangement in the high-speed serial I / F circuit 30 is not limited to the arrangement shown in FIG. For example, a modification in which the high-speed logic circuit 50 is not disposed between the physical layer circuit 40 and the logic circuit 60 is possible.

3. Detailed Configuration of High-Speed Serial I / F Circuit FIG. 5 shows a detailed configuration example of the high-speed serial I / F circuit 30. In FIG. 5, the physical layer circuit 40 includes transmitter circuits TX0, TX1, and TX2 (first to Nth transmitter circuits in a broad sense) for data transfer. A clock transfer transmitter circuit TCK is also included.

  The data transfer transmitter circuit TX0 receives the serial data from the parallel / serial conversion circuit 52, drives the differential signal lines D0P and D0M, and transmits the data. Similarly, the data transfer transmitter circuits TX1 and TX2 receive serial data from the parallel / serial conversion circuit 52, and drive the differential signal lines of D1P and D1M and D2P and D2M, respectively, to transmit data. . The transmitter circuit TCK for clock transfer drives the differential signal lines of CKP and CKM based on the clock generated by the PLL circuit 72 (or its divided clock) and transmits the clock. These transmitter circuits TX0, TX1, TX2, and TCK can be realized by, for example, an analog circuit (an operational amplifier or the like) that drives a differential signal line of a serial bus by current driving or voltage driving.

  Although FIG. 5 shows a case where the physical layer circuit 40 includes a transmitter circuit, the physical layer circuit 40 may include a receiver circuit. In this case, the data transfer receiver circuit (first to Nth receiver circuits) receives the data transferred via the differential signal line of the serial bus, and the received serial data is serial / parallel. It is output to the conversion circuit. The clock transfer receiver circuit receives the clock transferred via the differential signal line of the serial bus. These receiver circuits can be realized by analog circuits that detect the drive current or drive voltage of the differential signal line of the serial bus. Specifically, the receiver circuit amplifies the voltage generated at both ends of the resistance element provided between the first and second signal lines (for example, D0P and D0M) constituting the differential signal line, for example, so that the data And receive clocks.

  The bias circuit 70 generates a bias voltage for controlling the bias current and outputs the bias voltage to the physical layer circuit 40 or the like. The bias circuit 70 can be configured by a reference voltage generation circuit, a current mirror circuit, or the like.

  The PLL circuit 72 (clock generation circuit in a broad sense) generates a clock synchronized with PCLK based on the pixel clock PCLK and supplies the clock to the high-speed logic circuit 50 or the like.

  The logic circuit 60 includes an internal I / F circuit 62. A parity generation circuit 64, a data separator 66, and a register 68 are also included.

  The internal I / F circuit 62 uses the interface signals including the parallel data VD [23: 0], the vertical synchronization signal VS, the horizontal synchronization signal HS, the data enable signal DE, and the like to use the internal circuit 12 of the first semiconductor chip 10. Interfacing with the.

  The parity generation circuit 64 generates a parity bit to be added to the data. The data separator 66 performs data separation processing according to the number of data transfer channels. The register 68 (configuration register) is a register for performing various settings such as the number of transfer channels and interface mode.

  For example, by setting the number of transfer channels in the register 68, as shown in FIGS. 6A, 6B, and 6C, the number of used channels can be changed from 1 channel, 2 channels, and 3 channels according to the transfer rate. You will be able to choose.

  For example, in the 1-channel mode of FIG. 6A, 8-bit R data, 8-bit G data, 8-bit B data, and the like are serially transferred using D0 (D0P, D0M) which is channel 1. In this case, for example, the pixel clock PCLK is 4 to 15 MHz, and the bandwidth of the transfer rate is 120 to 450 Mbps.

  In the 2-channel mode of FIG. 6B, 8-bit R data, 4-bit G data, etc. are transferred using D0, and 4-bit G data is transmitted using D1 (D1P, D1M) which is channel 2. , 8-bit B data and the like are transferred. In this case, for example, PCLK is 8 to 30 MHz, and the bandwidth is 120 to 450 Mbps.

  6C, 8-bit R data or the like is transferred using D0, 8-bit G data or the like is transferred using D1, and D2 (D2P, D2M) that is channel 3 is transferred. 8-bit B data or the like is transferred using. In this case, for example, PCLK is 20 to 65 MHz, and the bandwidth is 200 to 650 Mbps.

  6A, 6B, and 6C is realized by the data separator 66 in FIG.

4). Internal I / F Circuit The internal I / F circuit 62 of the present embodiment can perform parallel transfer in the first and second interface modes with the internal circuit 12 of the first semiconductor chip 10.

  For example, in the first interface mode, the internal I / F circuit 62 transfers parallel data of 24 bits (K bits in a broad sense) to and from the internal circuit 12 of the first semiconductor chip 10 as shown in FIG. I do. On the other hand, in the second interface mode, as shown in FIG. 8A, parallel data of 12 bits (J bits in a broad sense, J <K) is transmitted to the internal circuit 12 of the first semiconductor chip 10. Perform the transfer. More specifically, in the first interface mode of FIG. 7, the internal I / F circuit 62 is connected to the rising edge (or may be the falling edge) of PCLK, which is a sampling clock for parallel data, from the internal circuit 12. Performs parallel data sampling. On the other hand, in the second interface mode (double data rate mode) in FIG. 8A, parallel data from the internal circuit 12 is sampled at both the rising edge and falling edge of PCLK.

  That is, in the first interface mode of FIG. 7, at the rising edge of PCLK, the data for one pixel consisting of 8-bit R data, G data, B data, VS, HS, and DE is sampled and the internal I / F circuit is sampled. 62. This first interface mode is a standard parallel interface mode, and all 24-bit VD [23: 0] are used.

  On the other hand, in the second interface mode of FIG. 8A, at the rising edge of PCLK, data consisting of 8-bit R data, 4-bit G data, VS, HS, and DE is sampled, and the internal I / F circuit is sampled. 62. At the falling edge of PCLK, data consisting of 4-bit G data, 8-bit B data, RSRV0, RSRV1, and RSRV2 are sampled and taken into the internal I / F circuit 62. The second interface mode is a mode for reducing the number of connection signal lines with the first semiconductor chip 10 (host chip). In this mode, 24-bit data (display data) can be transferred using only 12-bit VD [11: 0].

  That is, when the second semiconductor chip 20 is stacked on the first semiconductor chip 10 as shown in FIG. 4B, all the sides SB1 of the second semiconductor chip 20 are restricted due to the restriction of the bonding length design rule. It is difficult to bond the wiring to the pad of SB4 (electrode in a broad sense). Therefore, when the second semiconductor chips 20 are stacked, there is a limit to the number of pads that can be bonded to the wiring.

  On the other hand, the second semiconductor chip 20 may be used as a single general-purpose chip without being stacked on the first semiconductor chip 10. When used as a general-purpose chip in this way, wiring can be bonded to the pads of all the sides SB1 to SB4 of the second semiconductor chip 20.

  Therefore, in this embodiment, when the second semiconductor chip 20 is used as a single general-purpose chip, the first interface mode in FIG. 7 is set, and all the 24-bit VD [23: 0] pads are set. Use to transfer data. Specifically, as shown in FIG. 11 to be described later, for example, pads of VD [11: 0] are arranged on the sides SB2 and SB3 of the second semiconductor chip 20, and VD [23:12] is arranged on the side SB4. ] Pad. In the first interface mode, wiring is bonded to all pads of VD [23: 0] of these sides SB2, SB3, and SB4, and 24-bit VD [23: 0] as shown in FIG. All of these are used to transfer data. By doing so, the second semiconductor chip 20 can be used in a standard 24-bit parallel interface mode, and the versatility of the second semiconductor chip 20 can be improved.

  On the other hand, when the second semiconductor chip 20 is used while being stacked on the first semiconductor chip 10, the second interface mode in FIG. 8A is set and the 12-bit VD [11: 0] is set. Use only the pads to transfer data. Specifically, in FIG. 11 to be described later, wiring is bonded only to the pads of VD [11: 0] on the sides SB2 and SB3, and 12-bit VD [11: 0] as shown in FIG. ] Is used to transfer data. By doing so, it is not necessary to bond a wire to the pad of VD [23:12] of the side SB4 when stacking on the first semiconductor chip 10, so that the design rule regarding the bonding length can be observed. Therefore, the second semiconductor chip 20 can be suitably used as a stacking chip.

  As described above, according to the present embodiment, by preparing the first and second interface modes, the second semiconductor chip 20 can be used as both a single general-purpose chip and a stacking chip. Can be improved. Note that the first and second interface modes can be switched by, for example, a voltage level applied to a mode setting pad (XDDR or the like) provided in the second semiconductor chip 20.

  In the second interface mode of FIG. 8A, the reserve bits RSRV0, RSRV1, and RSRV2 are multiplexed with the HS, VS, and DE signals. That is, the internal I / F circuit 62 can capture HS, VS, DE information by sampling the HS, VS, DE signals at the rising edge of PCLK (one edge in a broad sense), By sampling the HS, VS, and DE signals at the falling edge of PCLK (the other edge in a broad sense), information of reserve bits RSRV0, RSRV1, and RSRV2 that are information other than HS, VS, and DE can be captured. it can. By using these reserve bits RSRV0, RSRV1, and RSRV2, various information can be transferred to and from the internal circuit 12 of the first semiconductor chip 10.

  For example, by using the reserve bits RSRV0, RSRV1, and RSRV2, commands such as a reset command, a shutdown command, and an operation mode switching command can be transferred to the reception (RX) side.

  Alternatively, as shown in FIG. 8B, when two (plural) display drivers 230 and 232 are used for one line of the display panel 240, the data is addressed to either of the display drivers 230 and 232. Can be specified by reserve bits RSRV0, RSRV1, and RSRV2. For example, the image processing controller 200 (internal circuit 12) designates the high-speed serial I / F circuit 210 (internal I / F circuit) on the transmission (TX) side by parallel data and reserve bits RSRV0, RSRV1, and RSRV2. Data destination information is transferred. The transmission (TX) side high-speed serial I / F circuit 210 converts the information into serial data and transfers the information to the reception (RX) side high-speed serial I / F circuit 220. Then, for example, when RSRV0 = RSRV1 = RSRV2 = 0, the high-speed serial I / F circuit 220 on the reception side outputs data from the transmission side to the display driver 230, and RSRV0 = RSRV1 = RSRV2 = 1. In this case, data from the transmission side is output to the display driver 232. If such reserved bits RSRV0, RSRV1, and RSRV2 are used, various attributes can be added for each pixel data, and various uses that have not been conventionally achieved can be realized.

  FIG. 9 shows a configuration example of the internal I / F circuit 62 that can realize the first and second interface modes as described above. In FIG. 9, registers 90, 92 and 94 sample VD [23:12], VD [11: 0] and VS / HS / DE, respectively, by sampling at the rising edge of PCLK. The registers 100, 102, and 104 sample and capture the outputs of the registers 90, 92, and 94 at the falling edge of PCLK, respectively. When the signal MODESEL is set to the first interface mode, the selector 130 selects the output of the registers 100, 102, and 104 and outputs it to the subsequent circuit (for example, the data separator 66).

  On the other hand, the registers 110 and 112 sample and capture VD [11: 0] and VS / HS / DE, respectively, at the rising edge of PCLK. The registers 120 and 122 sample and capture the outputs of the registers 110 and 112 at the falling edge of PCLK, respectively. The registers 124 and 126 sample and capture VD [11: 0] and VS / HS / DE, respectively, at the falling edge of PCLK. When the signal MODESEL is set to the second interface mode, the selector 130 selects the output of the registers 120, 122, 124, 126 and outputs it to the subsequent circuit.

  As described above, data transfer in the first and second interface modes of FIGS. 7 and 8A becomes possible.

5). Detailed Arrangement Example Next, a detailed arrangement example of the first and second semiconductor chips 10 and 20 and the circuits included therein will be described. For example, FIG. 10 shows a detailed arrangement example of the first and second semiconductor chips 10 and 20. In FIG. 10, the first semiconductor chip 10 includes a G / A (gate array) 13, DRAMs 14, 15 and the like as the internal circuit 12. Here, the DRAMs 14 and 15 are circuits in which stack arrangement is prohibited (hereinafter referred to as a stack prohibition circuit).

  As shown in FIG. 10, the second semiconductor chip 20 is stacked in a region (G / A 13) other than the region of the stack prohibition circuits (DRAMs 14 and 15) in plan view. If it arrange | positions in such an area | region, the situation where the reliability and circuit characteristic of the circuit of the 1st semiconductor chip 10 will deteriorate by the 2nd semiconductor chip 20 stacking arrangement | positioning can be prevented.

  That is, when the second semiconductor chips 20 are stacked, the stress generated thereby becomes an external pressure, and the reliability of the circuit of the first semiconductor chip 10 may be deteriorated. For example, the DRAMs 14 and 15 have a built-in fuse circuit for fine adjustment of characteristics, and the fuse circuit may be weak against external pressure. In this case, if the second semiconductor chip 20 is stacked on the DRAMs 14 and 15, the reliability of the circuit deteriorates. In addition, since the high-speed serial I / F circuit 30 included in the second semiconductor chip 20 operates at high speed, this high-speed operation becomes a noise source, which adversely affects the operation of the memory and analog circuit included in the first semiconductor chip 10. There is a risk. For example, the memory cells of the DRAMs 14 and 15 may malfunction due to noise from the high-speed serial I / F circuit 30 and the stored data may be lost.

  In this regard, according to the present embodiment, the second semiconductor chip 20 is stacked in an area other than the area of the stack prohibition circuit, and thus such a situation can be prevented. In particular, in the present embodiment, the second semiconductor chip 20 is an elongated chip. Therefore, as shown in FIG. 10, it is easy to dispose the second semiconductor chip 20 while avoiding the areas of the DRAMs 14 and 15, and it is possible to effectively prevent deterioration of circuit reliability and characteristics.

  The area of the stack prohibition circuit is not limited to the area of the DRAMs 14 and 15. For example, it may be an analog circuit area in which reliability and circuit characteristics may be deteriorated due to stack arrangement.

  FIG. 11 shows a detailed arrangement example of each circuit of the second semiconductor chip 20. As shown in FIG. 11, in this embodiment, the physical layer circuit 40 is disposed on the side SB1 side of the second semiconductor chip 20, and the logic circuit 60 is disposed on the side SB3 side. A high speed logic circuit 50 is disposed between the physical layer circuit 40 and the logic circuit 60. In addition, along the sides SB1, SB2, SB3, and SB4 of the second semiconductor chip 20, respectively, pad regions 81, 82, 83, and 84 (first, second, third, and fourth electrode regions in a broad sense, I / O area) is provided. For example, a modification in which the pad regions 83 and 84 are not provided is also possible.

  As shown in FIG. 11, in this embodiment, a CAP region 74 (capacitor forming region) is provided between the logic circuit 60 and the side SB3. In the CAP region 74, a capacitor for stabilizing the power (digital power) supplied to the second semiconductor chip 20 is formed. This capacitor can be formed by utilizing, for example, the gate capacitance of a G / A basic cell constituting the logic circuit 60.

  That is, in FIG. 11, the second semiconductor chip 20 is a long and narrow chip due to restrictions on the design rule of the bonding length. A pad region 81 is provided along the side SB1, and a pad region 83 is provided along the side SB3. Therefore, it is necessary to bond the wiring not only to the pads in the pad region 81 but also to the pads in the pad region 83. As a result, as shown in FIG. 12 to be described later, the length LB of the side SB2 of the second semiconductor chip 20 is set to a length capable of bonding such wiring. When the length LB of the side SB2 becomes longer in this way, an empty area is generated between the logic circuit 60 and the side SB3 (pad area 83).

  Also in this case, in the present embodiment, as shown in FIG. 11, since the CAP area 74 is formed between the logic circuit 60 and the side SB3, the free area can be used effectively. By providing the CAP region 74, the power supplied to the second semiconductor chip 20 can be stabilized, the circuit operation can be stabilized, and the EMI noise can be reduced.

  In FIG. 11, the physical layer circuit 40 includes a data transfer transmitter circuit TX0 and a clock transfer transmitter circuit TCK. The data transfer transmitter circuit TX0 and the clock transfer transmitter circuit TCK are arranged along the side SB1 which is the short side of the second semiconductor chip 20.

  In this embodiment, as described with reference to FIGS. 5 to 6C, as the transmitter circuit for data transfer, transmitter circuits TX0, TX1, and TX2 for channels 1, 2, and 3 (first to second in a broad sense). N transmitter circuits). These transmitter circuits TX0, TX1, TX2 are arranged along the side SB1 of the second semiconductor chip 20.

  Further, in FIG. 11, the clock transfer transmitter circuit TCK is disposed between the transmitter circuit TX0 (first transmitter circuit) and the transmitter circuits TX1 and TX2 (second to Nth transmitter circuits).

  If arranged as shown in FIG. 11, for example, the pads D0M, D0P, CKM, CKP, D1M, D1P, D2M, and D2P for high-speed serial transfer are arranged in the pad area 81 (first electrode area) along the side SB1. In this case, the signal lines from these pads can be connected to the transmitter circuits TX0, TCK, TX1, and TX2 by a short path. Therefore, signal skew and signal delay can be minimized. In addition, it is easy to make the lengths of the first and second signal lines (for example, D0M and D0P) constituting the differential signal line equal, and deterioration of transmission quality can be prevented. In addition, the length of the side SB1 can be minimized, and the second semiconductor chip 20 can be easily formed into an elongated shape.

  In the one-channel mode of FIG. 6A, data is transferred by the transmitter circuit TX0 and a clock is transferred by the transmitter circuit TCK. In FIG. 11, these transmitter circuits TX0 and TCK are arranged adjacent to each other. Therefore, the skew between the data and the clock in the one-channel mode can be minimized, and the occurrence of a sampling error on the receiving side can be prevented.

  6B, data is transferred by the transmitter circuits TX0 and TX1, and a clock is transferred by the transmitter circuit TCK. In FIG. 11, transmitter circuits TX0 and TCK are arranged adjacent to each other, and TX1 and TCK are also arranged adjacent to each other. Therefore, even in the 2-channel mode, the data and clock skew can be minimized, and the occurrence of sampling errors on the receiving side can be prevented.

  6C, data is transferred by the transmitter circuits TX0, TX1, and TX2, and a clock is transferred by the transmitter circuit TCK. In FIG. 11, transmitter circuits TX0 and TCK are arranged adjacent to each other, TX1 and TCK are also arranged adjacent to each other, and TX2 is also arranged near TCK. Therefore, even in the 3-channel mode, the skew between the data and the clock can be minimized, and the occurrence of a sampling error on the receiving side can be prevented.

  In FIG. 11, high-speed serial transfer pads D0M, D0P, CKM, CKP, D1M, D1P, D2M, and D2P for connecting the external device and the high-speed serial I / F circuit 30 are pads along the side SB1. Arranged in region 81. On the other hand, for the interface pads VD [11: 0], PCLK, VS, HS, DE, etc. for connecting the internal circuit 12 including the first semiconductor chip 10 and the high-speed serial I / F circuit 30, the side SB2 Are arranged in a pad region 82 along the side SB3 and a pad region 83 along the side SB3. Accordingly, signal lines from the logic circuit 60 (internal I / F circuit 62) to these pads VD [11: 0], PCLK, VS, HS, and DE can be connected by a short path, and signal skew and Signal delay can be minimized. In addition, since the pads VD [11: 0], PCLK, VS, HS, DE to the wiring pattern of the substrate or the pads (electrodes) of the first semiconductor chip 10 can be bonded by a short path, the mounting is possible. Can be made easier.

  In FIG. 11, a pad of VD [23:12] is arranged in the pad area 84 along the side SB4. In the present embodiment, a first interface mode shown in FIG. 7 and a second interface mode shown in FIG. 8A are prepared. The setting of the first and second interface modes is realized by setting a predetermined voltage level to an XDDR pad or the like arranged in the pad area 84.

  In the present embodiment, when the second semiconductor chip 20 is used as a single general-purpose chip, the first interface mode is set. Then, not only the pads of VD [11: 0] arranged in the pad areas 82 and 83 but also the pads of VD [23:12] arranged in the pad area 84 are bonded to each other as shown in FIG. Data transfer using bits VD [23: 0] is performed. As a result, the second semiconductor chip 20 can be used in a standard 24-bit parallel interface mode, and the versatility of the second semiconductor chip 20 can be enhanced.

  On the other hand, when the second semiconductor chip 20 is stacked on the first semiconductor chip 10, the second interface mode is set. The wiring is not bonded to the pad VD [23:12] arranged in the pad region 84, while the wiring is bonded to the pad of VD [11: 0] arranged in the pad regions 82 and 83, Data transfer is performed using the 12-bit VD [11: 0] of FIG. As a result, the second semiconductor chip 20 is used as a stacking chip, and data transfer can be performed with the internal circuit 12 of the first semiconductor chip 10 using a minimum number of signal lines.

  11 shows the arrangement method of the transmitter circuits TX0, TCK, TX1, and TX2 on the transmission (TX) side, the receiver circuit on the reception (RX) side can be arranged in the same manner as in FIG. For example, it is assumed that the receiver circuit for data transfer on the reception side is RX0, RX1, and RX2, and the receiver circuit for clock transfer on the reception side is RCK. In this case, these receiver circuits RX0, RCK, RX1, and RX2 may be arranged in the same manner as the transmitter circuits TX0, TCK, TX1, and TX2 in FIG. FIG. 11 shows an arrangement example in which the data channel has a multi-channel configuration, but the data channel may have a single-channel configuration.

6). Restriction of Bonding Length When the second semiconductor chip 20 is stacked on the first semiconductor chip 10, the bonding length of the wiring has a restriction on the design rule regarding mounting. In order to reduce the cost, the chip size of the second semiconductor chip 20 is desirably as small as possible. If the chip size is small, the number of pads that can be arranged on the second semiconductor chip 20 is limited. Therefore, how to bond the wiring to the second semiconductor chip 20 while satisfying these restrictions becomes a problem.

  In order to solve such problems, the present embodiment adopts the following method. For example, in FIG. 12, the length of the side SB2 of the second semiconductor chip 20 is LB, and the length of the side SA2 of the first semiconductor chip 10 parallel to the side SB2 is LA. Further, for the wirings 610 and 612 (for example, wirings connected to the wiring patterns 600 and 602 on the substrate) connected to the pads (electrodes) of the second semiconductor chip 20, the end portions of the first semiconductor chip 10 from the pads. Let LM be the maximum length in plan view on the design rule up to (A1, A2 in FIG. 12). In this case, in FIG. 12, the relational expression of LB ≧ LA−2 × LM is established for the length LB of the side SB2, which is the long side of the second semiconductor chip 20. That is, the second semiconductor chip 20 has an elongated shape that satisfies LB ≧ LA−2 × LM.

  Specifically, the second semiconductor chip 20 is based on the arrangement pitch of the transmitter circuits TX0, TCK, TX1, TX2 of the physical layer circuit 40 in FIG. 11, the arrangement pitch of the pads D0M to D2P for high-speed serial transfer, and the like. The length of the side SB1 is determined. Further, the length of the side SB2 of the second semiconductor chip 20 is determined based on the relational expression of LB ≧ LA−2 × LM in FIG. In this way, the chip shape of the second semiconductor chip 20 is determined, and the CAP area 74 of FIG. 11 is arranged in the surplus area.

  According to the method of the present embodiment as described above, the design rule for the maximum length LM of the wirings 610 and 620 can be observed. Further, not only the pad region 81 on the side SB1 side but also the pad region 83 on the side SB3 side is provided, and the wiring can be bonded to the pads in the pad region 83. Accordingly, the number of pads arranged on the second semiconductor chip 20 can be increased, and parallel transfer and transfer of various information to and from the internal circuit 12 of the first semiconductor chip 10 are facilitated.

7). Modified Examples The arrangement method of the first and second semiconductor chips 10 and 20 and the circuits included in the first and second semiconductor chips 10 and 20 is not limited to the method described above, and various modifications can be made. For example, as shown in FIG. 13A, the second semiconductor chip 20 may be stacked so that the corner portion of the internal circuit 12 and the corner portion of the second semiconductor chip 20 coincide. As shown in FIG. 13A, the pad areas 81 and 82 may be provided on the sides SB1 and SB2, while the pad area may not be provided on the sides SB3 and SB4.

  Further, as shown in FIG. 13B, not only the second semiconductor chip 20 but also the third semiconductor chip 21 may be stacked on the first semiconductor chip 10. In this case, for example, a high-speed serial I / F circuit for transmission (TX) is included in the second semiconductor chip 20, and a high-speed serial I / F circuit for reception (RX) is included in the third semiconductor chip 21, for example. Can be included. The pad regions 81 and 82 of the second semiconductor chip 20 and the pad regions 85 and 86 of the third semiconductor chip 21 are connected to the pads of the second semiconductor chip 20 and the pads of the third semiconductor chip 21. What is necessary is just to arrange | position in the position which wiring does not mutually cross. Instead of providing the third semiconductor chip 21, a high-speed serial I / F circuit that can perform both transmission and reception may be provided in the second semiconductor chip 20.

  Further, the high-speed serial transfer method of the present embodiment is not limited to the method described in the present embodiment, and various methods as shown in FIGS. 14A and 14B and FIG. 15 can be employed, for example.

  For example, FIGS. 14A and 14B are examples of the high-speed serial transfer method of the MDDI standard. In FIG. 14A, the physical layer circuit 340 (transceiver) is built in the host device, and the physical layer circuit 330 is built in the display driver. Reference numerals 336, 342, and 344 denote transmitter circuits, and reference numerals 332, 334, and 346 denote receiver circuits. Reference numerals 338 and 348 denote wake-up detection circuits. The host-side transmitter circuit 342 drives the differential strobe signal STB +/−. The client-side receiver circuit 332 amplifies the voltage generated at both ends of the resistor RT1 by driving, and outputs the strobe signal STB_C to the subsequent circuit. The host-side transmitter circuit 344 drives the data signal DATA +/−. The client-side receiver circuit 334 amplifies the voltage generated at both ends of the resistor RT2 by driving, and outputs the data signal DATA_C_HC to the subsequent circuit.

  As shown in FIG. 14B, the transmission side generates a strobe signal STB by taking the exclusive OR of the data signal DATA and the clock signal CLK, and transmits this STB to the reception side via the high-speed serial bus. To do. Then, the reception side reproduces the clock signal CLK by taking an exclusive OR of the received data signal DATA and the strobe signal STB.

  In the high-speed serial transfer method of FIG. 15, DTO + and DTO− are differential data signals (OUT data) output from the host-side transmitter circuit 442 to the target-side receiver circuit 432. CLK + and CLK− are differential clock signals output from the transmitter circuit 444 on the host side to the receiver circuit 434 on the target side. The host side outputs DTO +/− in synchronization with the edge of CLK +/−. Therefore, the target side can sample and capture DTO +/− using CLK +/−. Further, in FIG. 15, the target side operates based on the clock CLK +/− supplied from the host side. That is, CLK +/− becomes the system clock on the target side. Therefore, the PLL circuit 449 is provided on the host side and is not provided on the target side.

  DTI + and DTI− are differential data signals (IN data) output from the target-side transmitter circuit 436 to the host-side receiver circuit 446. STB + and STB− are differential strobe signals output from the target-side transmitter circuit 438 to the host-side receiver circuit 448. The target side generates and outputs STB +/− based on CLK +/− supplied from the host side. The target side outputs DTI +/− in synchronization with the edge of STB +/−. Therefore, the host side can sample and capture DTI +/− using STB +/−.

8). Electronic Equipment FIGS. 16A, 16B, and 16C show configuration examples of electronic equipment including the semiconductor device (integrated circuit device) of this embodiment.

For example, in FIG. 16A, the electronic device includes a BBE / APP (BaseBand Engine / Application Processor) 600, semiconductor devices 610 and 620, and a display panel 630. The semiconductor device 610 includes an image processing controller 612 and a high-speed serial I / F circuit 614. Here, the image processing controller 612 is included in the first semiconductor chip, and the high-speed serial I / F circuit 614 is included in the second semiconductor chip stacked on the first semiconductor chip. The semiconductor device 620 includes a high-speed serial I / F circuit 622 and a display driver 624. The display driver 624 is included in the first semiconductor chip, and the high-speed serial I / F circuit 622 is included in the second semiconductor chip.

  The image processing controller 612 functions as a graphic engine for image processing, and performs processing such as compression, expansion, and sizing of images (still images and moving images). The display driver 624 drives data lines and scanning lines of the display panel 630. The display panel 630 performs a display operation based on data serially transferred by the semiconductor devices 610 and 620. As the display panel 630, for example, an active matrix panel using a switching element (two-terminal nonlinear element) such as a thin film transistor (TFT) or a thin film diode (TFD) can be used. Alternatively, as the display panel 630, a simple matrix panel or a panel other than a liquid crystal panel (for example, an organic EL panel) may be employed.

  The BBE / APP 600 and the semiconductor device 610 are mounted on the first circuit board of the first device portion of the electronic device (for example, a mobile phone), and the semiconductor device 620 and the display panel 630 are the second device portion of the electronic device. 2 is mounted on the circuit board. In addition, data is transferred between the first and second device parts by high-speed serial transfer via a serial bus. Therefore, it is possible to reduce the number of signal lines that pass through the connection portions (such as hinges) of the first and second device portions.

  In FIG. 16B, the electronic device includes semiconductor devices 610 and 620 and a display panel 630. The semiconductor device 610 includes a BBE / APP 600 and a high-speed serial I / F circuit 614. The BBE / APP 600 is included in the first semiconductor chip, and the high-speed serial I / F circuit 614 is included in the second semiconductor chip. The semiconductor device 620 includes a high-speed serial I / F circuit 622 and a display driver 624. The display driver 624 is included in the first semiconductor chip, and the high-speed serial I / F circuit 622 is included in the second semiconductor chip. In FIG. 16B, unlike FIG. 16A, the image processing controller 612 that functions as a coprocessor of the BBE / APP 600 is not provided.

  In FIG. 16C, the electronic device includes a BBE / APP 600, semiconductor devices 610 and 620, a display panel 630, and a camera device 632. The semiconductor device 610 includes an image processing controller 612, a high-speed serial I / F circuit 614 for transmission, and a high-speed serial I / F circuit 616 for reception. Here, the image processing controller 612 is included in the first semiconductor chip, and the high-speed serial I / F circuits 614 and 616 are included in the second and third semiconductor chips stacked on the first semiconductor chip. Note that the high-speed serial I / F circuits 614 and 616 may be included in the second semiconductor chip without providing the third semiconductor chip. The semiconductor device 620 includes a high-speed serial I / F circuit 622 and a display driver 624. The display driver 624 is included in the first semiconductor chip, and the high-speed serial I / F circuit 622 is included in the second semiconductor chip. The camera device 632 is connected to the high-speed serial I / F circuit 616 via a serial bus. With the configuration in FIG. 16C, not only display data displayed on the display panel 630 but also photographing data by the camera device 632 can be serially transferred via the serial bus.

  The electronic device of the present embodiment is not limited to a mobile phone, and may be a digital camera, PDA, electronic notebook, electronic dictionary, projector, rear projection television, or portable information terminal.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are included in the scope of the present invention. For example, in the specification or drawings, at least once, together with different terms having a broader meaning or the same meaning (serial interface circuit, first logic circuit, second logic circuit, electrode, electrode region, transmitter circuit TX0, TX1, TX2, etc.) The described terms (high-speed serial I / F circuit, high-speed logic circuit, logic circuit, pad, pad area, first to Nth transmitter circuits, etc.) are different from each other in the specification or drawings. Can be replaced.

  Further, the configuration and arrangement of the first and second semiconductor chips and the serial interface circuit are not limited to the configuration and arrangement described in the present embodiment. For example, the second semiconductor chip may be arranged at a position different from that in FIG. 1B, or each circuit or electrode region of the serial interface circuit may be arranged at a position different from that in FIGS. Good. Also, the serial transfer method using a serial bus is not limited to the method described in the present embodiment. For example, a configuration without a clock transfer transmitter circuit or receiver circuit or a clock transfer transmitter circuit or receiver circuit may be used. A type of circuit that does not use a dynamic signal may be used.

1A and 1B are explanatory diagrams of a serial transfer method and a stack arrangement method according to this embodiment. FIG. 3 is a schematic cross-sectional view of a stack structure of first and second semiconductor chips. FIGS. 3A, 3B, and 3C are explanatory diagrams of a method for arranging pads and pad regions. 4A and 4B show a configuration and an arrangement example of a high-speed serial I / F circuit. 3 shows a detailed configuration example of a high speed serial I / F circuit. 6A, 6B, and 6C are explanatory diagrams of various channel modes. Explanatory drawing of a 1st interface mode. 8A and 8B are explanatory diagrams of the second interface mode. 2 shows a configuration example of an internal I / F circuit. 3 shows a detailed arrangement example of first and second semiconductor chips. 4 shows a detailed arrangement example of each circuit of a second semiconductor chip. Explanatory drawing about restrictions of bonding length. FIGS. 13A and 13B are modifications of this embodiment. 14A and 14B show an example of a serial transfer method. Another example of serial transfer technique. 16A, 16B, and 16C are configuration examples of electronic devices.

Explanation of symbols

TX0, TX1, TX2 Transmitter circuit for data transfer,
Transmitter circuit for TCK clock transfer,
2, 4 semiconductor device, 6, 8 high-speed serial I / F circuit, 10 first semiconductor chip,
12 internal circuit, 20 second semiconductor chip, 21 third semiconductor chip,
30 high-speed serial I / F circuit, 40 physical layer circuit, 42 transmitter circuit,
44 Transmitter circuit for data transfer, 46 Transmitter circuit for clock transfer,
50 high-speed logic circuit, 52 parallel / serial conversion circuit, 60 logic circuit,
62 internal I / F circuit, 64 parity generation circuit, 66 data separator,
68 registers, 70 bias circuit, 72 PLL circuit,
81, 82, 83, 84 Pad (electrode) region

Claims (14)

A first semiconductor chip;
A serial interface circuit for transferring serial data to and from an external device via a serial bus, and a second semiconductor chip stacked on the first semiconductor chip,
A first electrode region in which an electrode for connecting the external device and the serial interface circuit is disposed is provided along a first side which is a short side of the second semiconductor chip,
A second electrode region in which an electrode for connecting an internal circuit included in the first semiconductor chip and the serial interface circuit is disposed along a second side which is a long side of the second semiconductor chip Is provided,
The serial interface circuit
A physical layer circuit that performs at least one of transmission and reception of data to and from the external device via a serial bus;
The physical layer circuit is:
A transmitter circuit or receiver circuit for data transfer; and
Including a transmitter or receiver circuit for clock transfer,
The data transfer transmitter circuit or receiver circuit and the clock transfer transmitter circuit or receiver circuit are arranged along a first side which is a short side of the second semiconductor chip. Semiconductor device. In claim 1,
The physical layer circuit is:
Including first to Nth transmitter circuits or receiver circuits for data transfer of the first to Nth channels;
The semiconductor device, wherein the first to Nth transmitter circuits or receiver circuits for data transfer are arranged along the first side of the second semiconductor chip. In claim 2,
The transmitter circuit or receiver circuit for clock transfer is disposed between the first transmitter circuit or receiver circuit for data transfer and the second to Nth transmitter circuits or receiver circuits for data transfer. A semiconductor device. In any one of Claims 1 thru | or 3,
An electrode for connecting an internal circuit included in the first semiconductor chip and the serial interface circuit is disposed along a third side opposite to the first side of the second semiconductor chip. A semiconductor device comprising three electrode regions. In any one of Claims 1 thru | or 4,
An electrode for serial data for serial transfer is disposed in the first electrode region. In claim 5,
The semiconductor device according to claim 1, wherein an electrode for serial data for serial transfer and an electrode for clock for serial transfer are arranged in the first electrode region. In any one of Claims 1 thru | or 6.
The serial interface circuit
A physical layer circuit that transmits and receives data to and from the external device via a serial bus; and
A parallel / serial conversion circuit for converting parallel data from an internal circuit included in the first semiconductor chip into serial data; and a serial / parallel conversion circuit for converting serial data from the external device into parallel data. A first logic circuit;
And a second logic circuit having an internal interface circuit for transferring parallel data to and from an internal circuit included in the first semiconductor chip. In claim 7,
The physical layer circuit is:
Arranged on the first side which is the short side of the second semiconductor chip;
The second logic circuit includes:
A semiconductor device, wherein the semiconductor device is disposed on a third side facing the first side of the second semiconductor chip. In any one of Claims 1 thru | or 8.
The serial interface circuit
An internal interface circuit for transferring parallel data to and from an internal circuit included in the first semiconductor chip;
The internal interface circuit is
In the first interface mode, K-bit parallel data is transferred to and from an internal circuit included in the first semiconductor chip,
In the second interface mode that is set when the second semiconductor chip is stacked on the first semiconductor chip, J bits (J <K) with the internal circuit included in the first semiconductor chip are provided. A semiconductor device for transferring parallel data. In claim 9,
J-bit parallel data electrodes are disposed along the second side, which is the long side of the second semiconductor chip,
A semiconductor device, wherein an electrode for parallel data of KJ bits is arranged along a fourth side opposite to the second side of the second semiconductor chip. In claim 9 or 10,
The internal interface circuit is
In the first interface mode, parallel data is sampled on one of the rising edge and falling edge of the parallel data sampling clock;
In the second interface mode, the parallel data is sampled at both the rising edge and the falling edge of the sampling clock. In any one of Claims 1 thru | or 11,
The first semiconductor chip includes a stack prohibiting circuit in which stack placement is prohibited,
The semiconductor device according to claim 1, wherein the second semiconductor chip is stacked in a region other than the region of the stack prohibition circuit. In claim 12,
The semiconductor device according to claim 1, wherein the stack prohibition circuit is a DRAM. A semiconductor device according to any one of claims 1 to 13,
A display panel that performs a display operation based on data serially transferred by the semiconductor device;
An electronic device comprising:

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