JP2007305021A - Semiconductor storage device and its reading method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device using an FIFO buffer and capable of efficiently reading a plurality of continuous data by means of a CPU or a DMA controller. <P>SOLUTION: When higher n-bits in an m-bit address signal output from a data processor 2 such as a CPU match a value preset in a register 12A, a match detection signal EQ is output from a comparator 13A. When a read request signal RQ is output from the data processor 2, a read control signal RE is output from an AND 14 to the FIFO buffer 11 and the oldest data is read as read data RD. Since the data can be read from the FIFO buffer 11 even if all the bits of the address signal AD do not match, a plurality of continuous data can be read from a CPU or a DMA controller. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device for a buffer provided between a data generation device and a data processing device, and more particularly to an access control technique from the data processing device.

FIG. 2 is a configuration diagram of a conventional semiconductor memory device.
The semiconductor memory device 10 is provided between the data generation device 1 and a data processing device 2 such as a CPU (central processing unit), and the data output timing on the data generation device 1 side and the data input timing on the data processing device 2 side. And a FIFO (first in first out) buffer 11 is used. The FIFO buffer 11 is a memory having a fixed storage capacity, and is configured to read out the written data in order from the oldest data. Writing and reading data without specifying an address from the outside Is something that can be done.

  That is, when the write control signal WE is given from the data generation device 1, the FIFO buffer 11 reads the write data WD given from this data generation device 1 and stores it in the memory. Further, when the read control signal RE is given, the FIFO buffer 11 outputs the oldest data among the data stored in the memory as read data RD. The area where the read data is stored is opened as a storage area for newly given data.

  On the other hand, the data processing device 2 such as a CPU specifies not only the data from the data generation device 1 but also other devices, circuits, and memories such as RAM and ROM in order to specify the access target. Address space. Therefore, the data processing device 2 is configured to output an m-bit address signal AD and a read request signal RQ that designate an access target, and to input read data RD.

  In order to cope with such a data processing device 2, the semiconductor memory device 10 has an m-bit register (REG) 12 that stores an address assigned by the data processing device 2. The m-bit address information of the register 12 is given to one input side of the comparator (CMP) 13, and the m-bit address signal AD is given from the data processor 2 to the other input side of the comparator 13. ing. The comparator 13 compares the address information supplied from the register 12 with the address signal AD supplied from the data processing device 2 for each bit, and outputs a coincidence detection signal EQ (outputs level “H”) when all bits match. ) If even one bit is different, the comparator 13 does not output the coincidence detection signal EQ (that is, outputs a level “L”).

  The output side of the comparator 13 is connected to one input side of a 2-input AND (logical product gate) 14, and a read request signal RQ is given from the data processing device 2 to the other input side of the AND 14. . A read control signal RE output from the AND 14 is supplied to the FIFO buffer 11.

Next, the operation will be described.
First, the data processing device 2 assigns an address to the semiconductor memory device 10, and the assigned address is set in the register 12.

  Data generated by the data generation device 1 is given to the FIFO buffer 11 as write data WD, and is stored in the memory of the FIFO buffer 11 in accordance with a write control signal WE given together with the write data WD.

  On the other hand, when reading the data stored in the FIFO buffer 12, the data processing device 2 outputs the address assigned to the semiconductor memory device 10 as the address signal AD and also outputs the read request signal RQ. The address signal AD output from the data processing device 2 is supplied to the comparator 13 and compared with the address of the semiconductor memory device 10 set in the register 12.

  When the address signal AD matches the address of the semiconductor memory device 10, the match detection signal EQ output from the comparator 13 becomes “H”. At this time, since the read request signal RQ output from the data processing device 2 is “H”, the read control signal RE that is an output signal of the AND 14 is also “H”. As a result, the oldest data is read from the FIFO buffer 11 and output to the data processing device 2 as read data RD.

  On the other hand, if the address signal AD does not match the address of the semiconductor memory device 10, the match detection signal EQ output from the comparator 13 becomes “L”, the read control signal RE also becomes “L”, and the FIFO buffer 11 data is not read.

JP 2004-252705 A JP 2000-276358 A

  However, the semiconductor memory device 10 has the following problems because it is necessary to always designate one fixed address when performing read / write access.

(1) For example, in a RISC (reduced instruction set computer) type CPU called ARM (AdvancedRISCMachines) (registered trademark) of ARM Co., Ltd. described in Patent Document 2, “LDR instruction” and “ LDM instruction ". The “LDR instruction” reads out one data with one instruction, and the “LDM instruction” reads out data at a plurality of consecutive addresses with one instruction. Therefore, when reading four pieces of data continuously from the semiconductor memory device 10, it is necessary to issue the same instruction four times when the “LDR instruction” is used. On the other hand, if the “LDM instruction” is used, only one instruction is required. In this case, the address signal AD is automatically increased by one every time data is read. For this reason, the first data can be read correctly, but the second and subsequent data have addresses that do not match, and cannot be read from the semiconductor memory device 10. Therefore, the “LDM instruction” cannot be used for the semiconductor memory device 10, and continuous data cannot be read efficiently.

(2) A DMA (dynamic memory access) controller can also access data at a plurality of consecutive addresses with one transfer instruction. However, for this semiconductor memory device 10, (1) For the same reason, only one data can be read with one instruction, and the performance of the DMA controller cannot be used up.

  An object of the present invention is to provide a semiconductor memory device using a FIFO buffer that can efficiently read a plurality of continuous data by a CPU or a DMA controller, and a reading method thereof.

  A semiconductor memory device according to the present invention stores write data given in accordance with a write control signal, and reads and outputs the stored data in a predetermined order when a read control signal is given, and a data processing device Matches when the upper n bits (where n is an integer smaller than m) of the m-bit (where m is a plurality) address signals output from the side match a preset n-bit value A comparison unit that outputs a detection signal; and a read that provides the read control signal to the buffer memory when the coincidence detection signal is output from the comparison unit and a read request signal is output from the data processing device side And a control means.

  In the present invention, the comparison means for outputting a coincidence detection signal when the upper bits of the address signal output from the data processor side such as a CPU or DMA controller coincide with a preset value, and coincidence detection Read control means for outputting a read control signal to the buffer memory when a signal and a read request signal are given. As a result, data can be read from the buffer memory even if all the bits of the address signal do not match, so that a plurality of continuous data can be read efficiently from the CPU or DMA controller.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

  FIG. 1 is a configuration diagram of a semiconductor memory device showing an embodiment of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.

  Similar to the semiconductor memory device 10 of FIG. 2, the semiconductor memory device 10A is provided between the data generation device 1 and the data processing device 2 such as a CPU, and the data output timing and data processing device on the data generation device 1 side. It is used as a buffer for absorbing differences in data input timing on the two sides.

  This semiconductor memory device 10A has a FIFO buffer 11 as a memory element. The FIFO buffer 11 is a memory having a certain storage capacity. When a write control signal WE is given from the data generation device 1, the FIFO buffer 11 reads the write data WD given from the data generation device 1 and stores it in the memory. When the read control signal RE is given, the oldest data among the data stored in the memory is output to the data processing device 2 as read data RD. The area where the read data is stored is opened as a storage area for newly given data.

  On the other hand, the data processing device 2 is supplied with an m-bit address signal AD and a read request signal RQ for designating a read / write access target.

  The semiconductor memory device 10A includes an n-bit register 12A that stores upper n bits (that is, n <m) of m-bit (m is a plurality) addresses allocated from the data processing device 2. The n-bit address information stored in the register 12A is given to one input side of the comparator 13A as a comparison means, and the other input side of the comparator 13A has m bits output from the data processing device 2. The upper n bits of the address signal AD are provided.

  The comparator 13A compares the n-bit address information supplied from the register 12A with the upper n bits of the address signal AD supplied from the data processing device 2 for each corresponding bit, and matches when all n bits match. The detection signal EQ is set to “H” and output. If even one bit is different, the comparator 13A stops the output of the coincidence detection signal EQ and makes it "L".

  The output side of the comparator 13A is connected to one input side of a two-input AND 14 that is a read control means, and a read request signal RQ is given from the data processing device 2 to the other input side of the AND 14. . A read control signal RE is output from the output side of the AND 14 and is supplied to the FIFO buffer 11.

Next, the operation will be described. Here, description will be made assuming that m = 16 and n = 12.
First, the data processing device 2 assigns an address for the semiconductor memory device 10A, for example, H0100 (where H indicates that the following number is a hexadecimal number). Thereby, the upper 12 bits of the address H0100, that is, H010 is set in the register 12A of the semiconductor memory device 10A.

  Data generated by the data generation device 1 is given to the FIFO buffer 11 as write data WD, and is sequentially stored in the memory of the FIFO buffer 11 in accordance with the write control signal WE given together with the write data WD.

  On the other hand, when data stored in the FIFO buffer 12 is read, the data processing device 2 outputs an address (that is, H0100) assigned to the semiconductor memory device 10A as an address signal AD and also outputs a read request signal RQ. The upper 12 bits of the address signal AD output from the data processing device 2 are supplied to the comparator 13A and compared with the upper 12 bits of the address of the semiconductor memory device 10A set in the register 12A.

  Therefore, the comparator 13A compares H010, which is the upper 12 bits of the address signal AD, with H010 set in the register 12A. Since the two values match, the match detection signal EQ output from the comparator 13A becomes “H”. At this time, since the read request signal RQ output from the data processing device 2 is “H”, the read control signal RE that is an output signal of the AND 14 is also “H”. As a result, the oldest data is read from the FIFO buffer 11 and output to the data processing device 2 as read data RD.

  Next, in order to read data at consecutive addresses from the data processing device 2, the address signal AD increases by 1 to H0101, but since the address signal given to the comparator 13A is the upper 12 bits, its value is H010. Accordingly, the coincidence detection signal EQ output from the comparator 13A remains “H”, and the next data is read from the FIFO buffer 11 by the read control signal RE.

  Thus, while the upper 12 bits of the address signal AD output from the data processing device 2 are H010, that is, while the address signal AD is H0100 to H010F, the coincidence detection signal EQ becomes “H”, and the FIFO buffer A plurality of data can be read continuously from 11.

  On the other hand, if the upper 12 bits of the address signal AD do not match the upper 12 bits of the address specified in the semiconductor memory device 10A, the coincidence detection signal EQ output from the comparator 13A becomes “L”, and the read control signal RE also becomes “L” and data in the FIFO buffer 11 is not read.

  As described above, the semiconductor memory device 10A according to the present embodiment compares only the upper n digits of the m-digit address signal AD given from the data processing device 2 with the value set in the register 12. Thus, the data is read from the FIFO buffer 11 when they match. Thereby, when a read request is made by designating a continuous address from the data processing device 2 such as a CPU or a DMA controller, there is an advantage that a plurality of continuous data can be efficiently read corresponding to this. is there.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) Not only the FIFO buffer 11 but also a FILO (first-in last-out) buffer that reads data written earlier and a LILO (last-in last-out) buffer that reads data written later can do.
(B) The case where the data processing device 2 outputs continuous addresses and reads data has been described. However, when the data generation device 1 outputs continuous addresses and writes data to the FIFO buffer 11, the register 12A The comparator 13A and the AND 14 can be provided as write control means on the write control signal WE side of the FIFO buffer 11.
(C) It is not necessary to set an address for the register 12A from the data processing device 2. Instead of the register 12A, a dip switch or the like may be used for manual operation.

1 is a configuration diagram of a semiconductor memory device showing an embodiment of the present invention. It is a block diagram of the conventional semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data generator 2 Data processing apparatus 10A Semiconductor memory device 11 FIFO buffer 12A Register 13A Comparator 14 AND

Claims (4)

A buffer memory for storing write data given in accordance with a write control signal, and reading and outputting the stored data in a predetermined order when a read control signal is given;
The upper n bits (where n is an integer smaller than m) of the m-bit (where m is a plurality) address signals output from the data processor side match the preset n-bit value. A comparison means that sometimes outputs a coincidence detection signal;
Read control means for providing the read control signal to the buffer memory when the coincidence detection signal is output from the comparison means and a read request signal is output from the data processing device side,
A semiconductor memory device comprising: A buffer memory for storing write data given in accordance with a write control signal, and reading and outputting the stored data in a predetermined order when a read control signal is given;
The upper n bits (where n is an integer smaller than m) of the m-bit (where m is a plurality) address signals output from the data generation device side match a preset n-bit value. A comparison means that sometimes outputs a coincidence detection signal;
Write control means for supplying the write control signal to the buffer memory when the coincidence detection signal is output from the comparison means and a write request signal is output from the data generation device side;
A semiconductor memory device comprising:   3. The buffer memory is a first-in first-out buffer that sequentially reads from the previously written data among the stored data when the read control signal is given. Semiconductor memory device. A read method for a semiconductor memory device that stores write data given in accordance with a write control signal and reads and outputs the stored data in a predetermined order when a read control signal is given,
Comparison that compares the upper n bits (where n is an integer smaller than m) of the m-bit (where m is a plurality) address signals output from the data processor side with a preset n-bit value Processing,
A read process for reading data from the semiconductor memory device by providing the read control signal to the semiconductor memory device when a match is detected by the comparison process and a read request signal is output from the data processor side; The
A reading method for a semiconductor memory device, comprising:

Images