JP2007299913A - Thin film transistor, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor which is excellent in stability, is high in mobility and suitable for a pixel portion and a drive portion of a flexible display. <P>SOLUTION: In a thin film transistor device, wherein a gate electrode is included on an insulating substrate, a drain electrode and a source electrode are arranged on a gate insulating film formed on these, and an oxide semiconductor pattern is arranged so that it may include a gap between the source electrode and the drain electrode, a sealing layer is included on the oxide semiconductor pattern. The sealing layer is an inorganic insulating film, for example it is oxidized silicon nitride or fluorinated resin. Moreover, the sealing layer is not included at least on a pixel electrode. Furthermore, an interlayer dielectric having an opening at a pixel electrode portion is included on the sealing layer, and an upper pixel electrode connected with the pixel electrode at the opening is included on the interlayer dielectric. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a thin film transistor used in various image display devices and the like and a method for manufacturing the same, and further relates to a display using the thin film transistor.

  Conventionally, thin film transistors (TFTs) of amorphous silicon (a-Si) or polysilicon (poly-Si) are manufactured on a glass substrate on the basis of transistors and integrated circuit technology using the semiconductor itself as a substrate. It is applied to displays and electronic paper.

In recent years, organic semiconductors and oxide semiconductors have appeared (for example, see Non-Patent Document 1), and it has been shown that TFTs can be manufactured at a low temperature of 200 ° C. or lower, and expectations for flexible displays using plastic substrates are increasing. . In particular, since an oxide semiconductor has a high mobility of about 10 cm ² / Vs, a high-performance TFT like poly-Si is expected. That is, it is expected that not only the TFT in the pixel but also the peripheral driving logic circuit is made of the oxide TFT.
K. Nomura et al., Nature, 432, 488 (2004)

  However, as a result of trial manufacture of the oxide TFT, when the oxide semiconductor was in contact with a general non-fluorinated resin (epoxy, acrylic, etc.), a phenomenon that the threshold value of the TFT was shifted by about −30V was observed.

This phenomenon is a problem whether a thin film transistor is used as a logic circuit or a display. For example, when used as a logic circuit, it is normally embedded with an epoxy resin. However, when an oxide semiconductor is in contact with the epoxy, the characteristics of the TFT change and normal logic operation is not performed.
Also, when used as a display and when an interlayer insulating film and an upper pixel electrode are provided, the characteristics of the TFT change due to the oxide semiconductor coming into contact with a resin such as epoxy or acrylic that is usually used as the interlayer insulating film. Will do. Alternatively, in the case of using as a display and without using an interlayer insulating film, the characteristics of the TFT change by contacting the liquid crystal in the liquid crystal display and contacting the adhesive in the electronic paper. In either case, an abnormality occurs on the display.

  In view of the above circumstances, an object of the present invention is to provide an oxide thin film transistor having a small characteristic change. It is another object of the present invention to provide a pixel thin film transistor and a driving thin film transistor logic circuit suitable for a flexible display.

  In order to achieve the above object, the thin film transistor of the present invention includes a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, a drain electrode disposed on the gate insulating film, A thin film transistor having an oxide semiconductor pattern disposed at least in a gap portion between the drain electrode and the source electrode, wherein a sealing layer is provided on the oxide semiconductor pattern . By providing the sealing layer, the influence on the oxide semiconductor can be suppressed even when a normal non-fluorinated resin is in contact therewith. Specifically, if the threshold shift of the thin film transistor is within ± 5 V before and after applying the non-fluorinated resin thereon, it can be considered that the influence on the oxide semiconductor is small.

The sealing layer is an inorganic insulating film. That is, an inorganic insulating film can be used as a sealing layer that does not affect the oxide semiconductor. The sealing layer is silicon oxynitride. Among inorganic insulating films, silicon oxynitride can easily obtain a film having good insulation and sealing performance.
2. The thin film transistor according to claim 1, wherein the sealing layer is a fluorinated resin. A fluorinated resin can be used as a sealing layer which does not affect the oxide semiconductor.

In addition, a gate wiring connected to the gate electrode, a capacitor electrode, and a capacitor wiring connected to the capacitor electrode are provided in the same layer as the gate electrode, and connected to the drain electrode in the same layer as the drain electrode and the source electrode. The pixel electrode is connected to the drain wiring and the source electrode, and at least the pixel electrode does not have a sealing layer. With such a structure, the pixel electrode serves to apply a voltage to the liquid crystal layer, and can be used as a TFT for a flexible display.
In addition, a gate wiring connected to the gate electrode, a capacitor electrode, and a capacitor wiring connected to the capacitor electrode are provided in the same layer as the gate electrode, and connected to the drain electrode in the same layer as the drain electrode and the source electrode. And a drain electrode and a pixel electrode connected to the source electrode, a sealing layer at least on the oxide semiconductor pattern, and an interlayer insulating film having an opening in the pixel electrode portion on the sealing layer. And an upper pixel electrode connected to the pixel electrode through the opening on the interlayer insulating film. With such a structure, the upper pixel electrode serves to apply a voltage to the liquid crystal layer, and can be used as a flexible display TFT.

  In addition, by using a thin film transistor display using the above thin film transistor, a flexible display with stable characteristics can be realized.

  The method of manufacturing a thin film transistor of the present invention includes a step of forming a gate electrode on an insulating substrate, a step of forming a resist pattern on a gate insulating film opening planned portion, and a step of forming a gate insulating film and an oxide semiconductor. Removing the resist in the gate insulating film planned opening to form an opening in the gate insulating film; patterning the oxide semiconductor before or after forming the opening; and forming a drain electrode and a source electrode And a step of forming a sealing layer before or after the formation of the drain electrode and the source electrode, and when patterning the oxide semiconductor, by not etching the vicinity of the opening of the gate insulating film, The gate electrode in the opening is not exposed to the etchant. Thereby, the selection range of the gate electrode material can be widened.

The thin film transistor manufacturing method of the present invention includes a step of forming a gate electrode on an insulating substrate, a step of forming a gate insulating film, a step of forming an oxide semiconductor pattern, and a step of forming a drain electrode and a source electrode. And a step of forming a sealing layer before or after the formation of the drain electrode and the source electrode, and the step of forming the sealing layer is reactive sputtering. By using reactive sputtering in the sealing layer process, a film having good performance can be obtained with high reproducibility by a simple method.
Further, the step of forming the sealing layer is reactive sputtering with a SiN sintered body as a target. By this method, a sealing film with good performance can be obtained with good reproducibility.

  Further, the thin film transistor manufacturing method of the present invention includes a step of forming a gate electrode, a gate wiring, a capacitor electrode, and a capacitor wiring on an insulating substrate, a step of forming a gate insulating film, and a step of forming an oxide semiconductor pattern. Forming a drain electrode, a drain wiring, a source electrode, and a pixel electrode, forming a sealing layer before or after forming the drain electrode, the drain wiring, the source electrode, and the pixel electrode, and an interlayer insulating film And a step of forming an upper pixel electrode, and the step of forming the upper pixel electrode is screen printing. By using screen printing in the process of the upper pixel electrode, a thin film transistor can be manufactured by a simple process.

According to the thin film transistor of the present invention, by providing the sealing layer on the oxide semiconductor pattern, a change in TFT characteristics can be suppressed even when a normal non-fluorinated resin is applied thereon. Therefore, according to such a display using thin film transistors, high-quality image display can be performed by stabilizing TFT characteristics.
According to the method for manufacturing a thin film transistor of the present invention, the etching of the gate electrode can be suppressed by leaving the resist also in the opening of the gate insulating film at the time of etching the oxide semiconductor. Alternatively, a sealing film with good characteristics can be obtained by producing the sealing layer by reactive sputtering. Furthermore, the upper pixel electrode can be easily manufactured by screen printing.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
Examples of the thin film transistor according to the first embodiment of the present invention are shown in FIGS.
FIG. 1 is a plan layout view showing an inverter made of a thin film transistor according to a first example of the present embodiment, and a cross-sectional view taken along line AA ′.
FIG. 2 is a plan layout view showing an inverter manufactured using the thin film transistor according to the second example of the present embodiment, and a cross-sectional view taken along the line BB ′.
Further, FIG. 3 shows a plan layout showing an inverter made of the thin film transistor according to the third example of the present embodiment, and a cross-sectional view taken along the line CC ′.

As shown in FIGS. 1 to 3, in the thin film transistor according to the first embodiment of the present invention, the gate electrode 2 is provided on the insulating substrate 1, and the gate insulating film 3 having the opening 3A and the oxide semiconductor pattern are provided. 6 and a drain electrode 5 and a source electrode 4 are further provided. At least a portion of the upper surface of the semiconductor layer 6 that is not covered with the source electrode 4 and the drain electrode 5 is covered with the sealing layer 9.
In FIG. 1, a sealing layer 9 is provided so as to cover the semiconductor layer 6 after the source electrode 4 and the drain electrode 5 are attached. In FIG. 2, after the sealing layer 9 is attached so as to cover the channel portion of the semiconductor layer 6, the source electrode 4 and the drain electrode 5 are connected to portions not attached to the sealing layer 9. Further, in FIG. 3, not only the channel portion of the semiconductor layer 6 is covered, but also the connection portion between the source electrode 4 and the drain electrode 5 and the connection portion 3 </ b> A with the gate electrode are all covered with the sealing layer 9. In FIG. 3 and FIG. 9 and subsequent figures, reference numeral 9A denotes a sealing layer opening provided in the sealing layer 9.

  An example of the manufacturing method is shown in FIGS. As the insulating substrate 1, a rigid substrate such as glass can be used. However, since the process temperature is as low as 200 ° C. or less, a flexible plastic substrate can be used. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE) Polypropylene (PP), nylon (Ny), etc. are used.

  As the gate electrode 2, an arbitrary conductive film such as a metal such as Mo, Cr, Au, Ag, Cu, Ni, Al, or Ti, or a transparent conductive film such as ITO can be used. For patterning, a normal photolithography + etching method can be used, but other methods such as a printing method may be used.

As the gate insulating film 3, an inorganic insulating film such as SiON, SiO _x , SiN, Al ₂ O ₃ , Y ₂ O ₃ or the like can be used. As a method for opening the opening 3A, a lift-off method is preferable in which a resist pattern 3AR is formed in advance on a planned opening and the upper film is removed together with the resist pattern 3AR after the gate insulating film 3 is formed. Other methods such as photolithography + etching may be used.
As the oxide semiconductor pattern 6, InGaZnO, InGaSnO, ZnGaO, GaSnO, or the like can be used. As a patterning method of the oxide semiconductor, a photolithography + etching method is preferable, but other methods such as a printing method may be used.

What is important is that the resist is left in the opening 3A so that the gate electrode 2 in the gate insulating film opening 3A is not exposed to the etchant of the oxide semiconductor during the patterning of the oxide semiconductor. .
Specifically, for example, there are the following methods. For example, after a resist pattern 3AR is formed in the gate opening planned portion (FIG. 10 to FIG. 12A), the gate insulating film 3 and the oxide semiconductor layer 6L are continuously formed (FIG. 10B to FIG. 12B). )), The resist 3AR is lifted off to form the opening 3A (FIGS. 10 to 12C), another resist is applied on the entire surface, and the resist pattern 6R is left in the opening simultaneously with the semiconductor pattern. Every time (FIG. 10 to FIG. 12D), the oxide semiconductor is etched (FIG. 10 to FIG. 12E).
Alternatively, a resist pattern 3AR is formed in the gate opening planned portion, and after the gate insulating film 2 and the oxide semiconductor layer 6L are continuously formed, another resist is applied to the entire surface without lifting off the resist 3AR, for semiconductor processing. A pattern 6R is formed (the original resist pattern 3AR is also left in the opening), and the oxide semiconductor is etched (this method is not shown, but the resist 3AR is not lifted off). 12). By these methods, it is possible to use Mo, Cu, Al, Ti, ITO, or the like that is weak against acid as the gate electrode 2.

  As the drain electrode 5 and the source electrode 4, various conductive films such as metals such as Mo, Cr, Au, Ag, Cu, Ni, Al, Ti, and transparent conductive films such as ITO can be used. Here too, a photolithography + etching method, a lift-off method, a printing method, or the like can be used. When the drain electrode 5 and the source electrode 4 are attached prior to the sealing layer 9 as shown in FIG. 10, a lift-off method or a printing method is suitable so that the semiconductor layer 6 is not damaged. 11 and 12, when the drain electrode 5 and the source electrode 4 are attached after the sealing layer 9, the semiconductor layer 6 is covered with the sealing layer 9 or the drain electrode 5 and the source electrode 4. Photolithography + etching can be used.

  As the sealing layer 9, an inorganic insulating film such as SiON, SiOx, SiN, Al2O3, Y2O3, or the like can be used. In particular, SiON is particularly preferable because a film having good insulating properties and few defects can be easily obtained by reactive sputtering. When the SiN sintered body is used as a target and the oxygen flow rate is appropriately controlled (for example, when the film is formed at 5% to 20% of (argon flow rate + oxygen flow rate)), good sealing characteristics can be obtained. In normal sputtered SiN film formed only with argon, the stress in the film is too large and easily peels off. When the oxygen flow rate is large, there is a problem that the film formation rate is slow.

  Alternatively, a fluorinated resin in which hydrogen of the resin is replaced with fluorine can be used as the sealing layer 9. Specifically, fluorinated epoxy, fluorinated acrylic, fluorinated polyimide, polyvinylidene fluoride, fluorinated olefin / propylene copolymer, fluorinated olefin / vinyl ether copolymer, fluorinated olefin / vinyl ester copolymer, fluorine An etherified cyclized polymer can be used. In addition, the fluorinated resin includes a partially fluorinated resin in which part of hydrogen is replaced with fluorine, and a fully fluorinated resin in which all hydrogen is replaced with fluorine, but the fully fluorinated resin is more preferable. Unlike ordinary non-fluorinated resins (such as epoxy and acrylic), fluorinated resins are highly stable substances and do not affect oxide semiconductors. In the case of an inorganic insulating film, the lift-off method is suitable for patterning. In the case of a fluorinated resin, patterning can be performed by printing (screen printing, flexographic printing, reversal printing, ink jet printing, etc.), but after forming the entire surface by spin coating or die coating, only the contact portion can be peeled off with tweezers. Good.

  The channel width is determined by the width of the semiconductor layer 6. When the source electrode 4 and the drain electrode 5 are formed before the sealing layer 9 (FIGS. 1 and 10), the channel length is determined by the distance between the source electrode 4 and the drain electrode 5. When the source electrode 4 and the drain electrode 5 are formed after the sealing layer 9 (FIGS. 2 to 3, 11, and 12), the channel length is determined by the width of the sealing layer 9. As shown in FIG. 3, if all the parts other than the connection part are covered with the sealing layer 9, there is an advantage that the leakage current and the stray capacitance at the intersection of the wirings can be reduced.

  1 to 3 are inverters, it goes without saying that other logic circuits such as NAND, NOR, shift register, and the like can be manufactured in the same manner. 1 to 3 is an enhancement / enhancement (E / E) type, but is not limited thereto, and may be an enhancement / depletion (E / D) type or a complementary type. Good. However, since oxide semiconductors are usually n-type, it is necessary to combine p-type semiconductors to make them complementary. Further, such a logic circuit can be used not only as an IC but also as a peripheral circuit of a display around the matrix array.

(Second Embodiment)
Examples of the thin film transistor according to the second embodiment of the present invention are shown in FIGS.
FIG. 4 is a plan view showing one pixel in the TFT array manufactured by the thin film transistor according to the first example of the present embodiment, and a cross-sectional view along the line DD ′.
FIG. 5 is a plan view showing one pixel in the TFT array manufactured by the thin film transistor according to the second example of the present embodiment, and a cross-sectional view taken along the line EE ′.
Further, FIG. 6 shows a plan layout showing one pixel in the TFT array manufactured by the thin film transistor according to the third example of the present embodiment, and a cross-sectional view along the line FF ′.

As shown in FIGS. 4 to 6, in the thin film transistor according to the second embodiment of the present invention, the gate electrode 2, the gate wiring 2 'connected thereto, the capacitor electrode 10, and the capacitor electrode 10 are connected to the insulating substrate 1. Capacitor wiring 10 ′ is provided, gate insulating film 3 and oxide semiconductor pattern 6 are provided, drain electrode 5, drain wiring 5 ′ connected thereto, source electrode 4, and pixel electrode 8 connected thereto are provided. ing.
At least a portion of the oxide semiconductor pattern 6 that is not covered with the source electrode 4 and the drain electrode 5 is covered with the sealing layer 9. The pixel electrode 8 acts to apply a voltage to the image display object. Therefore, it is desirable that the pixel electrode 8 is not covered with the sealing layer 9.
In FIG. 4, a sealing layer 9 is provided so as to cover the semiconductor layer 6 after the source electrode 4 and the drain electrode 5 are attached. In FIG. 5, after the sealing layer 9 is attached so as to cover the channel portion of the semiconductor layer 6, the source electrode 4 and the drain electrode 5 are connected to a portion where the sealing layer 9 is not attached. Further, in FIG. 6, not only the channel portion of the semiconductor layer 6 is covered, but all portions other than the connection portion between the source electrode 4 and the drain electrode 5 and the portion constituting the capacitor under the pixel electrode 8 are covered with the sealing layer 9. It has been broken.

  Next, examples of the manufacturing method are shown in FIGS. As the insulating substrate 1, a rigid substrate such as glass can be used. However, since the process temperature is as low as 200 ° C. or less, a flexible plastic substrate can be used. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE) Polypropylene (PP), nylon (Ny), etc. are used.

  As the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10, and the capacitor wiring 10 ′, any metal such as Mo, Cr, Au, Ag, Cu, Ni, Al, Ti, or a transparent conductive film such as ITO may be used. A conductive film can be used. For patterning, a normal photolithography + etching method can be used, but other methods such as a printing method may be used.

As the gate insulating film 3, an inorganic insulating film such as SiON, SiO _x , SiN, Al ₂ O ₃ , Y ₂ O ₃ or the like can be used. As the oxide semiconductor pattern 6, InGaZnO, InGaSnO, ZnGaO, GaSnO, or the like can be used. As a patterning method of the oxide semiconductor, a normal photolithography + etching method is preferable, but other methods such as a lift-off method may be used.

The drain electrode 5, the drain wiring 5 ′, the source electrode 4, and the pixel electrode 8 can be various types of conductive materials such as metals such as Mo, Cr, Au, Ag, Cu, Ni, Al, and Ti, and transparent conductive films such as ITO. A membrane can be used. Here too, a photolithography + etching method, a lift-off method, a printing method, or the like can be used.
Further, when the drain electrode 5 and the source electrode 4 are attached before the sealing layer 9 as shown in FIG. 13, a lift-off method or a printing method is suitable so that the semiconductor layer 6 is not damaged. Further, when the drain electrode 5 and the source electrode 4 are attached after the sealing layer 9 as shown in FIGS. 14 and 15, the semiconductor layer 6 is covered with the sealing layer 9 or the drain electrode 5 and the source electrode 4. Therefore, photolithography + etching can be used.

As the sealing layer 9, an inorganic insulating film such as SiON, SiO _x , SiN, Al ₂ O ₃ , Y ₂ O ₃ or the like can be used. In particular, SiON is particularly preferable because a film having good insulating properties and few defects can be easily obtained by reactive sputtering. When a SiN sintered body is used as a target and the oxygen flow rate is set to 5% to 20% of (argon flow rate + oxygen flow rate), good sealing characteristics can be obtained. In ordinary SiN film formed only with argon, the stress in the film is too large and easily peels off. When the oxygen flow rate is large, there is a problem that the film formation rate is slow.

  Alternatively, a fluorinated resin in which hydrogen of the resin is replaced with fluorine can be used as the sealing layer 9. Specifically, fluorinated epoxy, fluorinated acrylic, fluorinated polyimide, polyvinylidene fluoride, fluorinated olefin / propylene copolymer, fluorinated olefin / vinyl ether copolymer, fluorinated olefin / vinyl ester copolymer, fluorine An etherified cyclized polymer can be used. In addition, the fluorinated resin includes a partially fluorinated resin in which part of hydrogen is replaced with fluorine, and a fully fluorinated resin in which all hydrogen is replaced with fluorine, but the fully fluorinated resin is more preferable. Unlike ordinary non-fluorinated resins (such as epoxy and acrylic), fluorinated resins are highly stable substances and do not affect oxide semiconductors. In the case of an inorganic insulating film, the lift-off method is suitable for patterning. In the case of a fluorinated resin, patterning can be performed by printing (screen printing, flexographic printing, reverse printing, inkjet printing, etc.).

  The channel width is determined by the width of the semiconductor layer 6. When the source electrode 4 and the drain electrode 5 are formed before the sealing layer 9 (FIGS. 4 and 13), the channel length is determined by the distance between the source electrode 4 and the drain electrode 5. When the source electrode 4 and the drain electrode 5 are formed after the sealing layer 9 (FIGS. 5 to 6, 14, and 15), the channel length is determined by the width of the sealing layer 9. Further, if all the parts other than the connection part are covered with the sealing layer 9 as shown in FIG. 6, there is an advantage that the leakage current and the stray capacitance at the intersection of the wirings can be reduced.

(Third embodiment)
Examples of the thin film transistor according to the third embodiment of the present invention are shown in FIGS.
FIG. 7 is a plan view showing one pixel in the TFT array manufactured by the thin film transistor according to the first example of the present embodiment, and a cross-sectional view taken along the line GG ′.
FIG. 8 shows a plan layout showing one pixel in a TFT array manufactured by the thin film transistor according to the second example of the present embodiment, and a cross-sectional view taken along the line HH ′.
Further, FIG. 9 shows a plan layout showing one pixel in the TFT array manufactured by the thin film transistor according to the third example of the present embodiment, and a cross-sectional view taken along line II ′.

As shown in FIGS. 7 to 9, in the thin film transistor according to the third embodiment of the present invention, the gate electrode 2, the gate wiring 2 'connected thereto, the capacitor electrode 10, and the capacitor connected thereto are formed on the insulating substrate 1. A wiring 10 ′ is provided, the gate insulating film 3 and the oxide semiconductor pattern 6 are provided, a drain electrode 5, a drain wiring 5 ′ connected thereto, a source electrode 4, and a pixel electrode 8 connected thereto are provided. Yes. At least a portion on the oxide semiconductor pattern 6 is covered with the sealing layer 9. Further, an interlayer insulating film 7 having an opening is provided on the pixel electrode 8, and an upper pixel electrode 12 is provided thereon. The upper pixel electrode 12 is connected to the pixel electrode 8 in the opening 7 A of the interlayer insulating film 7. Further, it is desirable to cover most of the drain electrode 5, the source electrode 4, the gate wiring 2 ′, and the capacitor electrode 10.
In FIG. 7, a sealing layer 9 is provided so as to cover the semiconductor layer 6 after the source electrode 4 and the drain electrode 5 are attached. In FIG. 8, after the sealing layer 9 is attached so as to cover the channel portion of the semiconductor layer 6, the source electrode 4 and the drain electrode 5 are connected to a portion where the sealing layer 9 is not attached. Further, in FIG. 9, not only the channel portion of the semiconductor layer 6 is covered, but all the portions other than the connection portion between the source electrode 4 and the drain electrode 5 and the portion constituting the capacitor under the pixel electrode 8 are covered with the sealing layer 9. It has been broken.

  Next, examples of the manufacturing method are shown in FIGS. As the insulating substrate 1, a rigid substrate such as glass can be used. However, since the process temperature is as low as 200 ° C. or less, a flexible plastic substrate can be used. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE) Polypropylene (PP), nylon (Ny), etc. are used.

  As the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10, and the capacitor wiring 10 ′, any metal such as Mo, Cr, Au, Ag, Cu, Ni, Al, Ti, or a transparent conductive film such as ITO may be used. A conductive film can be used. For patterning, a normal photolithography + etching method can be used, but other methods such as a printing method may be used.

As the gate insulating film 3, an inorganic insulating film such as SiON, SiO _x , SiN, Al ₂ O ₃ , Y ₂ O ₃ or the like can be used. As the oxide semiconductor pattern 6, InGaZnO, InGaSnO, ZnGaO, GaSnO, or the like can be used. As a patterning method of the oxide semiconductor, a normal photolithography + etching method is preferable, but other methods such as a lift-off method may be used.

  The drain electrode 5, the drain wiring 5 ′, the source electrode 4, and the pixel electrode 8 can be various types of conductive materials such as metals such as Mo, Cr, Au, Ag, Cu, Ni, Al, and Ti, and transparent conductive films such as ITO. A membrane can be used. Here too, a photolithography + etching method, a lift-off method, a printing method, or the like can be used. When the drain electrode 5 and the source electrode 4 are attached before the sealing layer 9 as shown in FIG. 16, the lift-off method or the printing method is suitable so that the semiconductor layer 6 is not damaged. When the drain electrode 5 and the source electrode 4 are attached after the sealing layer 9 as shown in FIGS. 17 and 18, the semiconductor layer 6 is covered with the sealing layer 9 or the drain electrode 5 and the source electrode 4. Therefore, photolithography + etching can be used.

The sealing layer _{9, SiON, SiO x, SiN} , Al 2 O 3, Y 2 O 3 , etc., may be used an inorganic insulating film. In particular, SiON is particularly preferable because a film having good insulating properties and few defects can be easily obtained by reactive sputtering. When a SiN sintered body is used as a target and the oxygen flow rate is set to 5% to 20% of (argon flow rate + oxygen flow rate), good sealing characteristics can be obtained. In ordinary SiN film formed only with argon, the stress in the film is too large and easily peels off. When the oxygen flow rate is large, there is a problem that the film formation rate is slow.

  Alternatively, a fluorinated resin in which hydrogen of the resin is replaced with fluorine can be used as the sealing layer 9. Specifically, fluorinated epoxy, fluorinated acrylic, fluorinated polyimide, polyvinylidene fluoride, fluorinated olefin / propylene copolymer, fluorinated olefin / vinyl ether copolymer, fluorinated olefin / vinyl ester copolymer, fluorine An etherified cyclized polymer can be used. In addition, the fluorinated resin includes a partially fluorinated resin in which a part of hydrogen is replaced with fluorine, and a fully fluorinated resin in which all hydrogen is replaced with fluorine, and the perfluorinated resin is more preferable. Unlike ordinary non-fluorinated resins (such as epoxy and acrylic), fluorinated resins are highly stable substances and do not affect oxide semiconductors. In the case of an inorganic insulating film, the lift-off method is suitable for patterning. In the case of a fully fluorinated resin, patterning can be performed by printing (screen printing, flexographic printing, reverse printing, inkjet printing, etc.).

  The channel width is determined by the width of the semiconductor layer 6. When the source electrode 4 and the drain electrode 5 are formed before the sealing layer 9 (FIGS. 7 and 16), the channel length is determined by the distance between the source electrode 4 and the drain electrode 5. When the source electrode 4 and the drain electrode 5 are formed after the sealing layer 9 (FIGS. 8, 9, 17, and 18), the channel length is determined by the width of the sealing layer 9. Further, if all the parts other than the connection part are covered with the sealing layer 9 as shown in FIG. 9, there is an advantage that the leakage current and the stray capacitance at the intersection of the wirings can be reduced.

  As the interlayer insulating film 7, an organic insulator such as epoxy or acrylic is preferably used. A method of directly forming an interlayer insulating film having an opening by screen printing, or a method of forming an opening by exposure and development after film formation on the entire surface while imparting photosensitivity is preferable.

  As the upper pixel electrode 12, an arbitrary conductive film such as a metal such as Mo, Cr, Au, Ag, Cu, Ni, Al, or Ti, or a transparent conductive film such as ITO can be used. The upper pixel electrode 12 acts to apply a voltage to the image display object. As a manufacturing method, the film may be formed on the entire surface and then formed by photolithography + etching. However, if a printing method, particularly screen printing, is used, film formation and patterning can be performed simultaneously in a simple process, which is preferable. .

  By the way, in the oxide semiconductor, oxygen vacancies act as n-type carriers. This is why most oxide semiconductors operate n-type. When a general non-fluorinated resin is applied thereon, the non-fluorinated resin is oxidized to reduce the oxide semiconductor and increase oxygen vacancies (carriers) in the oxide semiconductor. ITO or the like used as a transparent electrode, a pn junction element, or the like is originally used in a state where the carrier is high, and there is no problem even if the carrier is slightly increased. However, in a thin film transistor whose basic condition is that there are almost no carriers, an increase in carriers due to an external cause causes a threshold shift and becomes a serious problem. Inorganic insulating films and fluorinated resins manufactured under good conditions have little effect of depriving oxygen, so even if they are formed on oxide semiconductors, they do not increase carriers, and ordinary resins are applied on them. However, it does not increase the carrier because it blocks the action of depriving oxygen.

  In addition, since it uses as a display, it cannot be overemphasized that TFT of FIGS. 4-9 is used as a matrix-like array. Since the TFTs in FIGS. 4 to 9 are for switching, the names of the drain electrode 5 and the gate electrode 4 are convenient and may be called in reverse.

  As Example 1 of the present invention, a method of manufacturing the logic circuit of FIG. 1 will be described with reference to FIGS. PEN was used as the insulating substrate 1, Al was deposited to a thickness of 30 nm on the entire surface, and the gate electrode 2 was formed by photolithography and wet etching. Then, a resist pattern was formed on the gate opening planned portion by photolithography (FIG. 10A). Next, a SiON film of 500 nm was formed as the gate insulating film 3 and an InGaZnO film was formed as the oxide semiconductor 6 by 50 nm continuous sputtering (FIG. 10B). Then, the resist was removed by dipping in a stripping solution to form a gate opening (FIG. 10C). Further, a resist is applied on the entire surface to form a pattern 6R that leaves the resist not only in the semiconductor pattern but also in the gate insulating film opening (FIG. 10D), and the oxide semiconductor is patterned by wet etching (FIG. 10E )).

Next, an ITO pattern having a thickness of 50 nm was formed as the drain electrode 5 and the source electrode 4 by a lift-off method (FIG. 10 (f)). Finally, a 200 nm thick SiON pattern was formed as the sealing layer 9 by the lift-off method (FIG. 10G).
The input / output characteristics shown in FIG. 19 were obtained when a power supply of 15 V was applied to the inverter thus fabricated.

  As Example 2 of the present invention, a method of manufacturing the logic circuit of FIG. 2 will be described with reference to FIG. PEN was used as the insulating substrate 1, Al was deposited to a thickness of 30 nm on the entire surface, and the gate electrode 2 was formed by photolithography and wet etching. Then, a resist pattern was formed on the gate opening planned portion by photolithography (FIG. 11A). Next, a SiON film having a thickness of 500 nm was formed as the gate insulating film 3 and an InGaZnO film having a thickness of 50 nm was formed as the oxide semiconductor 6 (FIG. 11B). Then, the resist was removed by soaking in a stripping solution, and a gate opening was formed (FIG. 11C). Further, a resist is applied to the entire surface to form a pattern 6R that leaves the resist not only in the semiconductor pattern but also in the gate insulating film opening (FIG. 11D), and the oxide semiconductor is patterned by wet etching (FIG. 11E )).

Next, an SiON pattern having a thickness of 200 nm was formed as the sealing layer 9 by a lift-off method (FIG. 11F). Finally, an ITO pattern having a thickness of 50 nm was formed as the drain electrode 5 and the source electrode 4 by photolithography and etching (FIG. 11G).
Input / output characteristics similar to those in FIG. 19 were obtained when a power supply of 15 V was applied to the inverter thus fabricated.

  As Embodiment 3 of the present invention, a method for manufacturing the logic circuit of FIG. 3 will be described with reference to FIG. PEN was used as the insulating substrate 1, Al was deposited to a thickness of 30 nm on the entire surface, and the gate electrode 2 was formed by photolithography and wet etching. Then, a resist pattern was formed on the gate opening planned portion by photolithography (FIG. 12A). Next, a SiON film having a thickness of 500 nm was formed as the gate insulating film 3 and an InGaZnO film having a thickness of 50 nm was formed as the oxide semiconductor 6 (FIG. 12B). Then, the resist was removed by soaking in a stripping solution, and a gate opening was formed (FIG. 12C). Further, a resist is applied on the entire surface to form a pattern 6R that leaves the resist not only in the semiconductor pattern but also in the gate insulating film opening (FIG. 12D), and the oxide semiconductor is patterned by wet etching (FIG. 12E )).

Next, a SiON pattern having a thickness of 200 nm was formed as the sealing layer 9 by a lift-off method (FIG. 12F). Finally, an ITO pattern having a thickness of 50 nm was formed as the drain electrode 5 and the source electrode 4 by photolithography and etching (FIG. 12G).
Input / output characteristics similar to those in FIG. 19 were obtained when a power supply of 15 V was applied to the inverter thus fabricated.

  As Example 4 of the present invention, a method of manufacturing the TFT of FIG. 4 will be described with reference to FIGS. PEN was used as the insulating substrate 1, Al was deposited to a thickness of 30 nm, and the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10, and the capacitor wiring 10 ′ were formed by photolithography and wet etching (FIG. 13A). . Next, SiON is sputtered to 500 nm as the gate insulating film 3 (FIG. 13B), InGaZnO is sputtered to 50 nm as the oxide semiconductor 6, and the oxide semiconductor is patterned by photolithography and wet etching (FIG. 13). (C)).

Next, an ITO pattern having a thickness of 100 nm was formed as the drain electrode 5 and the source electrode 4 by a lift-off method (FIG. 13D). Finally, a 200 nm thick SiON pattern was formed as the sealing layer 9 by the lift-off method (FIG. 13E).
The guest host liquid crystal 15 was sealed between the TFT array thus fabricated and the counter electrode (ITO) 14 / the counter substrate 13 to confirm that the monochrome liquid crystal display of FIG. 20 was displayed normally.

  As Example 5 of the present invention, a method of manufacturing the TFT of FIG. 5 will be described with reference to FIG. PEN was used as the insulating substrate 1, Al was deposited to a thickness of 30 nm on the entire surface, and the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10, and the capacitor wiring 10 ′ were formed by photolithography and wet etching (FIG. 14A). . Next, SiON is sputtered to 500 nm as the gate insulating film 3 (FIG. 14B), and InGaZnO is sputtered to 50 nm as the oxide semiconductor 6, and the oxide semiconductor is patterned by photolithography and wet etching (FIG. 14). (C)).

Next, a SiON pattern having a thickness of 200 nm was formed as the sealing layer 9 by a lift-off method (FIG. 14D). Finally, an ITO pattern of 100 nm was formed as the drain electrode 5 and the source electrode 4 by photolithography and etching (FIG. 14E).
It was confirmed that the guest host liquid crystal 15 was sealed between the TFT array thus produced and the counter electrode (ITO) 14 / the counter substrate 13 to obtain a monochrome liquid crystal display as shown in FIG.

  As Example 6 of the present invention, a method of manufacturing the TFT of FIG. 6 will be described with reference to FIG. Using PEN as the insulating substrate 1, Al was deposited to a thickness of 30 nm on the entire surface, and the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10 and the capacitor wiring 10 ′ were formed by photolithography and wet etching (FIG. 15A). . Next, SiON is sputtered to 500 nm as the gate insulating film 3 (FIG. 15B), InGaZnO is sputtered to 50 nm as the oxide semiconductor 6, and the oxide semiconductor is patterned by photolithography and wet etching (FIG. 15). (C)).

Next, a SiON pattern having a thickness of 200 nm was formed as the sealing layer 9 by a lift-off method (FIG. 15D). Finally, an ITO pattern of 100 nm was formed as the drain electrode 5 and the source electrode 4 by photolithography and etching methods (FIG. 15E).
It was confirmed that the guest host liquid crystal 15 was sealed between the TFT array thus produced and the counter electrode (ITO) 14 / the counter substrate 13 to obtain a monochrome liquid crystal display as shown in FIG.

  As Example 7 of the present invention, a method of manufacturing the TFT of FIG. 7 will be described with reference to FIG. PEN was used as the insulating substrate 1, Al was formed to a thickness of 30 nm on the entire surface, and the gate electrode 2 was formed by photolithography and wet etching (FIG. 16A). Next, SiON is sputtered to 500 nm as the gate insulating film 3 (FIG. 16B), InGaZnO is sputtered to 200 nm as the oxide semiconductor 6, and the oxide semiconductor is patterned by photolithography and wet etching (FIG. 16). (C)).

Next, an ITO pattern of 50 nm was formed as the drain electrode 5 and the source electrode 4 by the lift-off method (FIG. 16D). Then, a 200 nm SiON pattern was formed as the sealing layer 9 by the lift-off method (FIG. 16E). Further, 20 μm of a photosensitive acrylic film was applied, and an interlayer insulating film 7 was formed by exposure and development (FIG. 16F). Finally, Ag paste was screen printed and baked at 100 ° C. to form the upper pixel electrode 12 (FIG. 16G).
The electronic paper of FIG. 21 was produced by laminating the TFT array thus produced and the adhesive 18 / electrophoresis capsule 16 / counter electrode (ITO) 14 / counter substrate 13, and it was confirmed that normal display was possible.

  As Example 8 of the present invention, a method of manufacturing the TFT of FIG. 8 will be described with reference to FIGS. PEN was used as the insulating substrate 1, Al was deposited to a thickness of 30 nm on the entire surface, and the gate electrode 2 was formed by photolithography and wet etching (FIG. 17A). Next, SiON is sputtered to 500 nm as the gate insulating film 3 (FIG. 17B), InGaZnO is sputtered to 200 nm as the oxide semiconductor 6, and the oxide semiconductor is patterned by photolithography and wet etching (FIG. 17). (C)).

  Next, a 200 nm SiON pattern was formed as the sealing layer 9 by the lift-off method (FIG. 17D). Then, an ITO pattern of 50 nm was formed as the drain electrode 5 and the source electrode 4 by photolithography and etching (FIG. 17E). Further, 20 μm of a photosensitive acrylic film was applied, and an interlayer insulating film 7 was formed by exposure and development (FIG. 17F). Finally, Ag paste was screen printed and baked at 100 ° C. to form the upper pixel electrode 12 (FIG. 17G).

  An electronic paper as shown in FIG. 21 was prepared by laminating the TFT array thus prepared and the adhesive 18 / electrophoresis capsule 16 / counter electrode (ITO) 14 / counter substrate 13, and it was confirmed that normal display was possible.

  As an embodiment of the present invention, a method of manufacturing the TFT of FIG. 9 will be described with reference to FIG. PEN was used as the insulating substrate 1, Al was deposited to a thickness of 30 nm on the entire surface, and the gate electrode 2 was formed by photolithography and wet etching (FIG. 18A). Next, SiON is sputtered to 500 nm as the gate insulating film 3 (FIG. 18B), InGaZnO is sputtered to 200 nm as the oxide semiconductor 6, and the oxide semiconductor is patterned by photolithography and wet etching (FIG. 18). (C)).

  Next, a 200 nm SiON pattern was formed as the sealing layer 9 by a lift-off method (FIG. 18D). Then, an ITO pattern of 50 nm was formed as the drain electrode 5 and the source electrode 4 by photolithography and etching (FIG. 18E). Furthermore, 20 μm of a photosensitive acrylic film was applied, and an interlayer insulating film 7 was formed by exposure and development (FIG. 18F). Finally, Ag paste was screen printed and baked at 100 ° C. to form the upper pixel electrode 12 (FIG. 18G).

  An electronic paper as shown in FIG. 21 was prepared by laminating the TFT array thus prepared and the adhesive 18 / electrophoresis capsule 16 / counter electrode (ITO) 14 / counter substrate 13, and it was confirmed that normal display was possible.

  The following investigated the effect of the sealing layer 9. When reactive sputtering of SiON is used as the sealing layer 9 (O2 flow rate ratio 5% with respect to the total flow rate), even if a photosensitive acrylic resin is applied thereon, the change in the threshold value of the TFT is within ± 2 V Met. The SiON reactive sputtering conditions were a pressure of 0.5 Pa, an Ar flow rate of 38 sccm, an O2 flow rate of 2 sccm, a power of 300 W, and a film thickness of 200 nm.

  When reactive sputtering of SiON is used as the sealing layer 9 (O2 flow rate ratio 10% with respect to the total flow rate), even if a photosensitive acrylic resin is applied thereon, the change in the threshold value of the TFT is within ± 2 V Met. The SiON reactive sputtering conditions were a pressure of 0.5 Pa, an Ar flow rate of 36 sccm, an O2 flow rate of 4 sccm, a power of 300 W, and a film thickness of 200 nm.

  When reactive sputtering of SiON (20% ratio of O2 flow rate to the total flow rate) is used as the sealing layer 9, even if a photosensitive acrylic resin is applied thereon, the change in the threshold value of the TFT is within ± 2V. Met. The SiON reactive sputtering conditions were a pressure of 0.5 Pa, an Ar flow rate of 32 sccm, an O2 flow rate of 8 sccm, a power of 300 W, and a film thickness of 200 nm.

  When CYTOP (manufactured by Asahi Glass Co., Ltd.), which is a fluorinated resin, is used as the sealing layer 9, even if a photosensitive acrylic resin is applied thereon, the change in the TFT threshold is within ± 2V. It was.

Next, a comparative example will be described.
(Comparative Example 1)
In the case without the sealing layer 9, the change in the threshold value of the TFT when a photosensitive acrylic resin was applied thereon was −30V.

(Comparative Example 2)
When sputtering of SiN was used as the sealing layer 9, the sealing layer 9 was peeled off after film formation. It seems that the stress in the sealing layer 9 was large. The SiN sputtering conditions were pressure 0.5 Pa, Ar flow rate 40 sccm, power 300 W, and film thickness 200 nm.

1A and 1B are a plan view and a cross-sectional view illustrating an example of a thin film transistor according to a first embodiment of the invention. It is the top view and sectional drawing which show the other example of the thin-film transistor which concerns on the 1st Embodiment of this invention. It is the top view and sectional drawing which show another example in addition to the thin-film transistor which concerns on the 1st Embodiment of this invention. It is the top view and sectional drawing which show an example of the thin-film transistor concerning the 2nd Embodiment of this invention. It is the top view and sectional drawing which show the other example of the thin-film transistor which concerns on the 2nd Embodiment of this invention. It is the top view and sectional drawing which show another example of the thin-film transistor which concerns on the 2nd Embodiment of this invention. It is the top view and sectional drawing which show an example of the thin-film transistor concerning the 3rd Embodiment of this invention. It is the top view and sectional drawing which show the other example of the thin-film transistor which concerns on the 3rd Embodiment of this invention. It is the top view and sectional drawing which show another example of the thin-film transistor which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. FIG. 3 is a cross-sectional view showing an example of a manufacturing process of the thin film transistor shown in FIG. It is sectional drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. FIG. 5 is a cross-sectional view illustrating an example of a manufacturing process of the thin film transistor illustrated in FIG. 4. FIG. 6 is a cross-sectional view illustrating an example of a manufacturing process of the thin film transistor illustrated in FIG. 5. FIG. 7 is a cross-sectional view illustrating an example of a manufacturing process of the thin film transistor illustrated in FIG. 6. It is sectional drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. It is sectional drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. It is sectional drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. It is explanatory drawing which shows the operating characteristic of the inverter which concerns on Example 1 of this invention. It is sectional drawing which shows the example of the liquid crystal display which concerns on Example 2 of this invention. It is sectional drawing which shows the example of the electronic paper which concerns on Example 3 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Gate electrode, 2 '... Gate wiring, 3 ... Gate insulating film, 3A ... Gate insulating film opening part, 3AR ... Resist of gate insulating film opening part, 4 ... Source electrode, 5 ... Drain electrode, 5 '... Drain wiring, 6 ... Oxide semiconductor pattern, 6L ... Oxide semiconductor layer, 6R ... Oxide semiconductor patterning resist, 7 ... Interlayer insulating film, 7A ... Interlayer insulating film opening, 8... Pixel electrode, 9... Sealing layer, 9 A... Sealing layer opening, 10... Capacitor electrode, 10 '. DESCRIPTION OF SYMBOLS 13 ... Counter substrate, 14 ... Counter electrode, 15 ... Liquid crystal, 16 ... Electrophoresis capsule, 17 ... Black matrix, 18 ... Adhesive, 21 ... Power supply electrode, 22 ... GND electrode, 23 ... ... input electrode, 24 ... output electrode.

Claims (16)

A gate electrode formed on an insulating substrate; a gate insulating film formed on the gate electrode; and a drain electrode and a source electrode disposed on the gate insulating film, at least the drain electrode and the source electrode A thin film transistor in which an oxide semiconductor pattern is disposed in a gap portion of
Provided a sealing layer on the oxide semiconductor pattern,
A thin film transistor.   2. The thin film transistor according to claim 1, wherein the sealing layer is an inorganic insulating film.   3. The thin film transistor according to claim 2, wherein the sealing layer is silicon oxynitride.   2. The thin film transistor according to claim 1, wherein the sealing layer is a fluorinated resin.   A gate wiring connected to the gate electrode, a capacitor electrode, and a capacitor wiring connected to the capacitor electrode in the same layer as the gate electrode, and connected to the drain electrode in the same layer as the drain electrode and the source electrode; 5. The thin film transistor according to claim 1, comprising a drain wiring and a pixel electrode connected to the source electrode, and having no sealing layer on at least the pixel electrode.   A gate wiring connected to the gate electrode, a capacitor electrode, and a capacitor wiring connected to the capacitor electrode in the same layer as the gate electrode, and connected to the drain electrode in the same layer as the drain electrode and the source electrode; A drain wiring and a pixel electrode connected to the source electrode; a sealing layer on at least the oxide semiconductor pattern; and an interlayer insulating film having an opening in the pixel electrode portion on the sealing layer 6. The thin film transistor according to claim 1, further comprising an upper pixel electrode connected to the pixel electrode at the opening on the interlayer insulating film. Forming a gate electrode on an insulating substrate; forming a resist pattern on a gate insulating film opening portion; forming a gate insulating film and an oxide semiconductor; and forming a gate insulating film opening portion resist on the insulating substrate. Removing and forming an opening in the gate insulating film; patterning an oxide semiconductor before or after forming the opening; forming a drain electrode and a source electrode; and the drain electrode and the source electrode Forming a sealing layer before or after the formation of
When patterning the oxide semiconductor, the gate electrode in the opening is not exposed to the etchant by not etching the vicinity of the gate insulating film opening.
A method for manufacturing a thin film transistor.   Forming a gate electrode on an insulating substrate; forming a gate insulating film; forming an oxide semiconductor pattern; forming a drain electrode and a source electrode; and forming the drain electrode and the source electrode And a step of forming a sealing layer before or after the formation, and the step of forming the sealing layer is reactive sputtering.   9. The method of manufacturing a thin film transistor according to claim 8, wherein the step of forming the sealing layer is reactive sputtering using a SiN sintered body as a target. A step of forming a gate electrode, a gate wiring, a capacitor electrode, and a capacitor wiring on an insulating substrate, a step of forming a gate insulating film, a step of forming an oxide semiconductor pattern, a drain electrode, a drain wiring, a source electrode, And a step of forming a pixel electrode, a step of forming a sealing layer before or after forming the drain electrode, drain wiring, source electrode, and pixel electrode, a step of forming an interlayer insulating film, and an upper pixel electrode And forming a process,
The step of forming the upper pixel electrode is screen printing;
A method for manufacturing a thin film transistor. A gate electrode formed on an insulating substrate; a gate insulating film formed on the gate electrode; and a drain electrode and a source electrode disposed on the gate insulating film, at least the drain electrode and the source electrode A thin film transistor display using a thin film transistor in which an oxide semiconductor pattern is arranged in a gap portion of
The thin film transistor provided a sealing layer on the oxide semiconductor pattern,
A thin film transistor display.   12. The thin film transistor display according to claim 11, wherein the sealing layer of the thin film transistor is an inorganic insulating film.   13. The thin film transistor display according to claim 12, wherein the sealing layer of the thin film transistor is silicon oxynitride.   12. The thin film transistor display according to claim 11, wherein the sealing layer of the thin film transistor is a fluorinated resin.   A gate wiring connected to the gate electrode, a capacitor electrode, and a capacitor wiring connected to the capacitor electrode in the same layer as the gate electrode, and connected to the drain electrode in the same layer as the drain electrode and the source electrode; The thin film transistor display according to claim 11, further comprising a pixel electrode connected to the drain wiring and the source electrode, and having no sealing layer on at least the pixel electrode. A gate wiring connected to the gate electrode, a capacitor electrode, and a capacitor wiring connected to the capacitor electrode in the same layer as the gate electrode, and connected to the drain electrode in the same layer as the drain electrode and the source electrode; A drain wiring and a pixel electrode connected to the source electrode; a sealing layer on at least the oxide semiconductor pattern; and an interlayer insulating film having an opening in the pixel electrode portion on the sealing layer 16. The thin film transistor display according to claim 11, further comprising an upper pixel electrode connected to the pixel electrode at the opening on the interlayer insulating film.

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