JP2007287809A - Laminated semiconductor device and method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated semiconductor device which has such a structure that a semiconductor chip having an identical or nearly identical chip area can be easily laminated. <P>SOLUTION: The front face of a first semiconductor chip 1 and the rear face of a die pad 3 are adhered to each other, the rear face of a second semiconductor chip 2 and the front face of the die pad 3 are adhered to each other, the electrode pad 5a of the first semiconductor chip 1 is connected with the front face of an inner lead 6 through a wire 7a, and the electrode pad 5b of the second semiconductor chip 2 is connected with the front face of the inner lead 6 through a wire 7b. The die pad 3 is made smaller in area than the first semiconductor chip 1 and the second semiconductor chip 2, and the electrode pad 5a is provided in an area other than a bonding face between the front face of the first semiconductor chip 1 and the rear face of the die pad 3, and the wire 7a connected with the electrode pad 5a passes through the front face of the first semiconductor chip 1, the rear face of the second semiconductor chip 2 and a concave space 12 surrounded by the outer side face of the die pad 3, and enters the electrode pad 5a of the first semiconductor chip 1 from the diagonally upper side. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and an assembly technique thereof, and more specifically, a stacked semiconductor device in which a plurality of semiconductor chips having the same chip area or similar chip areas are stacked and mounted in a package, and the stacked layer The present invention relates to a method for manufacturing a type semiconductor device.

  In recent years, with the increase in memory capacity and the increased integration of semiconductor chips such as mixed memory and logic, multiple semiconductor chips are stacked in the same package in order to realize them in a limited area. There are an increasing number of stacked semiconductor devices.

  In particular, with respect to an increase in memory capacity, it is the mainstream to stack the same chip, and a similar chip area may be stacked even when the memory and logic are mounted together. As a stacked semiconductor device in which semiconductor chips having the same chip area or similar chip area are stacked, the first conventional structure disclosed in FIG. 8 of Patent Document 1 or FIG. It is used.

  In the first conventional structure, for example, as representatively shown in FIG. 5, one semiconductor chip 21 is placed on the surface of the die pad 23 on the front and back surfaces of the die pad 23 of the lead frame, and the other semiconductor chip 22 is placed on the die pad. The back surface of the semiconductor chip 21 is back-to-back and bonded and fixed with adhesives 24a and 24b. The connection between the semiconductor chips 21 and 22 and the lead frame inner lead 26 is performed by the electrode pad 25a of the semiconductor chip 21 on the surface of the die pad 23. The electrode pad 25 b of the semiconductor chip 22 on the back surface of the die pad 23 is connected to the back surface of the inner lead 26 on the surface of the inner lead 26.

  The stacked semiconductor device having the first conventional structure is manufactured by the following manufacturing method. First, the adhesive 24a is applied to the surface of the die pad 23 of the lead frame, and the first semiconductor chip 21 is mounted and fixed. Next, the lead frame on which the first semiconductor chip 21 is mounted is turned over, the adhesive 24b is applied to the back surface of the die pad 23, and the second semiconductor chip 22 is mounted and fixed. Next, the electrode pad 25 a of the first semiconductor chip 21 and the surface of the inner lead 26 are connected by a wire 27 a. Next, the lead frame in which the first semiconductor chip 21 and the inner lead 26 are joined by the wire is turned over, and both are connected by the wire 27b between the electrode pad 25b of the second semiconductor chip 22 and the back surface of the inner lead 26. Connecting. Thereafter, the semiconductor chips 21 and 22, the die pad 23, the inner lead 26, and the wires 27a and 27b are sealed with resin and separated from the outer frame of the lead frame.

  Incidentally, the stacked semiconductor device having the first conventional structure has the following problems, and various improvements have been attempted.

  That is, in the stacked semiconductor device having the first conventional structure, as shown in FIG. 5, the first semiconductor chip 21 and the second semiconductor chip 22 are back-to-back with the die pad 23 interposed therebetween. In order to mount and fix the semiconductor chip on the die pad, and to connect the wires to the inner leads, it is necessary to turn the lead frame several times during the manufacturing process, which makes the manufacturing process complicated. It was a factor of cost increase.

  Furthermore, in order to mount and fix one semiconductor chip and connect it to the inner lead, the element surface and the wire part of the other semiconductor chip are located below the lead frame. It is necessary to prevent scratches on the element surface of the semiconductor chip and deformation of the wire portion, and it is necessary to handle the semiconductor chip sufficiently carefully.

  Accordingly, in order to solve the problems of the stacked semiconductor device having the first conventional structure, the second stacked semiconductor device having the conventional structure (see Patent Document 1) and the third conventional structure described below are used. A stacked semiconductor device (see Patent Document 2) has been proposed.

  In both of the stacked semiconductor devices of the second and third conventional structures, the semiconductor chip mounted on the back surface side of the die pad is not bonded and fixed back to back, but the front surface of the semiconductor chip and the back surface of the die pad are opposed to each other. In other words, mounting the lead frame on the same side as the semiconductor chip mounted on the surface side of the die pad avoids turning the lead frame over several times during the manufacturing process.

  As shown in FIG. 6, the stacked semiconductor device of the second conventional structure has a first semiconductor chip 31 smaller than the die pad 33 on the front and back surfaces of the die pad 33 of the lead frame and the die pad 33. The second semiconductor chip 32 larger than 33 is bonded and fixed to the back surface of the die pad 33 and the respective element surfaces are aligned on the upper side, and the connection between the semiconductor chips 31 and 32 and the lead leads 36 to the inner leads 36 is performed. The electrode pads 35a and 35b of the semiconductor chips 31 and 32 on both the front and back surfaces are connected to the surface of the inner lead 36 via wires 37a and 37b, respectively.

  The stacked semiconductor device having the second conventional structure is manufactured by the following manufacturing method. First, an adhesive tape 34b attached to the back surface (lower surface) of the die pad 33 of the lead frame is prepared, and the second semiconductor chip 32 is mounted on the back surface of the die pad 33 by thermocompression bonding. Next, an adhesive 34 a is applied to the surface (upper surface) of the die pad 33 to mount and fix the first semiconductor chip 31. Next, the electrode pad 35a of the first semiconductor chip 31 and the surface (upper surface) of the inner lead 36 are connected by a wire 37a, and the electrode pad 35b of the second semiconductor chip 32 and the surface of the inner lead 36 ( The upper surface is connected by a wire 37b. Thereafter, the semiconductor chips 31, 32, the die pad 33, the inner leads 36, and the wires 37a, 37b are sealed with resin and separated from the outer frame of the lead frame.

  As shown in FIG. 7, the stacked semiconductor device having the third conventional structure includes a first semiconductor chip 41 in which electrode pads are arranged on the front and back surfaces of the die pad 43 of the lead frame, and the surface of the die pad 43. Further, the second semiconductor chip 42 having an electrode pad disposed at the center of the chip is bonded and fixed to the back surface of the die pad 43 with the respective element surfaces aligned on the upper side, and the inner leads of each of the semiconductor chips 41 and 42 and the lead frame are fixed. The connection to 46 has a structure in which the electrode pads 45a and 45b of the semiconductor chips 41 and 42 on both the front and back surfaces of the die pad 43 are connected to the surface of the inner lead 46 via wires 47a and 47b, respectively.

  The stacked semiconductor device having the third conventional structure is manufactured by the following manufacturing method. First, an adhesive tape 44b having an opening at the center is similarly applied to the back surface (lower surface) of the die pad 43 having an opening at the center of the lead frame, and the element of the second semiconductor chip 42 is attached to the back of the die pad 43. Adhere with the faces facing each other. At this time, the electrode pad 45 a of the second semiconductor chip 42 disposed in the center of the chip is exposed in the opening of the die pad 43. Next, the electrode pad 45 b of the second semiconductor chip 42 and the surface (upper surface) of the inner lead 46 are connected by a wire 47 a that straddles the upper side of the die pad 43 and passes through the opening of the die pad 43. Next, a non-conductive adhesive 44 a is applied to the surface (upper surface) of the die pad 43, the inside of the die pad 43 is filled, and the first semiconductor chip 41 is mounted and fixed on the surface of the die pad 43. Next, the electrode pad 41a of the first semiconductor chip 41 and the surface (upper surface) of the inner lead 46 are connected by a wire 47a. Thereafter, the semiconductor chips 41 and 42, the die pad 43, the inner leads 46, and the wires 47a and 47b are sealed with resin and separated from the outer frame of the lead frame.

JP 11-317488 A Japanese Patent Laid-Open No. 2004-200683

  However, the stacked semiconductor devices according to the second and third conventional structures described above have the following problems. That is, in the stacked semiconductor device according to the second conventional structure, the semiconductor chip mounted on the front surface side of the die pad is made smaller than the semiconductor chip mounted on the back surface side of the die pad so that the die pad is an intermediate size between the two semiconductor chips. As a result, a space margin required for wire connection above the electrode pad of the semiconductor chip mounted on the back surface side is secured, so a stacked semiconductor device in which semiconductor chips having the same chip area are mounted on both the front and back surfaces of the die pad is realized. I can't.

  Furthermore, in the stacked semiconductor device having the third conventional structure, the electrode pad of the semiconductor chip to be mounted on the back side of the die pad needs to be arranged in the center of the chip, which can restrict the design of the semiconductor chip, It is impossible to stack the same kind of semiconductor chips on which pads are arranged. Speaking extremely, it is not possible to stack the same semiconductor chip in which electrode pads are arranged on the periphery of the chip. In addition, a wire connecting the semiconductor chip mounted on the back side of the die pad and the inner lead passes between the front surface of the die pad and the back surface of the semiconductor chip mounted on the front side of the die pad, and the wire also becomes long and easily bent. Therefore, the thickness of the two semiconductor chips stacked is increased. Therefore, when there is a restriction on the thickness of the package, the interval is narrowed, and there is a possibility that the wire contacts the surface of the die pad or the back surface of the upper semiconductor chip.

  The present invention has been made in view of the above problems, and an object thereof is to provide a stacked semiconductor device having a structure in which semiconductor chips having the same or substantially the same chip area can be stacked easily.

  In order to achieve the above object, a stacked semiconductor device according to the present invention is a stacked semiconductor device in which semiconductor chips are mounted on both front and back surfaces of a die bonding member, and is mounted on the back side of the die bonding member. 1 The front surface of the semiconductor chip and the back surface of the die bonding member are bonded to face each other, and the back surface of the second semiconductor chip mounted on the front surface side of the die bonding member and the surface of the die bonding member are bonded to each other. Then, one or more electrode pads formed on the surface of the first semiconductor chip are connected to the surface side of the corresponding inner lead by a wire, and one or more electrode pads formed on the surface of the second semiconductor chip are connected. It is formed by connecting the electrode pad and the corresponding inner lead surface side with a wire, and each area of the front surface and the back surface of the die bonding member is The area of each of the first semiconductor chip and the second semiconductor chip is smaller than each chip area, and the electrode pad of the first semiconductor chip is a region other than the adhesive surface between the surface of the first semiconductor chip and the back surface of the die bonding member. And the wire connected to the electrode pad of the first semiconductor chip is surrounded by a front surface of the first semiconductor chip, a back surface of the second semiconductor chip, and an outer surface of the die bonding member. The first feature is that the light enters the electrode pad of the first semiconductor chip obliquely from above.

  Furthermore, in addition to the first feature described above, the stacked semiconductor device according to the present invention has the second feature that the chip areas of the first semiconductor chip and the second semiconductor chip are the same or substantially the same. To do.

  Furthermore, in the stacked semiconductor device according to the present invention, in addition to the first or second feature, the front surface of the first semiconductor chip and the back surface of the die bonding member are bonded with an adhesive or an adhesive tape. This is the third feature.

  Furthermore, in the stacked semiconductor device according to the present invention, in addition to any one of the first to third features, the back surface of the second semiconductor chip and the surface of the die bonding member are bonded with an adhesive or an adhesive tape. This is a fourth feature.

  Furthermore, in the stacked semiconductor device according to the present invention, in addition to any one of the first to fourth features, a fifth aspect is that the die bonding member is a rectangular die pad supported by a suspension lead. Features.

  Furthermore, in the stacked semiconductor device according to the present invention, in addition to any of the first to fourth features, the die bonding member is not provided with a rectangular die pad, but only a suspension lead for supporting the die pad. The sixth feature is that it is formed as described above.

  Furthermore, in the stacked semiconductor device according to the present invention, in addition to the fifth feature, a plurality of the electrode pads of the first semiconductor chip are arranged on a peripheral edge portion of the surface of the first semiconductor chip, and the die pad includes The seventh feature is that the area is smaller than a maximum rectangular area surrounded by the plurality of electrode pads of the first semiconductor chip.

  Furthermore, in the stacked semiconductor device according to the present invention, in addition to any of the fifth to seventh features, the suspension lead is provided at a position that does not overlap the electrode pad of the first semiconductor chip. Is the eighth feature.

  According to the stacked semiconductor device having any one of the above characteristics, the area of the front surface and the back surface of the die bonding member is smaller than the chip areas of the first semiconductor chip and the second semiconductor chip. And a recessed space having a height equal to the sum of the thickness of the adhesive material for bonding the die bonding member and each semiconductor chip is formed in the peripheral portion of the first semiconductor chip mounted on the back side of the die bonding member. The electrode pad formed on the peripheral edge of the surface of the first semiconductor chip is exposed to the recessed space, and the wire passes through the recessed space and enters the electrode pad of the first semiconductor chip obliquely from above. Therefore, the wire can be connected between the electrode pad and the inner lead without interfering with the peripheral portion of the second semiconductor chip mounted on the surface side of the die bonding member. As a result, it is possible to provide a stacked semiconductor device in which semiconductor chips having the same or substantially the same chip area are stacked.

  In addition, since any electrode pad of the first semiconductor chip and the second semiconductor chip can be disposed at the peripheral portion of the chip surface, the length of the wire connecting the electrode pad and the inner lead is shortened. The resulting contact failure can be reduced, the inductive component parasitic on the wire can be reduced, the noise caused by the parasitic inductive component can be reduced, and the electrical characteristics can be improved.

  In the description of the present invention, the chip surface or the surface of the semiconductor chip means a surface on the side where circuit elements such as semiconductor elements are formed with respect to the substrate of the semiconductor chip. Therefore, the back surface of the semiconductor chip means a surface opposite to the front surface of the semiconductor chip. In addition, the peripheral portion of the chip surface means a region that is recessed from each end of the semiconductor chip toward the center of the chip.

  In particular, according to the stacked semiconductor device of the third feature, the above-described effects can be obtained by using an adhesive or an adhesive tape as an adhesive material for bonding the front surface of the first semiconductor chip and the back surface of the die bonding member. Can do. In addition, since the adhesive material is coated with an insulating protective film on the surface of the first semiconductor chip, both a conductive material and an insulating material can be used.

  In particular, according to the stacked semiconductor device of the fourth feature, the above-described effects can be obtained by using an adhesive or an adhesive tape as an adhesive material for bonding the back surface of the second semiconductor chip and the surface of the die bonding member. Can do. Further, the adhesive material can use both a conductive material and an insulating material. Further, when the tape material of the adhesive tape is insulative, the electrode tape of the first semiconductor chip in the case where the back surface of the second semiconductor chip is conductive by applying the adhesive tape to the entire back surface of the second semiconductor chip. Can be prevented from being short-circuited due to the wire connected to contact with the back surface of the second semiconductor chip.

  In particular, according to the stacked semiconductor device having the eighth feature, the wire can be connected to the electrode pad of the first semiconductor chip without being interfered by the suspension lead, and the above-described effects can be obtained.

  Furthermore, the manufacturing method of the stacked semiconductor device according to the present invention is the manufacturing method of the stacked semiconductor device according to the first feature, wherein the surface of the first semiconductor chip and the surface of the first semiconductor chip are disposed on the back surface side of the die bonding member. A first die bonding step in which the back surface of the die bonding member is opposed to each other, and one or more electrode pads formed on the surface of the first semiconductor chip after the first die bonding step; A first wiring step for connecting the front surface side of the lead with a wire, and after the first wiring step, the back surface of the second semiconductor chip and the front surface of the die bonding member are opposed to the front surface side of the die bonding member. Formed on the surface of the second semiconductor chip after the second die bonding step and the second die bonding step. One or a plurality of electrode pads, and a second wiring step for connecting the surface side of the corresponding inner leads by wires, the sequential first feature to run the for.

  According to the manufacturing method of the stacked semiconductor device having the first feature, the second semiconductor chip is not bonded to the surface side of the die bonding member during the first wiring process, so the upper side of the electrode pad of the first semiconductor chip. In the open state, the wire can be easily connected to the electrode pad, and the stacked semiconductor device according to the present invention having the above-described effects can be manufactured.

  Furthermore, in addition to the first feature, the method for manufacturing a stacked semiconductor device according to the present invention extends, in the first wiring step, the wire from the surface of the electrode pad obliquely upward to the outside. The second feature is to connect.

  According to the method for manufacturing a stacked semiconductor device of the second feature, the wire connected to the electrode pad of the first semiconductor chip in the first wiring step can pass through the height of the recessed space, and the first wiring In the second die bonding step subsequent to the step, when the back surface of the second semiconductor chip and the front surface of the die bonding member are bonded to face each other, the wire connected to the electrode pad of the first semiconductor chip is connected to the second semiconductor chip. It is possible to prevent occurrence of poor adhesion between the back surface of the second semiconductor chip and the surface of the die bonding member or poor connection of the wires by contacting the back surface.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a stacked semiconductor device according to the present invention and a manufacturing method thereof (hereinafter, appropriately abbreviated as “device of the present invention” and “method of the present invention”) will be described with reference to the drawings.

<First Embodiment>
As shown in FIG. 1, the device 11 of the present invention mounts two semiconductor chips 1 and 2 having the same chip area on both front and back surfaces of a die pad 3 (corresponding to a die bonding member) and seals them in one resin package. This is a stacked semiconductor device. FIG. 1A is a plan perspective view of the internal structure of the resin-sealed portion of the device 11 of the present invention seen through the top surface of the package, and a part of the second semiconductor chip 2 mounted on the surface side of the die pad 3 ( The upper half of the drawing) is crushed and schematically shows a state in which the die pad 3 located on the back side of the second semiconductor chip 2 and the first semiconductor chip 1 mounted on the back side of the die pad 3 are exposed. FIG. FIG. 1B is a longitudinal sectional view schematically showing a sectional structure of the device 11 of the present invention in the section XX ′ shown in FIG.

  As shown in FIG. 1, the device 11 of the present invention is mounted on the front surface side of the die pad 3 by adhering the front surface of the first semiconductor chip 1 mounted on the back surface side of the die pad 3 to the back surface of the die pad 3. The back surface of the second semiconductor chip 2 and the surface of the die pad 3 are bonded to face each other, and the inner lead 6 corresponding to one or a plurality of electrode pads 5a formed on the front surface peripheral portion of the first semiconductor chip 1 Are connected by a wire 7a, and one or a plurality of electrode pads 5b formed on the peripheral edge of the surface of the second semiconductor chip 2 and the corresponding surface side of the inner lead 6 are connected by a wire 7b.

  The die pad 3 has a rectangular shape smaller than that of the first semiconductor chip 1 and the second semiconductor chip 2 and is supported by suspension leads 9 at four corners in the example shown in FIG. Outside the resin-encapsulated portion, the inner lead 6 is supported as an outer lead (not shown) together with the suspension lead 9 and connected to an outer frame (not shown) of the lead frame before resin encapsulation. The lead frame including the die pad 3, the inner lead 6, and the suspension lead 9 is formed using a known metal material such as an Fe—Ni alloy material such as 42 alloy or a Cu alloy material.

  The first semiconductor chip 1 and the second semiconductor chip 2 mounted on the device 11 of the present invention are provided with respective electrode pads 5a and 5b on the periphery of the chip surface. The vertical and horizontal dimensions of the die pad 3 are the distances from the chip end side of the first semiconductor chip 1 to the position closest to the inside of the electrode pad 5a with respect to the vertical and horizontal dimensions of the first semiconductor chip 1 during wire bonding. The length is more than twice as long as a margin added in consideration of the positioning accuracy. Thus, when the front surface of the first semiconductor chip 1 and the back surface of the die pad 3 are bonded to face each other, the electrode pads 5 a arranged on the peripheral edge of the front surface of the first semiconductor chip 1 are shielded by the die pad 3. No wire bonding is possible.

  In the present embodiment, the electrode pads 5 a are not disposed at the positions of the four suspension leads 9 that support the die pad 3 at the four corners, that is, at the four corners of the surface of the first semiconductor chip 1. The pad 5a is not shielded by the suspension lead 9, and wire bonding is possible. Note that when the electrode pads 5a are arranged at the four corners of the surface of the first semiconductor chip 1, the position of the suspension leads 9 may be adjusted to a location where the distance between the other electrode pads 5a is large.

  As shown in FIG. 1B, in the device 11 of the present invention, the two semiconductor chips 1 and 2 having the same chip area are bonded to both the front and back surfaces of the die pad 3 having a smaller area than the first semiconductor chip 1. A recessed space 12 surrounded by the front surface, the back surface of the second semiconductor chip 2, and the outer surface of the die pad 3 is formed in the periphery except for the suspension leads 9 of the die pad 3, and is a wire connected to the electrode pad 5 a of the first semiconductor chip 1. 7a passes through the recessed space 12 and enters the electrode pad 5a obliquely from above, so that the wire 7a is not interfered with the back surface of the second semiconductor chip 2 positioned above the electrode pad 5a. Wire bonding is possible.

  Next, a method for manufacturing the device 11 of the present invention will be described. First, as shown in FIG. 2 (A), the front surface of the first semiconductor chip 1 and the back surface of the die pad 3 are opposed to the back surface side of the die pad 3, and the adhesive 4a is applied and bonded, and then cured. And bond (first die bonding step). As the adhesive 4a used in the present embodiment, for example, an organic resin adhesive material can be used, but both a conductive adhesive material and an insulating adhesive material can be used.

  Subsequently, as shown in FIG. 2B, the electrode pads 5a formed on the surface peripheral edge portion of the first semiconductor chip and the surface side of the corresponding inner lead 6 are connected by the wire 7a (first wiring process). . At this time, the wire 7a is connected so as to extend outward and obliquely upward from the surface of the electrode pad 5a. In the present embodiment, it is necessary to wire the wire 7a by entering the electrode pad 5a at an angle passing through the recessed space 12 formed by the second die bonding step of the next step. For example, ultrasonic wire bonding or the like The wedge bonding method can be used.

  Subsequently, as shown in FIG. 2C, the back surface of the second semiconductor chip 2 and the front surface of the die pad 3 are opposed to the front surface side of the die pad 3, and the adhesive 4b is applied and bonded, and then cured. And bond (second die bonding step). As the adhesive 4b used in the present embodiment, for example, an organic resin-based adhesive material can be used, but both a conductive adhesive material and an insulating adhesive material can be used and used in the first die bonding step. The same adhesive as the adhesive 4a can be used.

  Subsequently, as shown in FIG. 2D, the electrode pads 5b formed on the surface peripheral edge portion of the second semiconductor chip 2 and the surface side of the corresponding inner leads 6 are connected by wires 7b (second wiring process). ). Here, the connecting point between the surface side of the inner lead 6 and the wire 7b is outside (closer to the outer lead) than the connecting point between the surface side of the inner lead 6 and the wire 7a in the first wiring step, so that the existing wire 7a. The wire 7b can be bonded to the surface side of the inner lead 6 without interference.

  Subsequently, the semiconductor chips 1 and 2, the die pad 3, the inner leads 6, and the wires 7 a and 7 b are sealed with the resin 8 and molded. Thereafter, the resin-molded device 11 of the present invention is cut and separated from the outer frame (not shown) of the lead frame.

Second Embodiment
Next, a second embodiment of the device of the present invention will be described. As shown in FIG. 3, the inventive device 11a of the second embodiment has one resin package in which two semiconductor chips 1 and 2 having the same chip area are mounted on both front and back surfaces of a non-rectangular die bonding member 13, respectively. This is a stacked semiconductor device sealed inside. FIG. 3 is a plan perspective view of the internal structure of the resin-sealed portion of the device 11a of the present invention seen through the top surface of the package, and a part of the second semiconductor chip 2 mounted on the surface side of the die bonding member 13 (drawing). The upper half of the upper part) is crushed so that the die bonding member 13 located on the back side of the second semiconductor chip 2 and the first semiconductor chip 1 mounted on the back side of the die bonding member 13 are exposed. FIG.

  As shown in FIG. 3, the device 11 a of the present invention adheres the front surface of the first semiconductor chip 1 mounted on the back surface side of the die bonding member 13 and the back surface of the die bonding member 13 so as to face each other. The back surface of the second semiconductor chip 2 mounted on the front surface side of the first semiconductor chip 1 and the surface of the die bonding member 13 are bonded to face each other, and one or a plurality of electrode pads 5a formed on the peripheral edge of the front surface of the first semiconductor chip 1; The corresponding inner lead 6 is connected to the surface side of the inner lead 6 by a wire 7a, and one or more electrode pads 5b formed on the peripheral edge of the surface of the second semiconductor chip 2 are connected to the corresponding inner lead 6 by the wire 7b. Connected and formed.

  The die bonding member 13 has the same function as the die pad 3 in the first embodiment. In this embodiment, the four suspension leads 9 extend in a wide state toward the center of the package, and the die pad 3 It has an “X” shape within the rectangular region where the X exists, and is supported by each suspension lead 9 at each end of the X shape. The suspension lead 9 and the inner lead 6 are the same as in the first embodiment. The lead frame including the die bonding member 13, the inner lead 6, and the suspension lead 9 is formed using a known metal material such as a Fe-Ni alloy material such as 42 alloy or a Cu alloy material. ing.

  As in the first embodiment, the first semiconductor chip 1 and the second semiconductor chip 2 mounted on the device 11a of the present invention have the electrode pads 5a and 5b arranged on the periphery of the chip surface, respectively. Here, the vertical and horizontal dimensions of the rectangle circumscribing the X-shaped die bonding member 13 are different from the vertical and horizontal dimensions of the first semiconductor chip 1 from the chip edge of the first semiconductor chip 1 to the electrode pad 5a. The distance to the position closest to the inside of the chip is at least twice as long as the added margin considering the alignment accuracy at the time of wire bonding. However, unlike the first embodiment, the rectangle circumscribing the X-shaped die bonding member 13 can be made larger than the first semiconductor chip 1 and the second semiconductor chip 2. That is, the position of the electrode pad 5a disposed on the surface of the first semiconductor chip 1 may be set so as not to overlap with the die bonding member 13. The size and shape of the die bonding member 13 are matched to the arrangement of the electrode pad 5a. Can be changed as appropriate.

  In the inventive device 11a as well, as in the first embodiment, the two semiconductor chips 1 and 2 having the same chip area are bonded to both the front and back surfaces of the die bonding member 13 so that the surface of the first semiconductor chip 1 and the first semiconductor chip 1 (2) A recessed space 12 surrounded by the back surface of the semiconductor chip 2 and the outer surface of the die bonding member 13 is formed around the die bonding member 13 except for the suspension leads 9, and is connected to the electrode pads 5a of the first semiconductor chip 1. Since the wire 7a passes through the recessed space 12 and enters from the upper side toward the electrode pad 5a, the wire 7a is not interfered with the back surface of the second semiconductor chip 2 positioned above the electrode pad 5a. Wire bonding with 5a is possible. Furthermore, since the manufacturing method of this invention apparatus 11a is the same as that of 1st Embodiment, the overlapping description is omitted.

<Another embodiment>
Hereinafter, another embodiment of the device of the present invention will be described.

  <1> In the above embodiments, in the first die bonding step, the front surface of the first semiconductor chip 1 and the back surface of the die pad 3 (or the die bonding member 13) are opposed to each other, and the adhesive 4a is applied and pasted. Although the case where it hardens | cures after bonding and adhere | attaches was assumed, as shown in FIG. 4, it is preferable to replace with the adhesive agent 4a and to use adhesive tapes 10a, such as a polyimide tape with which the adhesive agent was apply | coated. In this case, an adhesive tape 10a having the same shape as that of the die pad 3 (or die bonding member 13) is prepared in advance on the back surface of the die pad 3 (or die bonding member 13), and the first semiconductor chip is prepared. The process can be simplified by thermocompression bonding the surface of 1 to the surface of the adhesive tape 10a.

  Similarly, in the second die bonding step, the back surface of the second semiconductor chip 2 and the front surface of the die pad 3 (or the die bonding member 13) are made to face each other, and the adhesive 4b is applied and bonded, and then cured. However, instead of the adhesive 4b, an adhesive tape 10b such as a polyimide tape to which an adhesive is applied may be used.

  <2> In each of the above embodiments, it is assumed that the two semiconductor chips 1 and 2 have the same chip area. However, the chip areas do not have to be completely matched, and the same die pad 3 (or die bonding member). 13) It may be substantially the same area as long as it is larger and can be sealed with resin.

  The two semiconductor chips 1 and 2 do not have to be exactly the same semiconductor chip. For example, one may be a logic device and the other may be a memory device. In this case, if the signals input or output by the electrode pads 5a and 1b of the two semiconductor chips 1 and 2 are different, the inner leads 6 and the wires 7a and 7b provided exclusively for the respective electrodes are connected. You can do it.

  <3> In the above embodiments, the case where the number of the suspension leads 9 is four has been described as an example. However, the number of the suspension leads 9 may be two, three, or five or more.

  <4> In the above embodiments, the processing shape of the outer lead connected to the inner lead 6 is not particularly mentioned, but the present invention apparatus is DIP, SIP, ZIP, SOJ, SSOP, TSOP, QFP, TQFP. It is applicable to various package shapes such as SON, QFN, and outer lead shapes.

  The stacked semiconductor device and the manufacturing method of the stacked semiconductor device according to the present invention can be used for a stacked semiconductor device in which a plurality of semiconductor chips having the same chip area or similar chip areas are stacked and mounted in a package. is there.

Partially fractured plan perspective view (A) and longitudinal sectional view (B) schematically showing the internal structure of a resin-sealed portion in the first embodiment of the stacked semiconductor device according to the present invention Process sectional drawing which shows typically the cross-section of the laminated semiconductor device in the middle of each process of the manufacturing method of the laminated semiconductor device which concerns on this invention Partially fractured plan perspective view schematically showing the internal structure of a resin-sealed portion in a second embodiment of a stacked semiconductor device according to the present invention The longitudinal cross-sectional view which shows typically the cross-section of the resin sealing part in another embodiment of the laminated semiconductor device which concerns on this invention 1 is a longitudinal cross-sectional view schematically showing a cross-sectional structure of a first conventional stacked semiconductor device A longitudinal sectional view schematically showing a sectional structure of a stacked semiconductor device having a second conventional structure A longitudinal sectional view schematically showing a sectional structure of a third conventional stacked semiconductor device

Explanation of symbols

11, 11a: Stacked semiconductor device according to the present invention 1: First semiconductor chip 2: Second semiconductor chip 3: Die pad (die bonding member)
4a, 4b: Adhesive 5a: Electrode pad of the first semiconductor chip 5b: Electrode pad of the second semiconductor chip 6: Inner lead 7a, 7b: Wire 8: Resin 9: Suspended lead 10a, 10b: Adhesive tape 12: Recessed Space 13: Die bonding member 21, 31, 41: Semiconductor chip mounted on the front side of the die pad 22, 32, 42: Semiconductor chip mounted on the back side of the die pad 23, 33, 43: Die pad 24a, 24b, 34a 44a: Adhesive 25a, 25b, 35a, 35b, 45a, 45b: Electrode pad 26, 36, 46: Inner lead 27a, 27b, 37a, 37b, 47a, 47b: Wire 28, 38, 48: Resin 34b, 44b : Adhesive tape

Claims (10)

A stacked semiconductor device in which a semiconductor chip is mounted on each of the front and back surfaces of a die bonding member,
Adhering the front surface of the first semiconductor chip mounted on the back surface side of the die bonding member and the back surface of the die bonding member facing each other,
Adhering the back surface of the second semiconductor chip mounted on the surface side of the die bonding member and the surface of the die bonding member facing each other,
Connecting one or more electrode pads formed on the surface of the first semiconductor chip to the surface side of the corresponding inner lead with a wire;
Formed by connecting one or more electrode pads formed on the surface of the second semiconductor chip to the surface side of the corresponding inner lead with a wire;
Each area of the front surface and the back surface of the die bonding member is smaller than each chip area of the first semiconductor chip and the second semiconductor chip,
The electrode pad of the first semiconductor chip is provided in a region other than the adhesive surface of the surface of the first semiconductor chip with the back surface of the die bonding member;
The wire connected to the electrode pad of the first semiconductor chip passes through a recessed space surrounded by the surface of the first semiconductor chip, the back surface of the second semiconductor chip, and the outer surface of the die bonding member. A stacked semiconductor device, wherein the semiconductor device enters from the upper side toward the electrode pad of the first semiconductor chip.   2. The stacked semiconductor device according to claim 1, wherein the chip areas of the first semiconductor chip and the second semiconductor chip are the same or substantially the same.   3. The stacked semiconductor device according to claim 1, wherein a front surface of the first semiconductor chip and a back surface of the die bonding member are bonded by an adhesive or an adhesive tape.   4. The stacked semiconductor device according to claim 1, wherein a back surface of the second semiconductor chip and a surface of the die bonding member are bonded with an adhesive or an adhesive tape. 5.   5. The stacked semiconductor device according to claim 1, wherein the die bonding member is a rectangular die pad supported by a suspension lead.   5. The stacked semiconductor device according to claim 1, wherein the die bonding member is not provided with a rectangular die pad but is formed only with a suspension lead for supporting the die pad. 6. . A plurality of the electrode pads of the first semiconductor chip are disposed on the peripheral edge of the surface of the first semiconductor chip;
6. The stacked semiconductor device according to claim 5, wherein the die pad is smaller than a maximum rectangular region surrounded by the plurality of electrode pads of the first semiconductor chip.   The stacked semiconductor device according to claim 5, wherein the suspension lead is provided at a position that does not overlap the electrode pad of the first semiconductor chip. A method of manufacturing a stacked semiconductor device according to claim 1,
A first die bonding step of bonding the front surface of the first semiconductor chip and the back surface of the die bonding member opposite to each other on the back surface side of the die bonding member;
After the first die bonding step, a first wiring step of connecting one or more electrode pads formed on the surface of the first semiconductor chip and the surface side of the corresponding inner lead with a wire;
A second die bonding step of bonding the back surface of the second semiconductor chip and the surface of the die bonding member opposite to each other on the surface side of the die bonding member after the first wiring step;
After the second die bonding step, a second wiring step of sequentially connecting one or a plurality of electrode pads formed on the surface of the second semiconductor chip and the surface side of the corresponding inner lead with a wire is sequentially executed. A method for manufacturing a stacked semiconductor device, comprising: 10. The method of manufacturing a stacked semiconductor device according to claim 9, wherein in the first wiring step, the wires are connected so as to extend outward and obliquely upward from the surface of the electrode pad. 11.