JP2007281011A - Analog and digital mixed mounted semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To permit the reduction of crosstalk noise and minimizing of chip size. <P>SOLUTION: The analog and digital mixed mounted semiconductor device is provided with a semiconductor chip 30 wherein an analog circuit 32 and a digital circuit 31 are mounted in a mixed state, a plurality of digital pads 35 which are arranged around the periphery of the semiconductor chip 30 and are connected with the digital circuit 31, a plurality of analog pads 33 which are arranged inside the digital pads 35 in the semiconductor chip 30 and are connected with the analog circuit 32, a plurality of digital posts 21 which are provided adjacent to the semiconductor chip 30 and are connected with the digital circuit 31 by means of a digital wire 37, and a plurality of second analog posts 22 which are arranged adjacent to the semiconductor chip 30 and are connected with the analog circuit 32 by means of a digital wire 38. The digital posts 21 and the analog post 22 are arranged at different arrangement, respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an analog / digital mixed semiconductor device having a semiconductor chip in which an analog circuit portion and a digital circuit portion are mixedly mounted, and in particular, a plurality of analog circuit portion connecting and digital circuit portion connecting provided near the semiconductor chip. The present invention relates to an arrangement structure of posts and an arrangement structure of a plurality of pads for connecting electrodes provided on a semiconductor chip.

  Conventionally, as a technique related to an analog / digital mixed semiconductor device, for example, there are those described in the following documents.

JP 2003-37173 A

  Patent Document 1 describes a technique related to an analog / digital mixed semiconductor device having a semiconductor chip in which an analog circuit section that performs analog processing and a digital circuit section that performs digital processing are mixedly mounted. In this patent document 1, the analog circuit unit receives the digital noise from the digital circuit unit and eliminates the inconvenience that the quality of the analog signal deteriorates, and the coupling noise generated on the wiring of the analog circuit unit and on the wiring In order to suppress the loss, the analog circuit portion is disposed in the peripheral portion of the semiconductor chip, and the digital circuit portion is disposed in the central portion of the semiconductor chip.

  FIGS. 5 (1) to (3) are schematic configuration diagrams of an analog / digital mixed semiconductor device as in Patent Document 1, and FIG. 5 (1) is a diagram showing a layout configuration example viewed from the plane. (2) is an enlarged view of the crossing portion A of the wiring in FIG. 1 (1), and FIG. 3 (3) is an enlarged view of the parallel running portion B of the wiring in FIG.

  In the analog / digital mixed semiconductor device shown in FIG. 5A, a semiconductor chip 10 is fixed on a substrate 1 such as a ball grid array (hereinafter referred to as “BGA”). In the periphery of the semiconductor chip 10, a plurality of digital circuit posts (hereinafter referred to as “digital posts”) 2 and a plurality of analog circuit posts (hereinafter referred to as “electrode posts”) as electrode portions provided on the substrate 1 are disposed on the periphery of the substrate 1. "Analog post") 3 is provided. The semiconductor chip 10 includes a digital circuit section 11 that performs digital processing and an analog circuit section 12 that performs analog processing. The digital circuit section 11 is disposed at the center of the semiconductor chip 10 and an analog circuit is disposed at the periphery. The part 12 is arranged. In FIG. 5, for convenience of illustration, a diagram in which the digital circuit unit 11 and the analog circuit unit 12 are arranged at the center of the semiconductor chip 10 is illustrated.

  Between the analog circuit section 12 and the substrate 1, a plurality of input / output buffer circuits (hereinafter referred to as “I / O buffer circuits”) 13 are arranged near the analog circuit section 12. A plurality of digital circuit pads (hereinafter referred to as “digital pads”) 14 and a plurality of analog circuit pads (hereinafter referred to as “analog pads”) 15 are arranged between the semiconductor chip and the periphery of the semiconductor chip. The I / O buffer circuit 13 is electrically connected between the digital circuit section 11 and the digital pad 14 by a digital wiring (hereinafter referred to as “digital wiring”) 16 formed in the semiconductor chip. It has a function of holding an input / output signal for the unit 11. The analog circuit portion 12 and the analog pad 15 are electrically connected by an analog wiring (hereinafter referred to as “analog wiring”) 17 formed in the semiconductor chip 10.

  As shown in FIG. 5B, at the intersection A between the digital wiring 16 and the analog wiring 17, for example, the digital wiring 16 is formed in the lower layer (first layer) in the semiconductor chip 10, and the upper layer ( In the second layer), an analog wiring 17 is formed via an insulating layer so that they are not in electrical contact with each other. Further, as shown in FIG. 5 (3), in the parallel running portion B of the digital wiring 16 and the analog wiring 17, since they are not in electrical contact, the digital wiring 16 and the analog wiring 17 are in the same layer (for example, It may be formed in the first layer).

  The digital pad 14 connected to the digital wiring 16 is electrically connected to the digital post 2 by a digital wire (hereinafter referred to as “digital wire”) 18. The analog pad 15 connected to the analog wiring 17 is electrically connected to the analog post 3 by an analog wire (hereinafter simply referred to as “analog wire”) 19.

  For example, the entire surface of the analog / digital mixed semiconductor device having such a structure is covered with a resin mold or the like. The internal digital circuit unit 11 and the analog circuit unit 12 exchange signals and the like with the outside through the posts 2 and 3.

  However, the conventional analog / digital mixed semiconductor device as shown in FIG. 5 has the following problems (a) and (b).

  (A) As described in Patent Document 1, in the semiconductor chip 10 of FIG. 5, the analog circuit unit 12 receives the digital noise from the digital circuit unit 11 and eliminates the inconvenience that the quality of the analog signal deteriorates. At the same time, in order to suppress the coupling noise generated on the wiring of the analog circuit section 12 and the loss on the wiring, the analog circuit section 12 is arranged in the peripheral portion of the semiconductor chip 10, and the digital circuit section 11 is connected to the semiconductor chip 10. Located in the center. In general, the semiconductor chip 10 cannot increase the number of pads when the chip size is reduced, and it is difficult to reduce the size of the semiconductor chip 10 when the number of pads is increased.

  In this way, when the chip size depends on the number of pads, as in Patent Document 1, only the restriction due to the circuit arrangement of the digital circuit unit 11 and the analog circuit unit 12 causes the analog circuit unit 12 to the analog pad 15 to be limited. If the interval is shortened, the digital pad 14 adjacent to the analog pad 15 in the pad group located on the analog circuit unit 12 side is also arranged. Thus, when the digital pad 14 is used, as shown in FIGS. 5 (2) and 5 (3), the intersection A with the analog wiring 17 and the parallel running with the analog wiring 17 in the I / O buffer circuit 13 are performed. In part B, crosstalk noise between wirings is generated, which poses a problem in analog characteristics.

  (B) FIG. 6 is a schematic configuration diagram of an analog / digital mixed semiconductor device obtained by improving FIG. 5 considered to solve the problem (a).

  In this analog / digital mixed semiconductor device, the digital pad 14 disposed on the analog circuit section 12 side is unused, and an additional digital pad 14a and an additional I / O buffer circuit 13a are provided. However, when the additional digital pad 14a and the additional I / O buffer circuit 13a are installed in this manner, the chip size depends on the number of pads, which causes a problem that the chip size increases.

  From these points (a) and (b), in the analog / digital mixed semiconductor device, the number of pads can be increased by considering the crosstalk between the analog circuit unit 12 and the analog pad 15 only with the conventional circuit arrangement structure. There was a problem that restrictions would appear.

  In the analog / digital mixed semiconductor device of the present invention, a semiconductor chip in which an analog circuit section for performing analog processing and a digital circuit section for performing digital processing are mounted together is provided in the vicinity of the semiconductor chip, and the digital circuit section is electrically connected. A plurality of first posts for digital circuits connected to each other and a plurality of second posts for analog circuits provided in the vicinity of the semiconductor chip and electrically connected to the analog circuit portion. The plurality of first posts and the plurality of second posts are arranged in different arrays.

  According to the first and fourth aspects of the invention, since the first post and the second post are arranged in different arrays, electrical interference on the substrate can be suppressed.

  According to the second aspect of the present invention, since the first pad for the digital circuit and the second pad for the analog circuit are provided inside the first pad, the first pad disposed on the periphery of the semiconductor chip is provided. All the pads of 1 can be used effectively, and the chip size can be reduced.

  According to the third and fourth aspects of the invention, since the first conductor (wire) can be shortened, the influence of the inductance of the first conductor (wire) on the analog circuit portion can be reduced.

  According to the fifth aspect of the present invention, the wire non-connecting pad is provided below the wire connecting the first post and the second pad and between the first pad and the second pad. Since it is disposed, crosstalk noise to the analog signal can be eliminated, and further, bonding can be facilitated.

  The analog / digital mixed semiconductor device includes a semiconductor chip in which an analog circuit unit that performs analog processing and a digital circuit unit that performs digital processing are mixedly mounted, and a peripheral portion of the semiconductor chip, and is electrically connected to the digital circuit unit. A plurality of first pads for digital circuits connected to each other, and a plurality of pads for analog circuits disposed inside the plurality of first pads in the semiconductor chip and electrically connected to the analog circuit section A plurality of first posts for a digital circuit provided in the vicinity of the semiconductor chip and electrically connected to the digital circuit section via a first conductor, and the semiconductor chip And a plurality of second posts for an analog circuit that are electrically connected to the analog circuit portion through a second conductor. The plurality of first posts and the plurality of second posts are arranged in different arrays.

(Configuration of Example 1)
FIGS. 1A and 1B are schematic configuration diagrams of an analog / digital mixed semiconductor device showing a first embodiment of the present invention, and FIG. 1A is a diagram showing a layout configuration example viewed from a plane. FIG. 2B is a schematic enlarged cross-sectional view showing the periphery of the semiconductor chip of FIG.

  In FIG. 1, for example, a configuration example using a staggered pad structure of an embedded array in an analog / digital mixed semiconductor device in which a music reproduction function or the like is integrated is shown.

  In this analog / digital mixed semiconductor device, a substantially rectangular semiconductor chip 30 is fixed on a substrate 20 such as a BGA. Around the semiconductor chip 30, a digital substrate unit 20-1 and an analog substrate unit 20-2 are provided around the substrate 20, and a plurality of first posts (for example, digital posts) are provided on the digital substrate unit 20-1. ) 21 and a plurality of second posts (for example, analog posts) 22 are disposed on the analog board portion 20-2.

  The plurality of digital posts 21 are arranged at a predetermined pitch on the straight line L1 along the periphery of the semiconductor chip and closer to the semiconductor chip. The plurality of analog posts 22 are arranged at a predetermined pitch on a straight line L2 disposed substantially parallel to the straight line L1 near the substrate peripheral portion outside the straight line L1. The plurality of digital posts 21 near the semiconductor chip are arranged so as to be spaced apart from each other so as not to cause electrical interference with the plurality of analog posts 22 near the periphery of the substrate.

  The semiconductor chip 30 includes a digital circuit unit 31 that performs digital processing such as music reproduction control, and analog / digital conversion (hereinafter referred to as “D / A conversion”) that converts digital data into analog data that becomes sound. An analog circuit section 32 that performs processing is mixedly mounted, a digital circuit section 31 is disposed in the central portion of the semiconductor chip 30, and an analog circuit section 32 is disposed in the peripheral portion. In FIG. 1, for convenience of illustration, a diagram in which a digital circuit unit 31 and an analog circuit unit 32 are arranged at the center of the semiconductor chip 30 is illustrated.

  A plurality of second pads (for example, analog output pads) 33 are arranged on the analog circuit unit 32 at a predetermined pitch, and output signals from the analog circuit unit 32 are output from the analog output pads 33. It has become. A plurality of I / O buffer circuits 34 are disposed near the analog circuit section 32 between the analog circuit section 32 and the semiconductor chip periphery, and a plurality of I / O buffer circuits 34 and the semiconductor chip periphery are disposed between the plurality of I / O buffer circuits 34 and the semiconductor chip periphery. Two first pads (for example, digital pads) 35 are arranged in a zigzag pattern in an embedded array.

  The I / O buffer circuit 34 is electrically connected between the digital circuit unit 31 and the digital pad 35 by a digital wiring 36 formed in the semiconductor chip 30 and holds an input / output signal for the digital circuit unit 31. It has functions such as The plurality of digital pads 35 and the plurality of digital posts 21 positioned outside the plurality of digital pads 35 are electrically connected by first conductors (for example, digital wires) 37, respectively. Between the plurality of analog posts 22 positioned outside the digital post 21 and the plurality of analog output pads 33, second conductors (for example, analog wires) 38 disposed on the digital wires 37 are respectively provided. Electrically connected.

  For example, the entire surface of the analog / digital mixed semiconductor device having such a structure is covered with a resin mold or the like.

(Operation of Example 1)
For example, when a digital signal is input from the external terminal to the digital post 21, the input digital signal is sent to the digital pad 35 through the digital wire 37, and from the digital pad 35 to the digital wiring 36 in the semiconductor chip. The data is sent to the I / O buffer circuit 34 and held in the I / O buffer circuit 34. The digital signal held in the I / O buffer circuit 34 is sent to the digital circuit unit 31 through the digital wiring 36 in the semiconductor chip at a predetermined timing, and the digital circuit unit 31 performs predetermined digital processing.

  The processing result of the digital circuit unit 31 is subjected to analog processing such as D / A conversion into an analog signal by the analog circuit unit 32, and the analog signal of this processing result is output from the analog output pad 33. This analog signal is sent to the analog post 22 through the analog wire 38 and output to the outside through the external terminal.

(Effect of Example 1)
According to the first embodiment, since the plurality of digital pads 35 are arranged at the peripheral portion of the semiconductor chip 30 and the plurality of analog output pads 33 are arranged inside thereof, the plurality of digital pads arranged at the peripheral portion of the semiconductor chip. All 35 can be used effectively, and the effect of avoiding an increase in the size of the semiconductor chip can be obtained. Since the distance between the analog wire 38 and the digital wire 37 is larger than that between the analog wiring and the digital wiring 36 in the adjacent semiconductor chip in the layout, the digital pad 35 is provided at the periphery of the semiconductor chip. Even if it is arranged, an effect of reducing the influence of crosstalk noise can be obtained. Further, a plurality of analog posts 22 are arranged around the periphery of the substrate 20, and a plurality of digital posts 21 are arranged on the inner side, and a distance is provided between the posts 22, 21. The effect of suppressing is obtained.

  In the first embodiment, there is a possibility that interference may occur between the digital wire 37 and the analog wire 38, where interference between the digital signal and the analog signal is weak. In the second embodiment, this is solved.

(Configuration of Example 2)
FIG. 2 is a schematic configuration diagram of an analog / digital mixed semiconductor device showing Embodiment 2 of the present invention. Elements common to those in FIG. 1 showing Embodiment 1 are denoted by common reference numerals. .

  The analog / digital mixed semiconductor device of the second embodiment is different from the device of the first embodiment in that wires for electrically connecting sections of the plurality of analog posts 22 on the substrate 20 from the plurality of analog output pads 33 are used. The plurality of digital pads 35 located below are used as test signal pads (hereinafter referred to as “test pads”) 35a for executing a test of a large scale integrated circuit (LSI) or the like instead of the digital signals. It is. Among the pads 35 provided on each side of the chip 30, there are test and normal operation pads. Among these pads, the test pads are wires for electrically connecting the section from the analog output pad 33 to the analog post 22. Collected in the lower area, pads for normal operation are arranged in other areas. Other configurations are the same as those of the first embodiment.

(Operation of Example 2)
The test pad 35a is a pad used by a semiconductor manufacturer or the like to test the electrical characteristics of the semiconductor chip 30, and is treated as a test mode signal that is not used in the user specifications. During normal operation, a fixed signal (for example, "H" level fixed or "L" level fixed) is input.

(Effect of Example 2)
According to the second embodiment, the digital wire 37 adjacent to the analog wire 38 between the wires is connected to the test pad 35a dedicated to the test. Therefore, when the user uses it, the interference between the analog signal and the digital signal is caused. Will not occur.

  In the second embodiment, as shown in FIG. 1B, in order to connect the analog wire 38 so as to pass over the digital wire 37, a wire bonder having a complicated technique for three-dimensionally bonding wires ( Wire bonding apparatus) is required. In the third embodiment, this is solved.

(Configuration of Example 3)
FIG. 3 is a schematic configuration diagram of an analog / digital mixed semiconductor device showing Embodiment 3 of the present invention. Elements common to those in FIG. 2 showing Embodiment 2 are denoted by common reference numerals. .

  The analog / digital mixed semiconductor device of the third embodiment is different from the device of the second embodiment in that wires for electrically connecting sections of the plurality of analog posts 22 on the substrate 20 from the plurality of analog output pads 33 are used. That is, the plurality of digital pads 35 located below are used as bonding-unnecessary test pads 35b in which bonding is not performed in place of the digital signals. The bonding-unnecessary test pad 35a is, for example, a pad used only for a trimming pad of a regulator (adjuster) or a wafer probing test in a semiconductor manufacturing process. That is, among the test pads, pads that do not require wire bonding are gathered in a region under the wire that electrically connects the section from the analog output pad 33 to the analog post 22. Other configurations are the same as those of the first embodiment.

(Operation of Example 3)
Since the bonding-unnecessary test pad 35b of the third embodiment is not bonded when packaged, the analog wire 38 does not pass over the digital wire 37 as shown in FIG. It is that bonding is done.

(Effect of Example 3)
According to the third embodiment, since it is not necessary to change the loop height between the lower side and the upper side of the digital wire 37 and the analog wire 38, it can be handled by a wire bonder that does not have a complicated technique for three-dimensionally bonding the wires. .

(Configuration of Example 4)
FIG. 4 is a schematic configuration diagram of an analog / digital mixed semiconductor device showing Embodiment 4 of the present invention. Elements common to those in FIG. 1 showing Embodiment 1 are denoted by common reference numerals. .

  In the first embodiment, as an example in which the analog post 22 provided on the substrate 20 is disposed outside the analog circuit unit 32, a configuration example in which the analog post is directly connected to the analog post 22 by the analog wire 38 will be described. is doing.

  On the other hand, in the fourth embodiment, the opposite example, that is, the analog circuit unit 32, two rows of digital on the substrate 20 via the pads (for example, analog output pads) 33 on the semiconductor chip 30. The post 21 and the analog post 22 are connected to the analog post 22 disposed near the semiconductor chip. Details will be described below.

  Around the semiconductor chip 30, an analog substrate unit 20-2 and a digital substrate unit 20-1 are provided around the substrate 20, and a plurality of first posts (for example, analog posts) are provided on the analog substrate unit 20-2. ) 22 and a plurality of second posts (for example, digital posts) 21 are disposed on the digital board 20-1.

  The plurality of analog posts 22 are arranged at a predetermined pitch on the straight line L2 along the periphery of the semiconductor chip and closer to the semiconductor chip. The plurality of digital posts 21 are arranged at a predetermined pitch on a straight line L1 that is disposed substantially parallel to the straight line L2 near the periphery of the substrate outside the straight line L2. The plurality of digital posts 21 near the periphery of the substrate are arranged so as to have a distance that does not cause electrical interference with the plurality of analog posts 22 near the semiconductor chip.

  A digital circuit unit 31 and an analog circuit unit 32 are mixedly mounted on the semiconductor chip 30, the digital circuit unit 31 is disposed at the center of the semiconductor chip 30, and the analog circuit unit 32 is disposed at the peripheral part. 4, as in FIG. 1, for convenience of illustration, a diagram in which the digital circuit unit 31 and the analog circuit unit 32 are arranged at the center of the semiconductor chip 30 is illustrated.

  A plurality of second pads (for example, digital pads) 35 are disposed on the digital circuit unit 31, and the digital pads 35 are electrically connected to the digital posts 21 by a second conductor (for example, digital wires) 37. Connected. Between the analog circuit portion 32 and the peripheral portion of the semiconductor chip, two rows and a plurality of first pads (for example, analog output pads) 33 are arranged in a staggered manner in the embedded array. The analog wiring 39 in the semiconductor chip is electrically connected to the analog circuit unit 32 and is electrically connected to the analog post 22 by a first conductor (for example, analog wire) 38.

  The analog / digital mixed semiconductor device having such a structure is covered with a resin mold or the like as in the first embodiment.

(Operation of Example 4)
For example, when a digital signal is input from the external terminal to the digital post 21, the input digital signal is sent to the digital pad 35 through the digital wire 37, and is input from the digital pad 35 to the digital circuit unit 31. The circuit unit 31 performs predetermined digital processing. The processing result of the digital circuit unit 31 is subjected to analog processing by the analog circuit unit 32, and an analog signal of this processing result is sent to the analog post 22 through the analog wiring 39, the analog output pad 33, and the analog wire 38 in the semiconductor chip. Sent to the outside through an external terminal.

(Effect of Example 4)
According to the fourth embodiment, since the analog wire 38 can be shortened, the influence of the inductance of the analog wire 38 on the analog circuit unit 32 can be reduced.

(Modification)
The present invention is not limited to the first to fourth embodiments, and various usage forms and modifications are possible. For example, the following forms (A) to (C) are available as usage forms and modifications.

  (A) In the embodiment, the configuration example of the layout in the analog / digital mixed semiconductor device in which the music playback function and the like are integrated into the integrated circuit has been described.

  (B) Although the embodiment has been described using the embedded staggered pad, it can be used even when the cell base or the staggered pad is not used. Further, the layout of the circuit and wiring of the semiconductor chip 30 may be changed to a layout other than that shown in the drawing.

  (C) Although the embodiment has been described using the BGA package or the like, it can be used for other mold packages or the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram of an analog / digital mixed semiconductor device showing Embodiment 1 of the present invention. It is a schematic block diagram of the analog / digital mixed semiconductor device which shows Example 2 of this invention. It is a schematic block diagram of the analog / digital mixed semiconductor device which shows Example 3 of this invention. It is a schematic block diagram of the analog / digital mixed semiconductor device which shows Example 4 of this invention. It is a schematic block diagram of the conventional analog / digital mixed semiconductor device. FIG. 6 is a schematic configuration diagram of an analog / digital mixed semiconductor device obtained by improving FIG. 5.

Explanation of symbols

20 Substrate 21 Digital post 22 Analog post 30 Semiconductor chip 31 Digital circuit part 32 Analog circuit part 33 Analog output pad 35 Digital pad 37 Digital wire 38 Analog wire

Claims (5)

A semiconductor chip in which an analog circuit unit for performing analog processing and a digital circuit unit for performing digital processing are mixedly mounted;
A plurality of first posts for a digital circuit provided in the vicinity of the semiconductor chip and electrically connected to the digital circuit unit;
A plurality of second posts for an analog circuit provided in the vicinity of the semiconductor chip and electrically connected to the analog circuit unit;
The analog / digital mixed semiconductor device, wherein the plurality of first posts and the plurality of second posts are arranged in different arrangements. A semiconductor chip in which an analog circuit unit for performing analog processing and a digital circuit unit for performing digital processing are mixedly mounted;
A plurality of first pads for a digital circuit disposed on a peripheral portion of the semiconductor chip and electrically connected to the digital circuit portion;
A plurality of second pads for an analog circuit disposed inside the plurality of first pads in the semiconductor chip and electrically connected to the analog circuit unit;
A plurality of first posts for a digital circuit provided in the vicinity of the semiconductor chip and electrically connected to the digital circuit unit via a first conductor;
A plurality of second posts for an analog circuit provided in the vicinity of the semiconductor chip and electrically connected to the analog circuit section via a second conductor;
The analog / digital mixed semiconductor device, wherein the plurality of first posts and the plurality of second posts are arranged in different arrangements. A semiconductor chip in which an analog circuit unit for performing analog processing and a digital circuit unit for performing digital processing are mixedly mounted;
A plurality of first pads for an analog circuit disposed in a peripheral portion of the semiconductor chip and electrically connected to the analog circuit unit;
A plurality of second pads for a digital circuit disposed inside the plurality of first pads in the semiconductor chip and electrically connected to the digital circuit unit;
A plurality of first posts for an analog circuit provided in the vicinity of the semiconductor chip and electrically connected to the analog circuit section via a first conductor;
A plurality of second posts for a digital circuit provided in the vicinity of the semiconductor chip and electrically connected to the digital circuit unit via a second conductor;
The analog / digital mixed semiconductor device, wherein the plurality of first posts and the plurality of second posts are arranged in different arrangements.   4. The analog / digital mixed semiconductor device according to claim 2, wherein the first and second conductors are wires. The first and second conductors are wires,
A wire non-connecting pad is disposed under the wire connecting the first post and the second pad and between the first pad and the second pad. 3. The analog / digital mixed semiconductor device according to claim 2, wherein:

Images