JP2007273847A - Design method of semiconductor integrated circuit device, and design equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design method of a semiconductor integrated circuit device capable of creating a bridge wiring of high application potency. <P>SOLUTION: This method extracts a free area without wiring in an LB layer subject to revision, and constitutes the bridge wiring BD for connecting the free areas. In the LB layer subject to revision, a logic change wiring is made in the free area without wiring and then connected to the bridge wiring BD. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a design method and design apparatus for a semiconductor integrated circuit device.
In recent years, semiconductor integrated circuit devices (LSIs) have been increased in scale and integration, and elements are connected using many wiring layers. After the semiconductor integrated circuit device is created, it may be necessary to modify the circuit due to a change in specifications or the like. This circuit correction is often performed by revising a mask used for producing a semiconductor integrated circuit device. And it is required to modify the circuit by revising a few mask layers.

Conventionally, as a method of correcting a circuit of a semiconductor integrated circuit device by revising a mask, a detour wiring (dummy wiring) is inserted in a predetermined wiring layer in advance, and the detour wiring is used to reduce the number of mask layers. A method for correcting a circuit is disclosed (for example, see Patent Document 1 and Patent Document 2).
JP-A-6-216247 JP 2000-252360 A

  However, in the above-described conventional method, a means for optimizing the arrangement position and length of the bypass wiring is not disclosed. Therefore, there is not necessarily a wiring suitable for wiring correction, and the number of masks to be revised increases. There was a fear.

  In order to increase the utilization rate of the bypass wiring, it is conceivable to insert the bypass wiring as much as possible in the empty area. However, since unnecessary wiring portions are added to the wiring in the used bypass wiring, a large wiring capacity is added to the circuit, and the delay increases, so that it is difficult to use the bypass wiring. There was a problem.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a design method and design apparatus for a semiconductor integrated circuit device capable of creating a bridge wiring with high availability. is there.

  In order to achieve the above object, according to the first aspect of the present invention, a vacant area where a wiring of a second wiring layer different from the first wiring layer is not created is extracted, and a corresponding vacant area is selected. A number of bridge wires are created between the empty areas. Therefore, since the bridge wiring is created between the required empty areas, the utilization is high, and the length of the bridge wiring created is shorter than when creating the bridge wiring in all of the empty areas, so the extra wiring No capacity is added.

  According to the second aspect of the present invention, the number of nets in contact with the empty area is extracted, and the number of the bridge wirings corresponding to the number of nets is created. Therefore, the necessary number of bridge wires can be created.

  According to a third aspect of the present invention, the bridge wiring includes a wiring created in the first wiring layer, and a contact for connecting the wiring and the wiring of the second wiring layer. Is done. Therefore, by forming a wiring in the second wiring layer, that is, by revising only the second wiring layer, a semiconductor integrated circuit device with a changed logical connection can be created.

  According to a fourth aspect of the present invention, a process of searching for a connection path between each starting point and another empty area, starting from a wiring grid adjacent to the frame of the empty area, and connected by the connection path Storing the coordinates and wiring lengths of the connection points to be associated with the starting points, reading the coordinates and wiring lengths of the connection points, and creating a bridge wiring between the connection points according to a predetermined priority order A process.

  According to the fifth aspect of the present invention, a vacant area where a wiring of a second wiring layer different from the first wiring layer is not created is extracted, and the number of bridge wirings corresponding to each vacant area is a vacant area. Created in between. Therefore, since the bridge wiring is created between the required empty areas, the utilization is high, and the length of the bridge wiring created is shorter than when creating the bridge wiring in all of the empty areas, so the extra wiring No capacity is added.

  ADVANTAGE OF THE INVENTION According to this invention, the design method and design apparatus of a semiconductor integrated circuit device which can create bridge wiring with high availability can be provided.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of the invention will be described with reference to the drawings.
FIG. 1 is a schematic configuration diagram of a computer system for performing wiring processing and wiring correction processing of a semiconductor integrated circuit device.

  The computer 11 includes a general CAD (Computer Aided Design) device, and includes a central processing unit (hereinafter referred to as a CPU) 12, a memory 13, a magnetic disk 14, a display device 15, an input device 16, and an external storage device 17. They are connected to each other via a bus 18.

  The CPU 12 executes a program using the memory 13 and executes wiring processing and wiring correction processing of the semiconductor integrated circuit device. The memory 13 stores programs and data necessary for realizing various processes. The memory 13 usually includes a cache memory, a system memory, a display memory, and the like (not shown).

  The display device 15 is used for display of a layout display, a parameter input screen, and the like. Usually, a CRT, LCD, PDP, or the like (not shown) is used for this. The input device 16 is used to input requests, instructions, and parameters from the user. For this, a keyboard and a mouse device (not shown) are used.

  The magnetic disk 14 usually includes a magnetic disk device, an optical disk device, a magneto-optical disk device, etc. (not shown). The magnetic disk 14 stores various data such as program data, net list, layout data, and the like for wiring processing and wiring correction processing of the semiconductor integrated circuit device. In response to an instruction from the input device 16 or the like, the CPU 12 transfers the program and data to the memory 13 and executes them sequentially.

  Program data executed by the CPU 12 is provided on the recording medium 19. The external storage device 17 corresponds to the recording medium 19 to be used, and drives the recording medium 19 to access the stored contents. The CPU 12 reads program data from the recording medium 19 via the external storage device 17 and installs it on the magnetic disk 14.

  The recording medium 19 is a computer-readable recording medium. For example, an optical disk 19a such as a CDROM or DVD, a magnetic medium 19b such as a magnetic tape (MT), a flexible disk, a magneto-optical disk (MO, MD,...) Is used. . A semiconductor memory, an externally connected hard disk device, or the like may be used. The above-described program data can be stored in the recording medium 19 and loaded into the memory 13 for use as necessary.

  The recording medium 19 includes a medium on which program data uploaded or downloaded via a communication medium is recorded, a disk device, a storage device of a server device to which the computer 11 is connected via a communication medium, and the like. Furthermore, not only a recording medium that records a program that can be directly executed by a computer, but also a recording medium that records a program that can be executed once installed on another recording medium (such as a hard disk), or an encrypted program In addition, a recording medium on which a compressed program is recorded is also included.

Next, wiring processing and wiring correction processing of the semiconductor integrated circuit device will be described.
FIG. 2A is a partial flowchart of a process for creating the first layout data of the semiconductor integrated circuit device.

  In step 21, the CPU 12 shown in FIG. 1 arranges the cells constituting the semiconductor integrated circuit device based on the net list and library data stored in the memory 13 or the magnetic disk 14, and connects the cells by wiring. Then, the created layout data is stored in the memory 13 or the magnetic disk 14.

  In step 22, the CPU 12 inserts a bridge wiring into a predetermined wiring layer as the first wiring layer with respect to the layout data of the semiconductor integrated circuit device, and stores the layout data after the insertion. A semiconductor integrated circuit device has a multilayer wiring structure, and in the manufacturing process, a mask for forming a metal wiring such as aluminum or copper, a mask for forming a diffusion layer, and a through hole opened in an insulating layer between wiring layers A mask (mask for forming a through hole) for forming a contact for connecting the wiring layers or the like via a via (also referred to as a via) is used. The bridge wiring includes an unconnected wiring created in a predetermined metal wiring layer, and a contact for connecting the wiring layer of the wiring to another wiring layer.

  The CPU 12 creates a bridge wiring in a wiring layer corresponding to a predetermined revision target layer as the second wiring layer. Specifically, the CPU 12 first extracts a wiring track having no wiring as an empty area in the revision target layer. At this time, if the number of nets in contact with the empty area and the area of the empty area exceed a predetermined value, the empty area is divided into a plurality of areas, and a number of bridge wirings corresponding to the number of divisions are inserted between the areas. Then, the CPU 12 determines the required number of wirings between the empty areas based on the number of types of nets that are in contact with the empty areas.

  The necessary number of wirings between the empty areas is the number necessary to connect all the nets of the wiring of the revision target layer in contact with the areas to the nets whose connection is changed through the other empty areas. When bridge wiring is created for all wiring tracks in which no wiring exists, wiring capacity is added more than necessary to the net using the wiring, and signal delay time and signal level deteriorate. Further, the logic change scale by the metal ECO is limited to about 0.01% of the scale of the entire circuit in consideration of the restriction that the cells are not substantially added / deleted. For this reason, it is possible to cope with the problem by creating bridge wiring between the empty areas and setting the number of bridge wirings to the number of nets adjacent to the empty area.

Next, the CPU 12 extracts the coordinate value of the wiring existing in the wiring layer into which the bridge wiring is inserted as obstacle data.
Next, the CPU 12 searches for a connection route to another empty area, starting from the wiring grid adjacent to the empty area frame. At this time, the CPU 12 searches for the shortest connection route using the extracted obstacle data. Then, the CPU 12 uses the wiring track connected by the wiring of the connection path as the connection point, determines the wiring length from the shortest connection path, and stores the coordinate value of the connection point and the wiring length in association with each other in the table). To do. The table is stored in the memory 13, for example.

  When the coordinate values of the connection points and the wiring lengths are stored in the table for all wiring grids adjacent to the frame of the vacant area, the CPU 12 sorts the data in the table in ascending order of the wiring length using the wiring length as a key. .

When the above table is created for all free areas, the CPU 12 creates bridge wiring according to a predetermined priority.
The priority order is as follows.
1: Wiring with the connection point between the empty areas having the shortest distance as the connection point.
2: Wiring with a connection point at a point where the coordinate value is the maximum value / minimum value in a direction (Y axis) orthogonal to the wiring direction of the revision target layer.
3: Wiring with a connection point at a point where the coordinate value is the maximum value / minimum value in the direction parallel to the wiring direction of the revision target layer (X axis).
4: Wiring connected to a connection point having a short wiring length and wiring tracks of a predetermined grid or more around the wiring length.

  In step 23, the CPU 12 performs physical verification on the layout data created in step 22. In the physical verification, the CPU 12 checks whether or not layout data wiring or the like is formed according to a geometric design rule such as wiring width and wiring interval.

FIG. 2B is a flowchart of correction processing for revising the layout data of the semiconductor integrated circuit device.
In step 31, the CPU 12 in FIG. 1 examines whether or not the logic can be changed only by revising the metal wiring layer. The conditions for this examination are that the cells that are not required when the logic is changed are not substantially deleted, EC cells are added / changed / deleted, and the metal layer that forms the wiring connecting them is changed. The EC cell is a spare cell (redundant cell) created in advance in the semiconductor integrated circuit device in anticipation of a circuit change or the like. Add redundant cells to the net according to the circuit change, use redundant cells with different logic from the used logic cells (change), and form wiring so as not to use net logic cells (delete) ,Is possible. The CPU 12 proceeds to the next step when the logic change is possible only by the revision of the metal wiring layer, and ends this process when the logic change is impossible.

  In step 32, the CPU 12 performs a logic change. At this time, the net list for metal ECO (Engineering Change Order: responding to the change of the net list by changing only the metal wiring) is changed.

  In step 33, the CPU 12 performs metal ECO in the revision target layer using the bridge wiring created in advance based on the net list created in step 32. The revision target layer is set according to the contents of the revision. If this revision target layer is small, the number of masks created for manufacturing a semiconductor integrated circuit device with a corrected circuit is reduced, and the time, cost, etc. required for the mask creation can be reduced.

  The revision target layer is set according to a bridge wiring created in advance. When the CPU 12 does not add or delete cells, that is, when only the connection is changed, the CPU 12 sets a wiring layer that forms a wiring connectable to the bridge wiring contact as a revision target layer. In addition, when the EC cell is added / changed / deleted with the circuit change, the CPU 12 needs to modify the wiring layer that needs to be modified by using the EC cell and to connect the EC cell to the bridge wiring. The correct wiring layer is set as the revision target layer.

  For example, when the bridge wiring is composed of an LC layer (a metal wiring layer, a third layer upward from the semiconductor substrate), a wiring of the LC layer, and a contact connected to the wiring, the contact The wiring layer (for example, LB layer) connected to the wiring of the LC layer is set as the revision target layer. The wiring layers NA, LA, and NB that need to be changed in order to use the EC cell and the wiring layer LB that needs to be corrected in order to connect the EC cell to the bridge wiring are defined as revision target layers. The wiring layer LA is the lowest layer among the plurality of metal wirings, the wiring layer NA is a layer for forming a contact for connecting the wiring of the wiring layer LA and the diffusion layer, and the wiring layer NB is a wiring layer. This is a layer for forming a contact for connecting the wiring of the LB and the wiring of the wiring layer LA.

  The CPU 12 adds / changes / deletes wiring elements such as wirings and contacts for the set revision target layer in accordance with the net list created in step 32, and stores the revised layout data.

  Next, in step 34, the CPU 12 performs the timing ECO using the bridge wiring. Due to the addition / change / deletion of logic cells, the operation timing changes due to increase / decrease of gate delay and wiring delay. For this reason, circuit correction for timing adjustment is performed using a bridge wiring for a net that requires timing adjustment, and the layout data after the correction is stored.

  In step 35, the CPU 12 performs timing verification and physical verification of the semiconductor integrated circuit device on the layout data whose circuit has been corrected. If there is no error in this verification, the CPU 12 ends the correction process. If an error occurs in the verification, the process proceeds to step 31 to execute a correction process. Note that the transition step may be changed as appropriate according to the error that occurs.

Next, the bridge wiring insertion process in step 22 will be described with reference to an explanatory diagram of the layout.
FIG. 3 is a partially enlarged view of the layout data 41 created after the arrangement / wiring process, that is, in step 21 of FIG. FIG. 3 shows the elements, the wiring of the wiring layer (LC layer) into which the bridge wiring is inserted and the revision target layer (LB layer), and the contacts connecting the elements and the wirings or the wirings. Further, in FIG. 3, the vertical direction of the drawing is the wiring direction of the LB layer, and the horizontal direction of the drawing is the wiring direction of the LC layer.

  First, as shown in FIG. 4, the CPU 12 pays attention to the wiring of the LB layer, and extracts a wiring track in which no wiring exists as an empty area. In FIG. 4, a black circle is displayed on the wiring track in the empty area to indicate the area. Then, the CPU 12 extracts the net of the wiring that contacts the free area, and determines the required number of wirings between the free areas based on the type of the net. For example, wirings L1 to L8 are in contact with the empty area 42. Referring to FIG. 3, the wiring L1 and the wiring L2 are the same net, and the wiring L6 and the wiring L8 are the same net. Accordingly, there are six types of nets in contact with the empty area 42. Next, as shown in FIG. 5, the CPU 12 extracts the coordinate value of the wiring existing in the LC layer into which the bridge wiring is inserted as the obstacle data.

  Next, the CPU 12 pays attention to the wiring grid adjacent to the frame of the empty area 42. In the present embodiment, the wiring tracks are set to a wiring grid set in a matrix at intervals set by technology or the like, and a sub-grid set at a half of the interval. In FIG. 6A, the wiring track of the empty area which is currently focused on is circled and the wiring grid of interest is shown with a cross.

  Then, the CPU 12 searches for a connection path between the wiring track of the focused wiring grid and another empty area in the LC layer in which the bridge wiring is arranged. At this time, based on the obstacle data extracted earlier, the route search is performed while avoiding the wiring existing in the LC layer. In FIG. 6B, the connection paths R1 to R6 of the search result are indicated by solid lines.

  The CPU 12 performs the above processing for other free areas. The results are shown in FIG. When the number of wiring grids is smaller than the required number of wirings, the CPU 12 searches for connection routes of the required number of wirings also using the subgrids. A connection path between the empty areas is a connection candidate for the bridge wiring.

  As shown in FIG. 8, the CPU 12 stores the layout data 43 including the bridge wiring, which creates the bridge wiring BD based on a predetermined priority order with respect to the connection path. The bridge wiring BD includes a wiring BL created in the LC layer and a contact BC created at the end point of the wiring. In FIG. 8, the created bridge wiring is shown by hatching, and the contacts are shown by squares smaller than the wiring.

  As shown in FIG. 9, metal ECO for connecting the terminal T1 of the cell C1 and the terminal T2 of the cell C2 is performed on the semiconductor integrated circuit device in which the bridge wiring is created as described above. At this time, the CPU 12 uses the bridge wiring and creates a wiring in the LB layer that is the revision target layer so as to connect the bridge wiring according to the path R11 indicated by the solid line in FIG.

As described above, according to the present embodiment, the following effects can be obtained.
(1) An empty area in which no wiring is created in the LB layer that is the revision target layer is extracted, and a bridge wiring BD that connects the empty areas is created. In the LB layer that is the revision target layer, a wiring for logical change is created in an empty area where no wiring is created. Therefore, by creating a bridge wiring between the required empty areas, it is possible to create a bridge wiring with high utilization of the bridge wiring, that is, high availability. Furthermore, the bridge wiring BD connecting the empty areas has a short wiring length, so that no extra wiring capacity is added.

  (2) The number of nets in contact with the free area is extracted, and the number of bridge wirings BD corresponding to the number of nets is created. In many cases, the wiring formed in the empty area of the LB layer that is the revision target layer is connected to the wiring adjacent to the empty area. Therefore, by creating the number of bridge wirings BD corresponding to the number of nets, the necessary number of bridge wirings can be created.

  (3) The bridge wiring BD includes a wiring BL created in the LC layer and a contact BC for connecting the wiring BL and the wiring in the LB layer. Therefore, a semiconductor integrated circuit device with a changed logical connection can be created by forming wiring in the LB layer, that is, by revising only the LB layer.

In addition, you may implement the said embodiment in the following aspects.
In the above embodiment, the LB layer is a revision target layer and the LC layer is a wiring layer for creating a bridge wiring, but each wiring layer may be appropriately changed.

  In the above embodiment, the wiring process and the correction process of the semiconductor integrated circuit device have been described as being performed by the same computer 11, but each process may be performed by different computers.

The technical ideas that can be grasped from the above embodiments are described below.
(Appendix 1)
A design method of a semiconductor integrated circuit device for creating a bridge wiring in a predetermined first wiring layer of layout data,
A semiconductor integrated circuit characterized in that a free area in which a wiring of a second wiring layer different from the first wiring layer is not created is extracted, and a number of bridge wirings corresponding to each free area are created between the free areas. Circuit device design method.
(Appendix 2)
2. The method of designing a semiconductor integrated circuit device according to appendix 1, wherein the number of nets in contact with the empty area is extracted and the number of the bridge wirings corresponding to the number of nets is created.
(Appendix 3)
The bridge line is composed of a line created in the first wiring layer and a contact for connecting the line and the line in the second wiring layer. 1 or 2 A method for designing a semiconductor integrated circuit device according to the description.
(Appendix 4)
Starting from a wiring grid adjacent to the frame of the empty area, and searching for a connection path between each empty area and another empty area;
Storing the coordinates of the connection points connected by the connection path and the wiring length in association with the starting points;
Reading the coordinates and wiring length of the connection point, and creating a bridge wiring between the connection points according to a predetermined priority,
The method for designing a semiconductor integrated circuit device according to any one of appendices 1 to 3, further comprising:
(Appendix 5)
A design apparatus for a semiconductor integrated circuit device for creating a bridge wiring in a predetermined first wiring layer of layout data,
A semiconductor integrated circuit characterized in that a free area in which a wiring of a second wiring layer different from the first wiring layer is not created is extracted, and a number of bridge wirings corresponding to each free area are created between the free areas. Circuit device design equipment.
(Appendix 6)
6. The semiconductor integrated circuit device design apparatus according to appendix 5, wherein the number of nets in contact with the empty area is extracted, and the number of the bridge wirings corresponding to the number of nets is created.
(Appendix 7)
The bridge wiring is composed of a wiring created in the first wiring layer and a contact for connecting the wiring and the wiring of the second wiring layer. The design apparatus of the semiconductor integrated circuit device of description.
(Appendix 8)
Starting from a wiring grid adjacent to the frame of the empty area, and searching for a connection path between each empty area and another empty area;
Storing the coordinates of the connection points connected by the connection path and the wiring length in association with the starting points;
Reading the coordinates and wiring length of the connection point, and creating a bridge wiring between the connection points according to a predetermined priority,
The design apparatus for a semiconductor integrated circuit device according to any one of claims 5 to 7, further comprising:

It is a schematic block diagram of a computer system. (A) is a partial flowchart of the design process, and (b) is a flowchart of the revision process. It is explanatory drawing of a bridge | bridging wiring insertion process. It is explanatory drawing of a bridge | bridging wiring insertion process. It is explanatory drawing of a bridge | bridging wiring insertion process. (A) and (b) are explanatory drawings of bridge wiring insertion processing. It is explanatory drawing of a bridge | bridging wiring insertion process. It is explanatory drawing of the insertion result of bridge wiring. It is explanatory drawing of the revision result using bridge wiring.

Explanation of symbols

BD Bridge wiring BL wiring BC contact

Claims (5)

A design method of a semiconductor integrated circuit device for creating a bridge wiring in a predetermined first wiring layer of layout data,
A semiconductor integrated circuit characterized in that a free area in which a wiring of a second wiring layer different from the first wiring layer is not created is extracted, and a number of bridge wirings corresponding to each free area are created between the free areas. Circuit device design method.   2. The method of designing a semiconductor integrated circuit device according to claim 1, wherein the number of nets in contact with the empty area is extracted and the number of the bridge wirings corresponding to the number of nets is created.   The said bridge wiring is comprised from the wiring produced in the said 1st wiring layer, and the contact for connecting this wiring and the wiring of the said 2nd wiring layer, The Claim 1 characterized by the above-mentioned. 3. A method of designing a semiconductor integrated circuit device according to 2. Starting from a wiring grid adjacent to the frame of the empty area, and searching for a connection path between each empty area and another empty area;
Storing the coordinates of the connection points connected by the connection path and the wiring length in association with the starting points;
Reading the coordinates and wiring length of the connection point, and creating a bridge wiring between the connection points according to a predetermined priority,
The method for designing a semiconductor integrated circuit device according to claim 1, further comprising: A design apparatus for a semiconductor integrated circuit device for creating a bridge wiring in a predetermined first wiring layer of layout data,
A semiconductor integrated circuit characterized in that a free area in which a wiring of a second wiring layer different from the first wiring layer is not created is extracted, and a number of bridge wirings corresponding to each free area are created between the free areas. Circuit device design equipment.

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