JP2007272342A - Board design support device and board design support program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To determine a layer change place by evaluating the necessity of layer change for securing a return current route on a solid pattern. <P>SOLUTION: A check point where the necessity of the layer change of a return current route on a solid pattern should be decided is detected from a signal line and the shape of a pattern adjacent to the signal line by a check point detection means 110. Whether or not any inter-layer connection element necessary for the layer change of a return current route exists within a check range including the detected check point is decided by an inter-layer connection element check means 120. The check ranges where any inter-layer connection element does not exist are compounded by a check range compounding means 130, and weights to be applied to the check ranges are added about the overlapped section of the check ranges. The necessity of the layer change of the return current route is decided according to the added weights by a range check means 140. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a printed circuit board design support apparatus and a board design support program that can detect a layer change portion of a return current route.

  In recent years, the density of printed wiring boards, the speed of signals, and the driving voltage have been lowered. Along with this, problems of occurrence of common mode noise or deterioration of signal quality due to an inappropriate route of a return current flowing in the direction opposite to the signal current in the power supply layer or the ground (GND) layer has become serious. For example, the voltage difference between ON and OFF of the digital signal is reduced by lowering the drive voltage, and a malfunction may occur due to slight noise.

  The case where the return current route is not appropriate includes a case where there is a missing pattern intersecting the return current route in the GND layer where the return current flows, or a case where the signal line route is changed through a via hole. is there. When there is a pattern omission in the GND layer through which the return current flows, the return current flows in a detour, and the impedance becomes high at the break. Therefore, the signal line cannot have a uniform characteristic impedance from the transmission terminal to the reception terminal, and reflection due to impedance mismatching occurs.

  In addition, when there is a change in the layer of the signal line, if there is no change in the solid pattern in which the return current flows, the return current is also circulated, causing a disturbance in the signal waveform. In particular, in the case of a 16-bit or 32-bit bus line, since a large amount of current flows, disturbance of the characteristic impedance cannot be ignored, and it may cause waveform cracking and ringing.

  Until now, with respect to the return current route, measures have been taken to secure the return current route by installing interlayer connection elements such as vias and bypass capacitors at equal intervals between the solid patterns on the substrate. However, in the method of installing vias and bypass capacitors at equal intervals on the board, the interval between the vias and bypass capacitors to be installed becomes shorter as the signal speed increases, so the number of necessary interlayer connection elements increases and the number of work steps increases. Increase. In addition, since the installation is always uniform regardless of the state of the wiring, the manufacturing cost is increased by using more than necessary vias and bypass capacitors.

Conventionally, as a solution to the problem related to return current, a method has been proposed in which a solid pattern ground layer is provided on both sides of the insulating layer, the power source is wired with a power line on the ground layer, and vias of the earth net are installed at regular intervals. (See Patent Document 1). Furthermore, in order to secure a return current path at a layer change location due to a via of a signal line, a device that checks the position of the bypass capacitor, calculates the placement position of the bypass capacitor, and changes the via position has been proposed. (Patent Document 2). Furthermore, a method has been proposed in which an analysis function is implemented in the server, an error is detected at the intersection of the solid pattern extraction part and the signal line projection line, and the wiring route and the shape of the solid pattern are changed by notifying the operator. (See Patent Document 3).
JP 2003-163467 A JP 2000-242673 A JP 2004-246869 A

  Since the technique disclosed in Patent Document 1 cannot use a plurality of commonly used power supply or ground solid patterns, design restrictions are large, and all signal lines and power supply lines need to be orthogonal. It takes more time than before.

  The technique disclosed in Patent Document 2 performs a check on connection between solid patterns by vias and calculates the placement position of a bypass capacitor. Regarding the check of the presence of interlayer connection elements near the component pin position and the solid pattern intersection, Not touched.

  The technique disclosed in Patent Document 3 relates to a wiring design check using a server, and in the check related to the return current, only the error detection at the position where the projection line of the signal line intersects the extracted part of the solid pattern is disclosed. .

  Further, in the conventional technique, it is not possible to evaluate whether the part to be checked is a problem part that is really required to secure a return current route or a part that does not become a serious problem.

  In view of the above problems, the present invention provides a board design support apparatus and a board design capable of evaluating the necessity of layer change and determining a layer change point in order to secure a return current route on a conductor pattern such as a solid pattern. The purpose is to provide support programs.

  In order to achieve the above object, a substrate design support apparatus according to a first aspect of the present invention provides a layer of a return current route on a conductor pattern from a signal line through which a signal passes and a conductor pattern adjacent to the signal line. Check point detection means for detecting a check point for determining the necessity of change, and an interlayer connection element necessary for changing the layer of the return current route exists within the check range obtained from the detected check point and the allowable distance reference. Inter-layer connection element check means for determining whether or not to perform the check range synthesis, a check range synthesis means for summing up the weights given to the check range for a portion where the check ranges overlap, and the summed weight Accordingly, a range check means for determining the necessity of changing the layer of the return current route is provided.

  The check range combining means may combine the check range determined by the interlayer connection element check means that the interlayer connection element does not exist, and further, the return current route layer needs to be changed. An interlayer connection element arrangement position automatic calculation means for automatically calculating the arrangement position of the interlayer connection element necessary for the layer change may be provided within the determined combined check range.

  Furthermore, an error display layer generating means for generating an error display layer for displaying, for each net, a check range determined to require a layer change of the return current route may be provided.

  The board design support program according to the second aspect of the present invention should determine the necessity of layer change of the return current route on the conductor pattern from the signal line through which the signal passes and the shape of the conductor pattern adjacent to the signal line. A checkpoint detection function for detecting a checkpoint, and an interlayer for determining whether or not there is an interlayer connection element necessary for changing the layer of the return current route within the check range obtained from the detected checkpoint and the allowable distance reference Connection element check function, check range composition for combining the check ranges, and adding the weights given to the check ranges for the overlapping portions of the check ranges, and changing the layer of the return current route according to the combined weights A range check function for determining necessity is implemented in a computer.

  The present invention can determine the layer change location by evaluating the necessity of layer change by synthesizing the check range. Moreover, according to the interlayer connection element arrangement position automatic calculation means, it is possible to automatically detect a problem location related to the return current and to automatically secure a return current route. Furthermore, according to the error display layer, it is easy for the operator to perform correction work by displaying the problem location related to the return current in an easy-to-understand manner.

  Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are diagrams showing an outline of a CAD apparatus in which a wiring board design support apparatus according to an embodiment of the present invention is incorporated.

  The CAD device 10 includes a command input unit 1, a data input unit 2, a design information storage unit 3, a display unit 4, and a control unit 5.

  The command input unit 1 includes a keyboard 8 and a mouse 9 and receives various design commands input by operator operations. Further, a command input analysis unit is provided, the command received by the command input unit is analyzed, the command type is determined, and an instruction according to the determined command type is given to each unit constituting the CAD device. . If it is determined that the command type is a return current check command, the return current check command can be output to the control unit. The data input unit 2 accepts input of circuit diagram information and the like created by a circuit design CAD device or the like.

  The display unit 4 displays conductor information, hole information, unwired section information, various possible areas and prohibited area information on the wiring board.

The control unit 5 realizes various functions and controls for supporting the wiring board design.
The CAD device 10 is realized by executing software that realizes the functions of the respective units shown in FIG. 1 on computer hardware such as a personal computer and a workstation shown in FIG. The computer hardware includes a main body 6 including a microprocessor, a RAM, a ROM, and a hard disk device, a display device 7, a keyboard 8, a mouse 9, and the like.

  FIG. 3 is a diagram illustrating functions of the printed circuit board design support apparatus 100 according to the present embodiment. The printed circuit board wiring design support apparatus 100 includes a checkpoint detection unit 110 that detects a checkpoint that may cause a return current disturbance, and an interlayer connection such as a via or a bypass capacitor within an allowable distance from the detected checkpoint. Interlayer connection element check means 120 that checks whether an element exists, and for all checkpoints that are determined to have no interlayer connection element, a weight that is predetermined in a check range determined by an allowable distance from the checkpoint Check range combining means 130 for combining the check ranges, weights combined as a result of the combination of check ranges and allowable weights are compared, range check means 140 for combining check ranges exceeding the allowable weights as errors, and determination as an error Interlayer connection for specified check range Comprising interlayer connection element arrangement position automatic calculation means 150 for automatically calculating the position of the element.

  Further, in the present embodiment, the weight instruction means 135 capable of instructing the weight of the check range by the operator is provided, and the operator can set a desired weight in the check range.

  In general, in order to secure return current routes for all signal lines, a large number of interlayer connection elements must be installed, which increases the work man-hours and substrate manufacturing costs. Actually, when a bus line or the like which is a bundle of signal lines does not secure a return current route, a large voltage fluctuation occurs in the solid pattern, often adversely affecting important signal lines. In this embodiment, the check range combining unit 130 combines the check ranges with weights, evaluates the combined weights, and detects an error. It is possible to detect errors that are likely to cause problems depending on the type. When the check range is not combined, the layer change points of the return current route existed in the order of several thousand. However, as a result of the check range combination, the layer change points are reduced to several tens of orders. As described above, when the check range is synthesized, only a part where the necessity of changing the layer of the return current route remains very much, which is effective advice for the designer.

  The check point detection unit 110 of this embodiment will be further described. The check point detection means 110 includes the shape information of the conductor elements that are signal lines, the position information on the wiring board surface, and the signal lines stored in the database 210 of the design information storage unit 3 (FIG. 1). The signal line route is obtained based on the layer information indicating the existing layer and the net information indicating the connection relationship of the signal lines. Next, the solid pattern adjacent to the signal line route is specified based on the shape information, the position information, the layer information, and the net information of the solid pattern to be the power source or the GND similarly stored in the database 210. Then, the signal line route is divided into appropriate wiring sections, the state of the adjacent solid pattern is sequentially examined, and the check point is detected. In the present specification, the solid pattern is a conductor pattern having a width wider than that of the signal line, and is normally used as a power supply layer or a GND layer. Further, the adjacent solid pattern adjacent to the signal line route may exist in the adjacent layer of the signal wiring layer, but is not limited thereto. The adjacent solid pattern means a solid pattern closest to the signal line.

  Here, the check point is a place where the return current route suddenly changes, and an appropriate layer change is required for the return current route. In the present embodiment, the following three types of checkpoints are set. The first is the part where the signal line route is changed, that is, the part where the signal line route is a via, the second is the part where the signal line is connected to a component pin such as a driver or a receiver, and the third is adjacent to the signal line. This is a place where the solid pattern has a gap, that is, a point that becomes an intersection of the projected signal line and the side of the solid pattern when the signal line is projected onto the adjacent solid pattern.

  4A to 4C are explanatory diagrams schematically showing a cross section of a printed wiring board, and an example for explaining the behavior of return current by changing the layer of the signal line route. It is assumed that the signal current flows through the signal line S from left to right. In FIG. 5A, the signal line S is changed in layer, but the return current route flowing through the solid patterns B1 and B2 adjacent to the signal line S is not affected. However, in (b), when the signal line S intersects the solid pattern B3 and changes the layer, the solid pattern adjacent to the signal line S changes from the solid patterns B1 and B3 to the solid patterns B3 and B2. That is, a layer change occurs in the return current route of the solid pattern B1. Further, in (c), the signal line S intersects the solid patterns B3 and B4, and the adjacent solid pattern of the signal line S changes from the solid patterns B1 and B3 to the solid patterns B4 and B2. That is, the return current routes of the solid patterns B1 and B3 are changed to the solid patterns B4 and B2, respectively.

  In the present embodiment, checkpoints are set in the cases shown in FIGS. 4B and 4C. In (c), checkpoints are duplicated at the same point.

  FIG. 5 is a diagram for explaining a place where the first to third check points are set, and shows a cross section of the printed wiring board. A driver 51 and a receiver 53 are mounted on the printed wiring board 50. The printed wiring board 50 includes six layers including a first ground layer GND1, a wiring layer S1, a first power supply layer Vcc1, a second ground layer GND2, a signal layer S2, and a second power supply layer Vcc2. Each layer is insulated and protected by dielectric layers D1 to D7. A driver 51 and a receiver 53 are placed on the dielectric layer D1.

  The drive current output from the output terminal OUT of the driver 51 flows to the input terminal IN of the receiver 53 through the paths I1 to I5 as indicated by the solid line. Note that the return current is indicated by a broken line, and the return current that requires layer change is indicated by a dotted line. In this example, the signal line is changed from the wiring layer S1 to the wiring layer S2. That is, the path I2 on the wiring layer S1 passes through the via (path I3) and becomes the path I4 of the wiring layer S2. Here, the solid patterns adjacent to the signal line (path I2) of the wiring layer S1 are GND1 and Vcc1, and the solid patterns adjacent to the signal line (path I4) of the wiring layer S2 are GND2 and Vcc2. Therefore, in order to secure a path for the return current flowing through GND1 and Vcc1, both layers need to be changed. Therefore, the layer change portion P1 of this signal line becomes the first type checkpoint.

  When arranging the interlayer connection means for changing the layer of the solid pattern, when connecting the power supply layer and the power supply layer of the same potential or between the GND layer and the GND layer, the connection is usually made via a via hole. Further, when the potentials of the power supply layers are different, the connection between the power supply and the GND is given priority through the bypass capacitor, not the connection of the same net. However, the present invention is not limited to this.

  When the adjacent solid pattern itself cannot be found when detecting the checkpoint, an error may be output to notify the operator that the necessary solid pattern does not exist. In addition, a solid pattern that does not allow the generation of return current is set in advance, and when the solid pattern is detected as an adjacent solid pattern at the time of checkpoint detection, the operator is notified so that the solid pattern You can also check it.

  Next, a check point of the connection portion between the component pin and the signal line which is the second type will be described. For the second type of checkpoint, the adjacent solid pattern is examined at the portion where the component pin and the signal line are connected, and is set as a checkpoint when the solid pattern is other than GND. The check point information includes position information indicating the position of the check point, layer change information relating to a layer connected to the signal line, and net information on the adjacent solid pattern and ground (GND).

  In the second type of checkpoint, it is checked whether the return current returns from the ground (GND) to the power supply pin of the drive power supply on the premise of the presence of the power supply voltage stabilization bypass capacitor.

  In the example shown in FIG. 5, the connection point between the signal line and the component pin is a point P2 where the output pin 511 of the driver 51 is connected to the signal line, and a point P3 where the input pin 531 of the receiver is connected to the signal line. Each checkpoint is set. As shown in the figure, the return current from the ground pin 532 of the receiver 53 is finally returned from the ground pin 512 of the driver 51 to the power supply pin 513 through the power supply voltage stabilization bypass capacitor 55. It has become.

  In the second type of checkpoint, if there are multiple grounds, a standard ground can be determined in advance, but the ground corresponding to the drive power source of the signal line to be checked is checked, and an earth net is provided for each signal line. It may be specified.

  If it is uncertain that a bypass capacitor for stabilizing the power supply voltage exists in the vicinity of the driver pin, checkpoint information including position information of the drive power supply pin, drive power supply net information, and ground net information is set. be able to. In this way, it is possible to check the presence of the bypass capacitor simultaneously with the return current check.

  In the third type, a check point is set when a signal line and a constituent side of an adjacent solid pattern spatially intersect. In FIG. 5, the power supply layer Vcc2 has a so-called pattern removal portion 55 where no solid pattern is arranged. As shown in the drawing, the return current route is divided at the pattern removal portion 55. Therefore, the third type check points P41 and P42 are set. It can also be said that the check points P41 and P42 are set at points where the signal line (path I4) intersects with the side of the solid pattern (Vcc2). The third type of checkpoint information includes position information of intersecting positions, layer change information, adjacent solid patterns, and ground net information.

  In addition, when the wiring length of the signal line which runs through the extraction part of a solid pattern is long, you may make it notify an operator to change a solid pattern shape.

  After setting the check point as described above, the return current route is determined by checking whether or not an interlayer connection element that connects adjacent solid patterns as a return current path is installed at a position sufficiently close to the check point. It is possible to specify a place where no is secured.

  In the present embodiment, the check point detection unit 110 is further provided with an instruction unit that allows the operator to make various instructions or settings.

  The permissible distance reference instructing means 111 is a means for an operator to instruct and set permissible distance information that determines a check range when detecting an interlayer connection element existing in the vicinity of a check point. The specified allowable distance determines the check range in which the presence check of the via hole or bypass capacitor centering on the check point is performed, and the numerical value of the distance itself can be directly specified, and the rise time of each signal can be specified. Given this, the allowable distance can be obtained from the wiring delay value per unit length. If the allowable distance is determined by designating the rising time for each signal line, the allowable distance corresponding to each signal line can be easily obtained.

  The signal-to-be-checked instruction unit 112 checks not only all signal lines, but also only specific signal lines based on signal transmission speeds, signal technology, or classification information according to applications stored in the database 210. In this way, the operator can specify.

  For example, a signal line type such as a main signal, a control signal, a bus signal, or the like is displayed as a selection item on the display unit, and the operator can instruct a check target net by selecting an item. Also, keywords are input from the signal line type of the net, circuit attributes of signal lines such as transmission speed, and physical attributes such as line width and wiring layer, and one or more keywords are logically ORed. Alternatively, filter conditions based on logical products may be defined, and check necessity may be set for a net that satisfies the conditions. Furthermore, a net information list is displayed, and the operator can select a check target net from the list.

  According to the check target check point instruction unit 113, the operator can instruct the check point type to be checked, for example, the driver terminal, the layer change portion, the solid pattern removed portion, the receiver terminal, and the like.

  According to the check line exclusion unit 114 based on the lead line length, the operator can instruct the lead line length from the component pin that is not to be checked. As shown in FIG. 6, a component such as the driver 51 is usually surface-mounted and connected to a via hole 62 from a component pin 515 through a lead wire 61. When the lead line length L1 is short, the check point of the driver pin 515 and the check point of the layer change by the via 62 often overlap, and when an error occurs, the weight is doubled at the overlapped portion, so an error occurs. May be mistaken for a more serious error than necessary. Therefore, it is possible to omit one.

  The line width check exclusion means 115 is a means for an operator to specify a line width that is not to be checked. Although the net to be checked is a signal net, there may be a net used for power supply even if it is a signal net. These can be excluded also by the check target signal instruction means 112. However, since the net used for the power supply is usually thick in line width, the signal net having the line width not less than the predetermined width is not checked. Even so, it can be excluded. The operator can specify the width of the signal line that can be excluded from the check.

  Check exclusion means 116 due to a solid pattern cutout near the via is also provided. As shown in FIG. 7, there is a notch 67 in the adjacent solid pattern B66 of the via 65 that changes the layer of the signal line 63, and the distance L2 between the via 65, the side of the solid pattern, and the point where the signal line intersects is set. When the distance is close, as in the case where the distance between the component pin and the via is short, if the error overlaps, it may be determined that the error is more serious than necessary. Therefore, the points where the sides of the solid pattern intersect with the signal lines can be excluded from the check target. Note that the operator can instruct the length to the intersection of the via and the solid pattern to be excluded from the check target.

  Further, a solid pattern lower wiring check means 162 is provided. When the signal line intersects the side of the adjacent solid pattern, the problem becomes large when the line length of the signal line having no adjacent solid pattern is long. The solid pattern lower wiring check means 116 checks the line length of a signal line that does not have an adjacent solid pattern, and if it is longer than the allowable length set by the system or the operator, notifies the operator as an error. Note that if there is no solid pattern adjacent to the signal line, it is possible to check all the locations and notify the operator. In this way, in order to prevent impedance fluctuations for important signal lines, it can also be used for checking when the designer is instructing not to make a gap in the adjacent solid pattern. it can.

  Furthermore, in this embodiment, the bypass capacitor lead wiring check means 163 is provided, the connection state is checked based on the shape information, position information, layer information, and net information of the conductor element stored in the database, and the lead length from the bypass capacitor is checked. Is longer than the permissible length specified by the system or the worker, it is determined as an error, and the worker is notified. Specifically, the lead-out line length from the bypass capacitor is checked, and compared with the allowable line length set by the system or the operator, if the line length is longer than the allowable length, it is determined as an error. Further, the lead-out line width from the bypass capacitor is checked, and when the line width is smaller than the allowable width compared with the allowable line width set by the system or the operator, it is determined as an error and notified to the operator. In general, when a bypass capacitor is used, it is necessary to sufficiently shorten the lead line length and sufficiently wide the lead line width, and these can be checked by the bypass capacitor lead wiring check means 410.

  Next, the interlayer connection element check unit 120, the check range synthesis unit 130, the range check unit 140, and the interlayer connection element arrangement position automatic calculation unit 150 will be described.

  Based on the checkpoint information and the shape information, the position information, the layer information, and the net information of the conductor elements stored in the database, the interlayer connection elements such as via holes or bypass capacitors are removed from the checkpoint by the interlayer connection element check unit 120. Check whether it is within the allowable distance, that is, within the check range.

  Next, the check range synthesizing unit 130 synthesizes the check range determined by the interlayer connection element check unit 120 that there is no interlayer connection element. When synthesizing the check range, a weight determined in advance by the type of the signal line is set as the check range, and when the check range where the solid pattern net information matches like the pair of power supply layers and the GND layer intersects, The combined check range weights are added together and set as the weight of this intersection. The weight of each signal line is predetermined by the system based on the type of the signal line by default, but can be changed by an operator by the weight instruction means 131.

  FIG. 8 shows the concept of check range synthesis. The check ranges are a1, a2, and a3, and the weight of each check range is 5. Since the bypass capacitor BC exists in the check range a3, it is not synthesized. The check ranges a1 and a2 are combined, and the total weight of the intersection indicated by the oblique lines is 10. As will be described below, the synthesis of the actual check range is performed by converting it into a polygon in order to facilitate processing.

  The weight value summed up in each part of the check range synthesized by the check range synthesis means 130 is compared with the allowable weight value set by the system or the operator. As a result, a portion where the total weight value exceeds the allowable weight value is finally detected as a problematic error. Note that the check range is defined as a circle as an initial value, but at the time of synthesis, the check range is converted to an approximate polygon to obtain a composite shape of the check range. Since the error range obtained in this way takes into account the importance of signal lines and the density of problem areas, only problem areas that need to be improved are detected.

  Note that error range notification means 135 may be provided for notifying an operator of an error when the weight exceeds the allowable weight criterion.

  Further, in the present embodiment, the interlayer connection element arrangement position automatic calculation unit 150 is provided, and among the check ranges synthesized with weights, information on the check range determined to be an error and the shape of the conductor element stored in the database Based on information, position information, layer information, and net information, check the connection status within the check range determined to be an error, and automatically calculate the position of the adjacent interlayer connection element and the interlayer connection element where no clearance error is detected To.

Finally, means for displaying an error or the like to the worker will be described.
In this embodiment, an error display layer generation unit 311 is provided, and an error display layer is generated for each power supply net and / or earth net for the check range determined to be an error, and the error display layer is determined to be an error. Display the check range. That is, the system information layer for each net attribute different from the pattern design layer is generated by referring to the net information regarding the check point and the check range. The error mark and error range to be displayed are registered in the newly generated system layer. The check range has color information determined by the system for each weight or set by the operator, and is displayed in the set color when the screen is displayed. By displaying the error range on the error display layer, the operator can easily confirm the error location, and even when different power supply layers are divided into common layers, different power supply layers On the other hand, the error location can be clearly recognized by the individually generated error display layer.

  Further, the error range color instruction means 313 allows the operator to instruct a color for displaying the synthesized check range in a color-coded manner according to the weight.

  FIG. 9 is a diagram for explaining the concept of the error display layer. The first and second error display layers 73 and 75 are created separately from the pattern design layer 71. Here, the first and second error display layers 73 and 75 correspond to different power supply layers. Has been created. On the first and second error display layers 73 and 75, the combined portions b1, b2 and b3 of the check range converted into polygons are displayed in different colors according to the combined weights. A cross indicates a checkpoint. The color-coded colors can be designated by the error range color instruction means 313.

  Furthermore, a check range emphasis display means 312 is provided, and the check range and the corresponding interlayer connection element in the range can be set to be highlighted for each signal line. This is for the operator to check the check range and the corresponding interlayer connection element within the range, unlike the case of displaying the error location like the error display layer.

  An operator may instruct to highlight a net pattern element in order to confirm the connection state of signal lines on the display screen. At that time, the check range emphasis display means 312 enables the check points, the effective range of the interlayer connection elements, that is, the check range, and the interlayer connection elements existing in the vicinity to be highlighted.

  First, a checkpoint is detected for the instructed signal line, and a checkpoint mark and a circular check range created based on the checkpoint position and allowable distance are displayed on the screen. Next, the necessary interlayer connection elements are checked, and the corresponding elements such as capacitors and vias are highlighted on the screen. At that time, the check range and the interlayer connection element are displayed in different colors for each net type. For example, the signal line that connects the pins of two ICs is highlighted in color, the surrounding check range is highlighted in color in a circle, and the corresponding capacitor in the check range is checked. Are displayed in the same color. If there is a check range with different net types, they are displayed in different colors.

Next, the operation of the present embodiment will be described with reference to the operation flow shown in FIGS.
FIG. 10 is a flow for explaining the overall operation of the present embodiment for checking the problem part of the return current route, that is, the error part.

  In step S101, signal net information is read from the net information list. In step S102, it is checked whether or not the net information has been read for all signal nets. If reading of all net information is not completed, the process proceeds to step S103, and if some nets are designated as check target nets by the check target signal instruction means 112, it is determined whether or not they are check target nets. Is done. If it is not a check target net, the process returns to step S101, and the next net information is read. If it is a check target net, the process proceeds to step S104. If all signal nets are designated as check targets, all signal nets proceed to step S104.

  In step S104, it is determined whether or not there is an exclusion instruction by the line width check exclusion means 115. If there is an exclusion instruction, the process proceeds to step S105, and the net information matches from the line information table for the check target net. And the thickest line width is extracted. In step S106, it is determined whether or not the extracted line width exceeds the reference line width compared with the reference line width specified by the line width check exclusion unit 115. If the extracted line width exceeds the reference line width, it is determined that the net is not a signal line, so the process returns to step S101, and new signal net information is read.

  If the extracted line width does not exceed the reference line width in step S106, and if there is no exclusion instruction based on the line width in step S104, checkpoint detection is executed in step S107. As described above, the check points are checked and set at locations where signal line layer changes, component pins, and solid patterns are removed.

  When all the checkpoints are obtained, in step S108, the interlayer connection element is checked in the check range that is the allowable distance range from the checkpoint to determine whether there is a via hole or a bypass capacitor, and the interlayer connection element exists. Not checked check range is extracted. When finished, the process returns to step S101, and information on a new signal net is read out.

  As described above, when it is determined in step S102 that reading of the net information of all signal nets is completed, the process proceeds to step S109. In step S109, the check ranges in which no interlayer connection elements exist are synthesized, and the weights given according to the signal lines in the respective parts of the synthesized check ranges are added together. In step S110, the summed weight value is compared with the allowable weight value, and a check range exceeding the allowable weight value is extracted as an error range. Further, when there is an instruction for automatically calculating the interlayer connection element arrangement position, the arrangement position of the interlayer connection element is automatically calculated. Finally, in step S112, the error range shape information and color information are registered in the error display layer. In this way, an error display layer in which an error range is displayed can be displayed.

  FIG. 11 is a diagram showing a specific detection step of the check point detection step (S107) of the overall flow of FIG. As shown in FIG. 11, the checkpoint detection step includes the checkpoint detection of vias in step S210, the checkpoint detection of component pins in step S230, and the checkpoint detection of solid pattern intersections in step S250, ie, signal lines and solids. It consists of checkpoint detection at the intersections with the constituent edges of the pattern.

FIG. 12 shows a detailed flow of the via checkpoint detection step S210.
First, in step S211, vias whose net names match the check target net are extracted from the via information list and set as check target vias. Next, in step S212, a line that intersects with the check target via and has the same net name is extracted from the line information list and set as a check target line. In step S213, when the check target line exists in a plurality of layers, a solid pattern adjacent to the layer of each line is extracted from the solid pattern information list and is set as a check candidate solid pattern. At this time, the line layer number is associated with the check candidate solid pattern.

  Next, in step S214, combinations of line layer numbers are extracted in order. In step S215, it is determined whether or not this extraction process is completed. If the extraction process has not ended, the process proceeds to step S216. In step S216, if the check candidate solid patterns related to the line layer exist in different layers before and after the line layer change, each check candidate solid pattern is set as a check target solid pattern.

  In step S217, the combination of the extracted check target solid patterns is examined, and each net information is registered in the checkpoint information table. First, of the extracted combinations of the check target solid patterns, the net information is registered in the checkpoint information table for the related lines whose layer numbers are different and the check target solid patterns are the same net. Next, the net information is registered in the checkpoint information table for the layer number of the associated line is different and the check target solid pattern is a combination of power and ground. Check whether the last solid pattern to be checked is the layer number of the associated line and the solid pattern to be checked is a different ground or power source, and register the net information in the checkpoint information table To do.

FIG. 13 shows the detailed steps of the component pin checkpoint detection step S230.
In step S231, a component pin whose net name matches the check target net is extracted from the component pin information list and is set as a check target component pin. In step S232, a line that intersects with the check target component pin and has the same net name is extracted from the line information list and set as a check target line.

  In step S233, it is determined whether there is an exclusion instruction based on the leader line length. When there is an exclusion instruction, in step S234, the connection state between the line and the via is checked, and the lead line length from the component pin to the via is obtained. In step S235, it is determined whether or not the obtained leader line length is equal to or less than a predetermined reference value.

  If it is determined in step S233 that there is no instruction to exclude by the lead line length, and if the lead line length is longer than the reference, the process proceeds to step S236, and the adjacent solid pattern of the layer of the check target line is selected from the solid pattern information list. Extracted and set as a check target solid pattern.

  Next, in step S237, if the net information of the check target solid pattern does not match the driving power net of the check target net or the ground net information corresponding to the power source, the net information of the check target solid pattern and the check target net The earth net information corresponding to is registered in the checkpoint information table, and the process ends.

  14 and 15 show details of the check detection step S250 for the intersection of the signal line and the solid pattern when the solid pattern is missing.

  In step S251, a line whose net name matches the check target net is extracted from the line information list and is set as the check target line.

  In step S252, an adjacent solid pattern that is adjacent to the check target line is extracted from the solid pattern information list, and a position where a constituent side that becomes the outline of the solid pattern spatially intersects the line is obtained. In step S253, the connection state is checked for each direction in which the line extends from the obtained intersection position, and the line length of the part where the adjacent solid pattern does not exist is obtained.

  Next, in step S254, it is determined whether or not a solid pattern lower wiring check instruction is issued. If a solid pattern lower wiring check instruction is issued, in step S255, the line length obtained in step S253 is the allowable line. Determine whether the length is exceeded. If the line line length exceeds the allowable line length, a solid pattern lower wiring check error is output in step S256 to notify the operator that the line line length exceeds the allowable line length.

  If there is no intersection between the line to be checked and the adjacent solid pattern (hereinafter sometimes referred to as “intersection”), it can be said that there is no problem, but the adjacent solid pattern does not exist and is to be checked. There may be cases where the line does not intersect. Therefore, in the solid pattern lower wiring check, a check is also made when there is no intersection between the check target line and the solid pattern and when there is no adjacent solid pattern. This is step S257. If there is no intersection with the check target line and there is no adjacent solid pattern, a solid pattern lower wiring check error is output in step S258 to notify the operator that there is no adjacent solid pattern for the check target line in the first place. To do.

  When the solid pattern lower wiring check as described above is completed or there is no solid pattern lower wiring check instruction, a checkpoint is registered in step S259 (FIG. 15). That is, in step S259, there is a solid pattern including an intersection position formed in a layer other than the layer in which the check target solid pattern exists with respect to the solid pattern in which the intersection with the check target line exists, that is, the check target solid pattern. And if it exists, extract it. Then, the net information of the solid pattern to be checked and the net information of the extracted solid pattern are registered in the checkpoint information table. At that time, when there are a plurality of extracted solid patterns, priority is given to those having the same net information or a combination of power supply and ground.

  When the registration of the check point is completed, it is checked in step S260 whether or not there is an instruction to exclude the check of the via neighboring solid pattern intersection. If there is a check exclusion instruction for a solid pattern intersection near the via, in step S261, the line length of the signal line between the position where the signal line and the solid pattern intersect and the via position of the signal line is obtained. In step S262, it is determined whether or not the obtained line length is less than the reference. If the obtained line length is less than the reference, it is determined that it is not necessary to check the solid pattern intersection point. Delete from the checkpoint information table and end this flow. If the obtained line length is larger than the reference in step S262, the check point information is not deleted and this flow is terminated. Similarly, the check point information is not deleted even when there is no check exclusion instruction at the via pattern intersection intersection.

  As described with reference to FIGS. 11 to 15, checkpoint detection in FIG. 10 is performed (when S107 ends, an interlayer connection element check (S108) is performed.

  FIGS. 16 and 17 are detailed flows of step S108 in the interlayer connection element check in the overall flow of FIG. In the present embodiment, the interlayer connection element is a bypass capacitor for a heterogeneous net and a via for the net. In the flow of FIG. 12, before these checks, it is possible to check whether the lead-out wiring is appropriate for the bypass capacitor.

  First, in step S311, a component whose component type is a bypass capacitor is extracted from the component list. Then, the connection state is checked from the line information list and the via information list, and the lead-out via of the bypass capacitor is specified. The specified extraction via is registered in the extraction element table.

  In step S312, it is checked whether there is a bypass capacitor lead wiring check instruction. If there is a bypass capacitor lead wiring check instruction, the process proceeds to step S313. In step S313, the length of the lead line from the bypass capacitor pin to the specified lead via is checked. Further, the line width of the leader line is checked to obtain the minimum line width.

  In step S314, it is checked whether or not the lead line length exceeds the reference. If the lead line length exceeds the reference, a bypass capacitor lead line length check error is output and notified to the operator in step S315. Next, in step S316, the minimum line width of the leader line is compared with the reference value, and it is checked whether the leader line width is less than the reference. If the lead line width is less than the reference, a bypass capacitor lead line width check error is output in step S317, and the operator is notified.

  In this way, when the bypass capacitor lead-out wiring check is completed or when there is no bypass capacitor lead-out wiring check instruction, the process proceeds to step S318 (FIG. 17). Step S318 is processing when the bypass capacitor lead-out via is not specified in step S311. If there is no lead-out via, the component pin is registered in the lead-out element table.

  In step S319, it is checked whether the net information of the two solid patterns included in the check point information is the same. For example, if the net information of the two solid patterns is the same, such as the power supply layer and the power supply layer or the GND layer and the GND layer, the interlayer connection element can be determined as a via. Therefore, in step S320, checkpoint information is checked from the via information list. Vias that exist within the permissible distance of, and have matching net information, are extracted. If there is no via that matches this condition, it is determined as an error. This result is registered in the check range information table and the process ends.

  If the net information of the two solid patterns is not the same in step S319, the interlayer connection element can be determined as a bypass capacitor. Therefore, in step S321, the bypass capacitor exists within the allowable distance of the checkpoint information from the extraction element table. Therefore, the bypass capacitor having the same net information is extracted. If there is no bypass capacitor that meets this condition, it is determined as an error. This result is registered in the check range information table and the process ends.

  As described above, the inter-layer connection element check is completed for all check points, and the check range is combined (S109: FIG. 10).

FIG. 18 shows a detailed flow of the check range synthesis step S109 of FIG.
First, in step S411, certain check range information is read from a check range table in which a range in which no interlayer connection element exists is registered as a check range. The check range information table stores the shape of the check range, two solid pattern nets between which the interlayer connection elements should exist, and the weight of the check range.

  In step S412, it is checked whether reading of all check range information has been completed. If reading of all the check range information has not been completed, certain work check range information is read from the work check range information table in step S413. Here, the work check range information table is created as a result of this flow, and is registered by converting the range shape of the check range information from a circle to a polygon shape by polygon approximation. In step S414, it is determined whether or not reading from the work check range information table is completed. At the start of this flow, since there is no work check range information in the work check range information table, reading is complete, and in step S418, the shape of the range of the check range information is obtained by polygon approximation. Then, the check range information of the polygon shape is registered in the work check range information, and the process returns to step S411 to read the next check information.

  If the reading of the work check range information has not been completed in step S414, it is determined in step S415 whether the check range information and the work check range information have the same net information. If the two pieces of net information are not the same, the check range is not combined, so the process returns to step S413 to read the next work check range information.

  If the net information of the check range information and the work check range information is the same in step S415, it is determined in step S416 whether or not the two range shapes intersect. If it does not intersect, there is no need to synthesize the check range, so the process returns to step S413 to read the next work check range information. If both range shapes intersect, the process proceeds to step S417, and the shape of the range of the check range information is approximated by a polygon, and the intersection shape with the range shape of the work check range information is obtained. Also, the weights of the mutual check range information are added together at this intersection. The intersection range shape and the total weight thus obtained are registered or updated in the work check range information. Furthermore, a shape obtained by subtracting the shape of the intersection from the existing shape before synthesis is obtained, and this shape and weight are also registered in the work check range information. When the process ends, the process returns to step S411, and the next check range information is read.

  In this way, when the reading of all the check range information from the check range information table is completed, this flow is ended through step S412. As a result, polygonal check range information having a specific weight is registered in the work check range information table.

As described above, when the synthesis of the chuck range is completed, the range check / automatic calculation of the connecting element position (S110: FIG. 10) is executed.
FIG. 14 is a flowchart showing details of the range check / connection element position automatic calculation step S110 of the entire flow of FIG.

  First, in step S511, check range information (work chuck range information in the flow of FIG. 13) is read from the work check range information table. In step S512, it is checked whether all the check range information has been read. If all the check range information has not been read, it is determined in step S513 whether or not the combined weight value of the check range information exceeds a predetermined allowable weight value. If the total weight value does not exceed the allowable weight value, it is determined that there is no need to newly arrange an interlayer connection element, so the process returns to step S511 to read the next check range information. If it is determined in step S513 that the combined weight value does not exceed the allowable weight value, the process proceeds to step S514, and it is checked whether there is an instruction to automatically calculate the interlayer connection element arrangement position. If there is an instruction to automatically calculate the interlayer connection element arrangement position, an interlayer connection element arrangement position automatic calculation is executed in step S515 (details will be described later with reference to FIG. 21). When the arrangement position of the interlayer connection element is calculated, there is a case where the interlayer element cannot be arranged due to the relationship of adjacent circuit components and the like, and therefore, in step S516, it is determined whether or not the interlayer connection element has been correctly input. If the interlayer connection element is correctly input, the process returns to step S511 to read the next check range.

  If the interlayer connection element cannot be correctly input in step S516, a range check error is output and registered in the error information table in step S517. Thereafter, the process returns to step S511. When the reading of all the check ranges is completed in this way, it is determined in step S512 that the reading is completed, and this flow ends.

FIG. 20 is a detailed flow of the error display information registration step S112 in the overall flow of FIG.
First, in step S611, check range information is read from an error information table in which a check range having a weight exceeding the allowable weight value is registered without an interlayer connection element. In step S612, it is determined whether or not the entire check range has been read. If the reading of the check range has not ended, it is determined in step S613 whether or not an error has occurred in the range check. If the check range is not an error, the process returns to step S611 to read the next check range. If it is determined in step S613 that an error has occurred in the range check, it is checked in step S614 whether there is an error display layer corresponding to the solid pattern net in the check range in which the error occurred. If there is no error display layer, in step S615, a new error display layer for the net is added. Thereafter, in step S616, the shape information and color information of the check range information are registered in the added new layer, and the process returns to step S611 to read the next check range information.

  If it is determined in step S614 that there is an error display layer, the shape information and color information of the check range information are registered in the existing layer in step S616, and the process returns to step S611 to check the next check range. Read information. In this way, when all the check range information has been read out, it is determined in step S612 that reading has ended, and this flow ends.

  FIG. 21 is a detailed flow of the interlayer connection element arrangement position automatic calculation step S515 of FIG. As an interlayer connection element, a bypass capacitor is used for a heterogeneous net between the normal power supply layer and the GND layer or between the first power supply layer and a second power supply layer having a different potential. For this, use via holes.

  First, in step S711, it is determined whether the net information of the two solid patterns included in the check range information is the same. If they are the same, in step S712, vias having the same net information as the net information of the check range information are generated at positions that can be installed within the check range having the shape determined by the check range information.

  If the net information of the two solid patterns is not the same in step S711, in step S713, the part type is a bypass capacitor, and the part has net information that matches the net information of the solid pattern net in the check information range. To extract. That is, a bypass capacitor that connects two solid patterns in the check information range is extracted. Next, in step S714, it is checked whether there is an unarranged part in the check range. If there is an unplaced part, the placement position of the bypass capacitor cannot be determined. Therefore, the flow is finished without placing the bypass capacitor.

  If it is determined in step S714 that there are no unplaced parts in the check range, it is checked in step S715 whether or not to do so. If there is an unplaced part, the bypass capacitor extracted in step S713 is placed at a position where it can be placed within the check range having the shape determined by the check range information.

  Hereinafter, the embodiment of the present invention will be described more specifically by taking the multilayer wiring board shown in FIGS. 22 and 23 as an example. FIG. 22 is a diagram showing connections of circuit components mounted on the multilayer wiring board, and shows a connection relationship between the integrated circuits IC1 and IC2. As shown in the figure, IC1.1 and IC2.1 are connected via via BA1, IC1.2 and IC2.2 are connected via via BA2, and IC1.3 and IC2.3 are connected via via BA3. Has been. The component C1 is a bypass capacitor.

  FIG. 23 is an exploded perspective view of the multiphase wiring board. The multiphase wiring board is composed of six layers L1 to L6, IC1 is provided on the surface of the first layer L1, IC1 is provided on the surface of the first layer L1, and IC2 is the sixth layer L6. It is provided on the surface. The third layer L3 is a ground (GND) layer, and the fourth layer L4 is a power supply (Vcc1) layer. In FIG. 22, a display layer E1 is further provided to display a check range in which an error has occurred.

  22 and 23, the database 210 of the design information storage unit 3 stores a net information list, a line information list, a via information list, a component pin information list, a component information list, and a board configuration list. ing.

  FIG. 24 shows a net information list. The net information list 711 stores information representing net attributes, and the net information list 711 in this example includes weights for the net name, transmission speed, net type, and signal type. Stored.

  FIG. 25 shows a line information list. The line information list 712 is a list that stores information representing the position and attribute of the line, and the line information list 712 of this example stores a net name, a section, a layer number, and a line width.

  FIG. 26 shows a via information list. The via information list 713 is a list for storing information representing the position and attribute of the via, and the via information list 713 in this example stores a net name, a position, an effective layer, and a shape.

  FIG. 27 shows a component pin information list. The component pin information list 714 is a list for storing information representing the position and attribute of the component pin. The component pin information list of this example includes a net name, a component name, a pin name, a position, an effective layer, and a shape component pin. Is stored.

  FIG. 28 shows a parts information list. The component information list 715 is a list that stores information representing the position and attribute of the component. The component pin list 715 of this example stores a component name, a position, a mounting layer, and a component type.

  FIG. 29 shows a solid pattern information list. The solid pattern information list 716 is a list that stores information representing the position and attribute of a solid pattern, and in this example, a net name, shape, and layer number are stored.

  FIG. 30 shows a virtual layer information list. The virtual layer includes an error display layer for displaying a check range in which an error has occurred. The virtual layer information list of this example stores a name, a solid pattern net A, a solid pattern net B, and graphic information.

  As for the return current check command used for the return current route check of this example, the check point information table 718 shown in FIG. 31 and the check range information table 719 shown in FIG. 32 are generated at the time of command execution and discarded at the end of the command.

  The checkpoint information table 718 in FIG. 31 is a list that stores information indicating the position and attribute of the checkpoint. The checkpoint position, the allowable distance that defines the chuck range, and the solid pattern net A as the adjacent solid pattern net A solid pattern net B and a dependence source signal net which is a check target signal are stored.

  The check range information table 719 in FIG. 32 is a list that stores information indicating the position and attribute of the check range, and stores the shape, the solid pattern net A, the solid pattern net B, and the weight.

  In the following, the signal characteristic defect detection operation for this example will be described. The return current check command first extracts a check target net from the net information list 711. If all signals are to be checked by the check target signal instruction means 112, the nets A, B, and C are determined to be check targets.

  Next, checkpoint information is obtained for each checkpoint type by the checkpoint detection means 110. If all checkpoint types are targeted by the check target checkpoint instruction means 113, via checkpoint detection processing, component pin checkpoint detection processing, and solid pattern intersection checkpoint detection processing are sequentially performed.

  In the via checkpoint detection process, vias whose net names match the check target net are extracted from the via information list 713, and the vias of the net names A, B, and C are set as check target vias. Next, lines that intersect with the check target via and have the same net name are extracted from the line information list 712, and the lines of the net names A, B, and C are set as the check target lines.

  Next, a solid pattern existing in the adjacent layer is extracted from the check target line from the solid pattern information list 716, and the solid patterns with the net names Vcc1 and GND are set as the check target solid pattern. In determining the interlayer connection between solid patterns, the Vcc and GND solid patterns in which the layer of the dependency source line and the solid pattern layer, which are the sources of return currents, are different are determined to be connected, and via positions and allowable distance criteria are determined. The allowable distance designated by the instruction unit 111, the net name of one solid pattern, the net name of the other solid pattern, and the net name of the dependence source signal line are registered in the checkpoint information table 718.

  In the component pin check point detection process, component pins whose net names coincide with the check target net are extracted from the component pin information list 715, and the component pins of the net names A, B, and C are set as the check target component pins. Next, a line that intersects the check target component pin and has the same net name is extracted from the line information list 712, and the lines of the net names A, B, and C are set as check target lines.

  Next, the solid pattern existing in the adjacent layer is extracted from the check target line from the solid pattern information list 716, and IC1.1, IC1.2, and IC1.3 determine the GND solid pattern as the check target solid pattern, and IC2 .1, IC2.2, and IC2.3 determine that the Vcc1 solid pattern is the check target solid pattern, the component pin position, the allowable distance, the net name of the solid pattern, the net name of the ground GND, and the dependency source signal line The net name is registered in the checkpoint information table 718.

  In the check point detection process at the solid pattern intersection, a line whose net name matches the check target net is extracted from the line information list 712, and the lines of the net names A, B, and C are set as check target lines. Next, the solid pattern existing in the adjacent layer from the check target line is extracted from the solid pattern information list 716, and the position where the solid pattern component side intersects the check target line shape, the net name of the check target solid pattern, and the ground. The GND net name and the dependency source signal line net name are registered in the checkpoint information table 718. In this example, the state intersecting with the solid pattern is omitted.

  As described above, when the detection of the check point is completed, the interlayer connection element check is performed to check whether or not the interlayer connection element is arranged in the check range defined by the allowable distance from the check point.

  In the interlayer connection element check, first, a component C1 whose component type is a bypass capacitor is extracted from the component information list 715, the connection is traced from the line information list 712 and the via information list 713, and the extraction via is extracted. The extracted drawer via is registered in a drawer element table (not shown). Here, when the extraction via is not detected, the component pin of the extraction source is registered in the extraction element table. Next, with reference to the checkpoint information table 718, the target interlayer connection element type is specified from the two solid pattern net names of the checkpoint information. If the two solid pattern net names match, a via that has the net and is within the allowable distance is extracted from the via information list 713.

  If the two solid pattern net names are different, the bypass capacitor that has the net and is within the allowable distance is extracted from the extraction element table. In this example, at the checkpoints of the component pins IC1.1, IC1.2, and IC1.3, there is a lead via of IC1.4 within an allowable distance. Further, at each check point of the component pins IC2.1, IC2.2, and IC2.3, the bypass capacitor C1 exists within the allowable distance. At the via checkpoint, there is no required bypass capacitor within the allowable distance.

  Here, in the mode in which the check range is not combined, the operator is notified of checkpoint information in which no interlayer connection element is detected. In addition, in the mode in which the check range is synthesized, the check range shape, the net name of the solid pattern, and the weight previously defined in the net information list 711 are registered in the check range table 719 from the check point information in which the interlayer connection element is not detected. To do.

  In the check range synthesis, the check range table 719 is referenced to extract check range information with matching solid pattern net names. If the shapes intersect, the shape is approximated to a polygon to obtain the shape of the intersection. A value obtained by adding the shape and the weight of both check range information is registered in the check range information table 719. The existing shape is changed to a shape obtained by subtracting the shape of the intersection.

  In the range check, check range information exceeding the allowable weight value “5” is extracted from the check range information table after the check range synthesis process, and the operator is notified. In this way, only the highly necessary parts of the interlayer connection element are detected.

  The error display will be described below. In error display, the net information of the check range information exceeding the allowable weight value is referred to, and it is checked from the virtual layer information list 717 whether there is an error display layer for the corresponding net. If the corresponding layer does not exist, a new layer is registered. Next, graphic information including the shape information of the check range information and the color information defined by the error range color instruction unit 312 is registered in the corresponding layer. Thus, since a dedicated layer for each net is provided for error display, the error location can be clearly displayed to the operator.

  In the present embodiment, the check ranges are combined for the check range that is determined to be an error because there is no interlayer connection element in the check range. However, including the check range where the interlayer connection element exists, the weight of the check range where the interlayer connection element exists adds a negative number such as 0 or -5, and synthesizes all of them. You may do it.

The aspects of the present invention described above are as follows.
(Appendix 1)
Check point detection means for detecting a check point for determining the necessity of layer change of the return current route on the conductor pattern from the signal line through which the signal passes and the shape of the conductor pattern adjacent to the signal line;
Interlayer connection element check means for determining whether or not there is an interlayer connection element necessary for changing the layer of the return current route within the check range obtained from the detected checkpoint and the allowable distance reference;
Check range synthesis means for synthesizing the check ranges, and summing the weights given to the check ranges for the portions where the check ranges overlap;
A substrate design support apparatus, comprising: range checking means for determining the necessity of changing the layer of the return current route according to the combined weight.
(Appendix 2)
The board design support apparatus according to appendix 1, wherein the check range synthesis unit synthesizes the check range determined by the interlayer connection element check unit that the interlayer connection element does not exist.
(Appendix 3)
The board design support apparatus according to appendix 1 or 2, wherein the check range synthesis means synthesizes the check range by approximating a polygon.
(Appendix 4)
4. The board design support apparatus according to any one of appendices 1 to 3, further comprising an allowable distance reference instructing unit that sets the allowable distance reference for each signal by designating a rise time of the signal.
(Appendix 5)
The board design support apparatus according to any one of appendices 1 to 4, further comprising weight instruction means for setting a weight given to the check range for each of the signals.
(Appendix 6)
The board design support apparatus according to any one of appendices 1 to 5, further comprising inspection target signal instruction means that can set whether or not the checkpoint is necessary for each signal.
(Appendix 7)
The printed wiring board design support according to any one of appendices 1 to 6, further comprising inspection target layer change position indicating means capable of setting whether or not the checkpoint is detected for each type of the checkpoint. apparatus.
(Appendix 8)
Furthermore, when the lead line length from the component pin on the surface layer is equal to or shorter than the specified length, the lead line length check exclusion means that can be set not to check the lead portion is provided. The printed wiring board design support apparatus according to any one of the above.
(Appendix 9)
Furthermore, the signal line | wire width more than the designated width | variety is provided with the test | inspection exclusion means by the signal line | wire width which can be set so that a check may not be performed, The additional description 1-8 characterized by the above-mentioned. Printed circuit board design support device.
(Appendix 10)
Addendum 1-9 characterized by comprising inspection exclusion means for a via-neighboring conductor pattern intersection that is set so as not to be detected as a checkpoint at a point where a conductor pattern-extracted portion near the via intersects the signal line. The printed wiring board design support apparatus according to any one of the above.
(Appendix 11)
11. The print according to any one of appendices 1 to 10, further comprising a solid pattern lower wiring inspection unit that makes an error when a length of a portion where the adjacent conductor pattern of the signal line does not exist exceeds a specified length. Wiring board design support device.
(Appendix 12)
Any one of appendices 1 to 11, further comprising a bypass capacitor lead-out wiring inspection unit that causes an error when the length of the lead-out line from the bypass capacitor is longer than the specified length or when the line width is narrower than the specified width. The printed circuit board design support apparatus according to 1.
(Appendix 13)
The substrate design according to any one of appendices 1 to 12, wherein the range check means determines whether or not the layer of the return current route needs to be changed based on whether or not the combined weight exceeds a predetermined standard. Support device.
(Appendix 14)
Furthermore, an interlayer connection element arrangement position automatic calculation means for automatically calculating an arrangement position of the interlayer connection element necessary for the layer change is provided within a synthesized check range in which the layer change of the return current route is determined to be necessary. 14. The board design support apparatus according to any one of appendices 1 to 13, characterized in that:
(Appendix 15)
Any one of appendices 1-14, further comprising error display layer generation means for generating an error display layer for displaying, for each net, a check range determined to require layer change of the return current route. The board design support apparatus according to Item 1.
(Appendix 16)
16. The board design support apparatus according to any one of appendices 1 to 15, wherein the error display layer generation means can display the check range by color according to the weight of the check range.
(Appendix 17)
17. The printed circuit board design support apparatus according to any one of appendices 1 to 16, further comprising check range highlighting display means for highlighting a check range and an interlayer connection element for each signal line.
(Appendix 18)
A checkpoint detection function for detecting a checkpoint for judging the necessity of layer change of the return current route on the conductor pattern from the shape of the signal line through which the signal passes and the conductor pattern adjacent to the signal line;
An interlayer connection element check function for determining whether or not there is an interlayer connection element necessary for changing the layer of the return current route within the check range obtained from the detected check point and the allowable distance reference;
A check range synthesis function for synthesizing the check ranges, and adding up the weights given to the check ranges for the portions where the check ranges overlap;
A board design support program for causing a computer to realize a range check function for determining the necessity of layer change of a return current route according to the combined weight.
(Appendix 19)
The board design support program characterized in that the check range synthesis function synthesizes a check range determined by the interlayer connection element check means that the interlayer connection element does not exist.

It is a figure which shows the structure of the CAD apparatus in which embodiment of this invention is integrated. It is a figure which shows the computer which implement | achieves the CAD apparatus of FIG. It is a figure which shows the function of embodiment of this invention. It is a figure explaining the layer change of a return current route. It is a figure explaining the check point for the layer change of a return current. It is a figure explaining the check exclusion by leader line length. It is a figure explaining the check exclusion of the point which a signal line and the side of a solid pattern cross. It is a figure explaining composition of a check range. It is a figure explaining the layer for error display. It is a figure which shows the whole flow which detects the error of the return current route | root which is this embodiment. It is a figure which shows the detail of the flow of a checkpoint detection in the whole flow. It is a figure which shows the detail of the checkpoint detection flow of the via in the checkpoint detection flow. It is a figure which shows the detail of the checkpoint detection flow of the component pin in a checkpoint detection flow. FIG. 10 is a diagram (part 1) illustrating details of a check point detection flow at a solid pattern intersection in the check point detection flow; FIG. 11 is a diagram (part 2) illustrating details of a check point detection flow at a solid pattern intersection in the check point detection flow. FIG. 6 is a diagram (part 1) illustrating details of an interlayer connection check flow in the overall flow. FIG. 6 is a diagram (part 2) illustrating details of an interlayer connection check flow in the overall flow. It is a figure which shows the detail of the flow of the chuck | zipper range synthesis | combination in the whole flow. It is a figure which shows the detail of the flow of the range check in a whole flow, and a connection element position automatic calculation. It is a figure which shows the detail of the flow of the error display information registration in the whole flow. It is a figure which shows the detail of the flow of the interlayer connection element arrangement position automatic calculation in the range check and the connection element position automatic calculation flow. It is a figure which shows the connection state of the components of the wiring board which is a specific example of this embodiment. It is a figure which decomposes | disassembles and shows the wiring board which is a specific example of this embodiment. It is a figure which shows the net information list used by the specific example of this embodiment. It is a figure which shows the line information list used by the specific example of this embodiment. It is a figure which shows the via | veer information list used by the specific example of this embodiment. It is a figure which shows the component pin information list used in the specific example of this embodiment. It is a figure which shows the components information list used in the specific example of this embodiment. It is a figure which shows the solid pattern information list used by the specific example of this embodiment. It is a figure which shows the virtual layer information list used by the specific example of this embodiment. It is a figure which shows the checkpoint information table used in the specific example of this embodiment. It is a figure which shows the check range information table used in the specific example of this embodiment.

Explanation of symbols

50 Printed wiring board 51 Driver 511 Output pin 512 Earth pin 513 Power supply pin 53 Receiver 531 Input pin 532 Earth pin 55 Bypass capacitor I1 to I5 Current path GND1, GND2 Ground layer Vcc1, Vcc2 Power supply layer S1, S2 Signal layer D1-D7 Dielectric layer P1 to P42 Checkpoint 71 Pattern design layer 73, 75 Error display layer L1 to L6 Layers constituting the wiring board E1 Error display layer

Claims (5)

Check point detection means for detecting a check point for determining the necessity of layer change of the return current route on the conductor pattern from the signal line through which the signal passes and the shape of the conductor pattern adjacent to the signal line;
Interlayer connection element check means for determining whether or not there is an interlayer connection element necessary for changing the layer of the return current route within the check range obtained from the detected checkpoint and the allowable distance reference;
Check range synthesis means for synthesizing the check ranges, and summing the weights given to the check ranges for the portions where the check ranges overlap;
A substrate design support apparatus, comprising: range checking means for determining the necessity of changing the layer of the return current route according to the combined weight.   The board design support apparatus according to claim 1, wherein the check range synthesis unit synthesizes the check range determined by the interlayer connection element check unit that the interlayer connection element does not exist.   Furthermore, an interlayer connection element arrangement position automatic calculation means for automatically calculating an arrangement position of the interlayer connection element necessary for the layer change is provided within a synthesized check range in which the layer change of the return current route is determined to be necessary. The substrate design support apparatus according to claim 1 or 2.   4. An error display layer generating means for generating an error display layer for displaying, for each net, a check range determined to require layer change of the return current route. The board design support apparatus according to claim 1. A checkpoint detection function for detecting a checkpoint for judging the necessity of layer change of the return current route on the conductor pattern from the shape of the signal line through which the signal passes and the conductor pattern adjacent to the signal line;
An interlayer connection element check function for determining whether or not there is an interlayer connection element necessary for changing the layer of the return current route within the check range obtained from the detected check point and the allowable distance reference;
A check range synthesis function for synthesizing the check ranges, and adding up the weights given to the check ranges for the portions where the check ranges overlap;
A board design support program for causing a computer to realize a range check function for determining the necessity of layer change of a return current route according to the combined weight.

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