JP2007249560A - Cpu module in programmable controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure concurrency of input/output data. <P>SOLUTION: A pulse LSI writes a data transmitted from an input module 50 in an I-data area 36, while synchronized with a cycle period, and transfers a data of an O-data area 34 to an output module 60. An I-data control driver 21 copies the data written in the I-data area 36, into an I-data bank A31 or B32, and updates an up-to-date data bank register 33. A control processor 10 reads out the data from the I-data bank A31 or B32, referring to the register 33. The control processor 10 writes an output data not in the O-data area 34 but in an O-data temporary retraction buffer 37, when an O-data area exclusive flag 35 is flagged on or when a timer 14 is counted up. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a programmable controller.

In recent years, plants, factories, etc. have realized FA (factory automation) by using programmable controllers for sequence control of machines and devices.
As one form of the configuration of such a programmable controller, a CPU module for executing a program, data arithmetic processing, and the like, and an I / O module for inputting / outputting process data to / from various control target devices (usually a plurality of each) Conventionally, there is one that is connected to a bus and a CPU module performs data input / output with each I / O module via this bus.

FIG. 7 is a diagram schematically showing an example of the configuration of this conventional programmable controller.
In the figure, as described above, the CPU module 100, the input module 140, and the output module 150 are connected to the system bus 160. In the figure, only one input module 140 and one output module 150 are shown. However, as described above, there are usually a plurality of them.

The CPU module 100 includes a control processor 110, a bus LSI 130, and a shared memory 120 shared by the control processor 110 and the bus LSI 130.
The control processor 110 passes output data to the bus LSI 130 via the shared memory 120 when outputting data. The control processor 110 receives input data from the bus LSI 130 via the shared memory 120 when data is input.

  The bus LSI 130 receives input data from each input module 140 or transmits output data to each output module 150 via the system bus 160 in synchronization with the tact cycle. This is performed by the total frame method at the time of reception processing and by the multicast method at the time of transmission processing. The data input / output processing itself between the bus LSI 130, the input module 140, and the output module 150 on the system bus 160 synchronized with the tact cycle is described in, for example, an earlier application (Patent Document 1) by the present applicant. Therefore, it will not be described in detail here. Further, the detailed configurations and operations of the bus LSI 130, the input module 140, and the output module 150 are not particularly shown / explained here.

The data transfer operation in the control processor 110 will be described in more detail below.
At the time of data output, first, the control application 111 issues a data output request to the O data management driver 113. In response to this, the O data management driver 113 writes the output data in the O data area 121 in the shared memory 120. The bus LSI 130 reads out the output data stored in the O data area 121 in synchronization with the tact cycle and sends it to the system bus 160.

  At this time, if the control application 111 is configured to request data output at an arbitrary timing regardless of the tact cycle, there is no problem if the timing is as shown in FIG.

  However, a problem occurs when the timing is as shown in FIG. That is, when an output request from the control application 111 is made at a timing just before the tact interrupt t1, as shown in the figure, the tact occurs in the middle of data rewriting processing (rewriting from data a to b) in the O data area 121. At the timing of the interrupt t1, the bus LSI 130 starts reading the output data in the O data area 121 / sending the data onto the system bus 160. For this reason, the data passed to the output module 150 is data that is neither data a nor data b (data a ′ in the figure).

  Similarly, in the data input process, when a data read request from the control application 111 is made at a timing slightly before the tact interrupt t3 as shown in FIG. 9, the data read process from the I data area 122 is performed. The timing of the tact interrupt t3 is halfway, and as a result of rewriting of the I data area 122 by the bus LSI 130, the data obtained by the control application 111 is data that is neither data b nor data c (data b 'in the figure). It becomes).

  As described above, conventionally, in any of the data input process and the data output process, the control application 111 is configured to request the data input / output at an arbitrary timing regardless of the tact cycle. There was a problem that simultaneity could not be guaranteed.

The data b, data c, etc. are actually a collection of a plurality of input data or a collection of a plurality of output data, and may be called a “data group”. b, data c, etc.
JP 11-338523 A

  An object of the present invention is to enable a programmable controller to guarantee the simultaneity of input data / output data even when a data input / output request is made at an arbitrary timing irrespective of the tact cycle, and also to set the output order. It is to provide a CPU module that can be guaranteed.

  The CPU module in the first programmable controller of the present invention is a programmable controller in which a CPU module and at least one or more input modules / output modules are connected to a bus, and data transmission / reception is performed on the bus in synchronization with a tact cycle. , A bus LSI for storing input data from each input module received via the bus in synchronization with the tact cycle in the input data storage area, and input data stored in the input data storage area at an arbitrary timing Each time the input data is stored in the first storage means, the second storage means, and the input data storage area, the CPU module includes a control processor for reading the input data. Management means for alternately transferring to any one of the storage means and the second storage means For example, the control processor, the reading of the input data, first storage means, configured to perform the one of the second storage means.

  By using the CPU module configured as described above, the timing at which the control processor reads the input data at any time is, for example, immediately before the tact interrupt timing, and the data in the input data storage area is rewritten during the read processing. Even in such a case, since the data is read from the first storage means or the second storage means, the simultaneity of the input data can be guaranteed without any problem.

  The CPU module in the second programmable controller of the present invention is a programmable module in which a CPU module and at least one or more input modules / output modules are connected to a bus, and data transmission / reception is performed on the bus in synchronization with a tact cycle. In the controller, the control processor for storing the output data to be passed to each output module in the output data storage area at an arbitrary timing, and the output data stored in the output data storage area in synchronization with the tact cycle The CPU module comprising a bus LSI for sending out on a bus, wherein the control processor outputs data to be stored in the output data storage area when outputting data at a timing at which simultaneity of output data cannot be guaranteed. Output data save memory that is temporarily saved And interrupt processing means for transferring the output data saved in the output data saving storage means to the output data storage area by interrupt processing when it is time to guarantee the output data simultaneity after the saving It comprises so that it may be provided.

  According to the CPU module configured as described above, if data output is to be performed at a timing at which the simultaneity of the output data cannot be guaranteed, the data is not written to the output data storage area, and the output data saving storage means is temporarily stored. Since data is written to the, the output data simultaneity can be guaranteed.

  Further, in the CPU module in the second programmable controller, for example, the interrupt processing means causes the control processor to output the next data when there is output data saved in the output data saving storage means. Also when it is going to be noted, the said interruption process may be performed.

  In this way, the data output order can be further guaranteed.

  According to the CPU module of the programmable controller of the present invention, it is possible to guarantee the simultaneity of input data / output data even if a data input / output request is made at an arbitrary timing regardless of the cycle period. Furthermore, it is possible to guarantee the output order. These effects can be achieved without changing the control application.

Embodiments of the present invention will be described below with reference to the drawings.
In this description, “simultaneous” means that multiple input / output data (input data from multiple input modules or output data to multiple output modules) are all input at the same timing (within the same tact cycle). Or it means output.

  For example, when the operations of a plurality of devices connected to the I / O module are related to each other, the data that the control application 11 outputs to each of these devices (thus becoming a plurality of data) is the same for each device. It is important to maintain the “simultaneity” because there is a possibility that a malfunction or the like may occur if the operation is not received at the timing.

FIG. 1 is a system configuration diagram of a programmable controller according to this example.
The programmable controller shown in the figure has a configuration in which a CPU module 1, an input module 50, and an output module 60 are connected to a system bus 70. In the figure, each module is shown one by one, but there may be a plurality of each.

The CPU module 1 includes a control processor 10, a management processor 20, a shared memory 30, and a bus LSI 40.
The control processor 10 includes a control application 11, an I data management driver 12, an O data management driver 13, a timer 14, and a handler 15. The control application 11 performs input / output control processing for each input module 50 and output module 60, data calculation processing, and the like. The I data management driver 12 to handler 15 will be described later.

  The I data is input data received from the input module 50 via the system bus 70 (for example, status data of the control target device, sensor measurement data, etc.), and the O data is transmitted via the system bus 70. Output data to be passed to the output module 60 (for example, setting data such as the position and rotation speed of the control target device).

The management processor 20 includes an I data management driver 21.
The shared memory 30 is a memory shared by the control processor 10, the management processor 20, and the bus LSI 40. The shared memory 30 includes storage areas such as an I data bank A31, an I data bank B32, a latest data bank register 33, an O data area 34, an O data area exclusion flag 35, an I data area 36, and an O data temporary save buffer 37. Have.

Among the above storage areas, the I data bank A31, the I data bank B32, the latest data bank register 33, and the I data area 36 are related to data input processing.
The I data area 36 is originally a storage area for the bus LSI 40 to write I data collected from each input module 50 and read by the control processor 10, but in this example, as described later, The control processor 10 does not read data directly from the I data area 36.

  The I data bank A31 and the I data bank B32 hold a copy of the data in the I data area 36 at a certain moment. The latest data bank register 33 is a register that holds data (which may be a flag) indicating which of the two I data banks A31 and B32 holds the latest I data.

  The data copy to these two I data banks A31 and B32 and the update of the latest data bank register 33 are performed by the I data management driver 21 of the management processor 20 at the timing when the data in the I data area 36 is updated.

  The I data management driver 12 of the control processor 10 receives an I data acquisition request from the control application 11 at any time from the I data bank (A31 or B32) indicated by the latest data bank register 33. The latest I data is read and passed to the control application 11.

On the other hand, in each storage area in the shared memory 30, the O data area 34, the O data area exclusion flag 35, and the O data temporary save buffer 37 are related to data output processing.
The O data area 34 is a storage area for writing the O data and reading the bus LSI 40 when the control processor 10 outputs O data to the output module 60.

The O data area exclusion flag 35 is used to exclude access to the O data area 34.
The O data temporary save buffer 37 cannot write O data to the O data area 34 (for example, when the O data area exclusion flag 35 is set or the timer 14 is counting up; This is a buffer having a stack structure (FIFO or the like) for temporarily saving the O data (which has a FIFO structure in consideration of the case where a plurality of requests cannot be output).

  Note that the data input / output processing itself between the bus LSI 40 and each input module 50 / output module 60 is basically the same as the conventional one. That is, “a function for generating an interrupt at a constant cycle (tact cycle) according to the bus transfer rate” and “data input / output processing for each“ I / O module 50, 60 ”in synchronization with this tact interrupt” The data transfer on the system bus 70 is performed by the total frame method during the reception process and the multicast method during the transmission process. Therefore, detailed configurations and functions of the bus LSI 40, the input module 50, and the output module 60 are not particularly illustrated / explained.

Hereinafter, first, data input processing in the CPU module 1 of the programmable controller will be described with reference to FIGS. 2 and 3.
In FIG. 2, first, when the bus LSI 40 receives I data of each input module 50 via the system bus 70 for each tact cycle, the bus LSI 40 writes the I data in the I data area 36 (1). Then, a tact interrupt is generated for the management processor 20 (2).

  When receiving the tact interrupt, the I data management driver 21 of the management processor 20 reads the I data stored in the I data area 36 (3), and reads it out of either the I data bank A31 or the I data bank B32. On the other hand, the latest data bank register 33 is updated (5).

  Upon receiving an I data acquisition request from the control application 11, the I data management driver 12 can read I data from the I data bank (A 31 or B 32) indicated by the latest data bank register 33 and pass it to the control application 11.

  By doing so, there is no problem if the data in the I data area 36 is updated by the bus LSI 40 during the reading process. That is, as shown in FIG. 3, even when there is an I data acquisition request from the control application 11 just before the tact interrupt, as in FIG. Although it is rewritten, the data (b) in the I data bank B32 is not changed, so that it can be read without any problem. That is, simultaneity can be maintained (without changing the control application).

Next, data output processing in the CPU module 1 of the programmable controller in FIG. 1 will be described below with reference to FIGS.
In FIG. 4, when the O data management driver 13 receives an O data output request from the control application 11 at any time, first, the O data area exclusion flag 35 and the timer 14 are referred to, and the exclusion flag 35 is reset (OFF). If the timer 14 has not counted up, data is written in the O data area 34.

  On the other hand, if the exclusive flag 35 is set (ON) or the timer 14 is counting up, it is determined that data cannot be written to the O data area 34 at this timing, and this data is temporarily stored in the O data area. While writing to the save buffer 37, the interrupt mask (not shown) is released.

  The exclusion flag 35 is set at the start of the process in which the bus LSI 40 sends the data in the O data area 34 to the system bus 70 every tact cycle, and reset at the end. Therefore, there is a problem in rewriting data in the O data area 34 when the exclusive flag 35 is set.

  The interrupt mask is normally masked so that the interrupt by the handler 15 does not rise. However, the mask is released only when the data is saved in the O data temporary save buffer 37 so that the interrupt by the handler 15 is raised. ing. Thus, if the mask is released at the interrupt processing start timing (when the timer 14 counts up), the handler 15 transfers the data temporarily stored in the O data temporary save buffer 37 to the O data area 34. Execute interrupt processing to move to. Here, the interrupt timing by the handler 15 is assumed to be when the timer 14 counts up, but is not limited thereto.

  Then, the bus LSI 40 reads data from the O data area 34 at the next tact interrupt timing, sends it to the system bus 70, and each output module 60 receives it.

The reason why simultaneity can be maintained in the data output processing by the above processing will be described with reference to FIG.
FIG. 5 is a diagram illustrating an example of data output processing timing according to the present example.

  In the illustrated example, as in FIG. 8B, the case where the timing of the O data output request from the control application 11 becomes the tact interrupt timing during the O data area rewriting is taken as an example.

  In FIG. 5, at the timing when the O data output request is issued from the control application 11, the O data area exclusion flag 35 is reset. However, since the timer 14 is counting up, the O data management driver 13 The output data (here, data b) is not written in the O data area 34 but temporarily stored in the O data temporary save buffer 37 and the interrupt mask is released. In the figure, it may appear as if writing to the O data temporary save buffer 37 has been performed after the next tact interrupt timing t1, but this merely represents a time lag. . There is no problem even if the tact interrupt timing occurs during the writing process to the O data temporary saving buffer 37.

  Then, when the interrupt operation timing of the handler 15 is reached with the interrupt mask released (when the timer 14 counts up in this example), the handler 15 converts the data stored in the O data temporary save buffer 37 to the O data. Move to region 34. Then, an interrupt mask is set.

  Here, the timer 14 is set to count up ((tact interrupt cycle) − (maximum output point processing time)) (maximum output point processing time; a request for writing output data of the maximum output points from the control application 11). (That is, the time taken to write data to the O data area 34 when data is output to all output modules connected to the system bus 70).

  As a result, the “maximum output point processing time” is ensured between the timer 14 counting up and the next tact interrupt timing (t 2), so the data write processing to the O data area 34 by the handler 15 is always performed. It is completed before timing t2.

  Thus, at the next tact interrupt timing (t2), the bus LSI 40 can read data from the O data area 34 for which data writing processing has been completed and distribute it to each output module 60. In this case, simultaneity can be maintained (without changing the control application).

  Here, in the example shown in FIG. 5, the timer 14 starts from the time when the data distribution processing by the bus LSI 40 is completed between the timings t1 and t2 (from the time when the O data area exclusion flag 35 is reset in the figure). Until the count is increased, as described above, when the O data management driver 13 receives an O data output request from the control application 11, the O data management driver 13 performs a process of writing data in the O data area 34. For this reason, the data for which the output request is received later (referred to as data c) is written in the O data area 34 first, and the data in the O data temporary save buffer 37 (the data b) is then stored in the O data area 34 by the handler 15. It is written in the data area 34 (when writing is performed twice within the same tact cycle, it is not rewritten but becomes an additional form). In such a case, in the data distribution process by the bus LSI 40, the output order of the O data is reversed.

FIG. 6 is a diagram for explaining a method for ensuring a normal output order even in such a case.
6 is different from FIG. 4 and FIG. 5 in that the generation condition of the interrupt processing by the handler 15 is added to the above-described condition, and “when the interrupt mask is released, the output request from the control application 11 is This is the point that “if there was”.

  Thus, for example, when an output request for data c is received from the control application 11 at the timing shown in FIG. 6, an interrupt process is generated by the handler 15, and the data in the O data temporary save buffer 37 (the data b above) 34 data is rewritten. Then, an interrupt mask is set (thus, when the timer 14 counts up, interrupt processing by the handler 15 does not occur again).

  When the interrupt processing by the handler 15 ends, the O data management driver 13 writes the data c in the O data area 34. As described above, in such a case, since “rewriting” is not performed, the data stored in the O data area 34 is “b + c”. In the case of FIG. 4 and FIG. 5, it becomes “c + b” and the order is reversed, but in this example, a normal output order can be guaranteed.

It is a system block diagram of the programmable controller by this example. It is a figure for demonstrating the flow of a data input process. It is a timing diagram of data rewriting of each storage area in the data input process. It is a figure for demonstrating the flow of a data output process. It is a timing diagram of a data output process. It is a timing diagram of data output processing (guaranteed output order). It is a figure which shows schematically an example of a structure of the conventional programmable controller. (A), (b) is a figure for demonstrating the problem of the data output process in the conventional structure. It is a figure for demonstrating the problem of the data input process in the conventional structure.

Explanation of symbols

1 CPU module 10 control processor 11 control application 12 I data management driver 13 O data management driver 14 timer 15 handler 20 management processor 21 I data management driver 30 shared memory 31 I data bank 32 I data bank 33 latest data bank register 34 O data area 35 O data area exclusion flag 36 I data area 37 O data temporary save buffer 40 Bus LSI
50 Input module 60 Output module 70 System bus

Claims (3)

In a programmable controller in which a CPU module and at least one or more input modules / output modules are connected to a bus and data transmission / reception is performed on the bus in synchronization with the tact cycle, the CPU module is synchronized with the tact cycle via the bus. The CPU module includes a bus LSI that stores input data from each input module to be received in the input data storage area, and a control processor that reads the input data stored in the input data storage area at an arbitrary timing. And
First storage means, second storage means;
A management means for alternately transferring the input data to either the first storage means or the second storage means each time input data is stored in the input data storage area;
A CPU module in a programmable controller, wherein the control processor reads the input data from one of the first storage means and the second storage means. In a programmable controller in which a CPU module and at least one or more input modules / output modules are connected to a bus and data transmission / reception is performed on the bus in synchronism with the tact cycle, output data to be passed to each output module is arbitrarily selected The CPU module comprises: a control processor for storing the output data in the output data storage area; and a bus LSI for sending the output data stored in the output data storage area onto the bus in synchronization with the tact cycle. And
Output data saving storage means for temporarily saving data to be stored in the output data storage area when the control processor outputs data at a timing at which simultaneity of output data cannot be guaranteed;
An interrupt processing means for transferring the output data saved in the output data saving storage means to the output data storage area by an interruption process when it is time to guarantee the simultaneity of the output data after the saving;
A CPU module in a programmable controller, comprising:   The interrupt processing means executes the interrupt processing even when there is output data saved in the output data saving storage means, even when the control processor tries to output the next data. The CPU module in the programmable controller according to claim 2.

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