JP2007220998A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor device with a highly reliable interconnection structure by restraining generation of resist poisoning due to a reaction blocking material of a chemical amplification type resist. <P>SOLUTION: The method of manufacturing a semiconductor device has a step of depositing a first insulating film 21 on a substrate, a step of forming a first interconnection 22 by burying a conductive material in a formed groove after the groove is formed in the first insulating film 21, a step of forming a second insulating film 23 on the first insulating film 21, a step of casting ultraviolet rays in heating state to the second insulating film 23, a step of forming a third insulating film 25 on the second insulating film 23, and a step of forming a resist pattern 31 on the third insulating film 25. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a damascene structure.

  In recent years, higher integration of semiconductor integrated circuits has been promoted by miniaturization and multilayering of wiring structures. As a method for forming a high-density wiring pattern or a multilayer wiring structure, a damascene process is generally used in which copper (Cu) is used as a wiring material and the wiring is formed by flattening by a CMP (Chemical Mechanical Polishing) method. . Further, with the increase in the density of wiring patterns, it is necessary to reduce the parasitic capacitance generated between the wirings, and the use of a low dielectric constant film is being promoted as an inter-wiring insulating film and an interlayer insulating film.

  In the damascene process, it is necessary to form a wiring pattern connected to the via hole, and it is necessary to repeatedly deposit the interlayer insulating film and the etching stopper film and form the wiring pattern. When forming the wiring pattern, it is necessary to form a mask with a photoresist, and a chemically amplified resist is generally used as the photoresist. The chemically amplified resist has a mechanism for generating a hydrogen ion by photosensitivity and using this as a catalyst to chemically react the resist resin to resolve the pattern. Therefore, a very high sensitivity can be obtained because the chemical reaction of the resist resin proceeds in a chain manner with a slight amount of light.

  On the other hand, in the damascene process, when the interlayer insulating film and the etching stopper film are exposed to plasma, a substance that inhibits the chemical reaction of the chemically reactive resist is generated. The generated inhibitor stays at the interface between the interlayer insulating film and the etching stopper film. When the staying reaction inhibiting substance diffuses into the chemically amplified resist applied on the upper interlayer insulating film or the like, a resist poisoning phenomenon in which the wiring pattern is not normally resolved occurs. In particular, when the dielectric constant of the inter-wiring insulating film and the interlayer insulating film is lowered in order to reduce the parasitic capacitance between the wirings, the density of these films decreases, and the reaction inhibitor of the chemically amplified resist permeates the film. It is expected that resist poisoning will become more likely to occur.

As a solution to the resist poisoning phenomenon, an example is disclosed in which, in the damascene process, by performing a heat treatment after forming a via hole pattern, a reaction inhibitor that interferes with the chemical reaction of the resist is removed to prevent the occurrence of resist poisoning. (For example, see Patent Document 1).
Japanese Patent Application Laid-Open No. 2003-229481

  However, in the conventional method for preventing the occurrence of resist poisoning, the heat treatment is performed after the low dielectric constant film and the via hole pattern are formed on the etching stopper film. The main cause of resist poisoning is a reaction inhibitor that stays at the interface between the low dielectric constant film and the etching stopper film or a reaction inhibitor that occurs from the etching stopper film itself. In the case of a method of simply performing a heat treatment after forming a low dielectric constant film and a via hole pattern on the etching stopper film as in the conventional method for removing reaction inhibitory substances, the reaction inhibitor is generated from the source with a low dielectric constant. If it does not diffuse a long distance to the surface of the film, it will not be released out of the laminated insulating film. Further, the ease of removal of the reaction inhibiting substance varies depending on the density of the via hole pattern. As a result, there arises a problem that it is not possible to sufficiently prevent the occurrence of poor wiring reliability due to resist poisoning.

  An object of the present invention is to solve the above-mentioned conventional problems, to suppress the occurrence of resist poisoning due to a reaction inhibitor of a chemically amplified resist, and to realize a semiconductor device having a highly reliable wiring structure.

  In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device comprising a process for removing a substance that inhibits a reaction of a chemically amplified resist by irradiating ultraviolet rays or the like after forming an etching stopper film. To do.

  Specifically, in the first method for manufacturing a semiconductor device according to the present invention, a step (a) of depositing a first insulating film on a substrate, and a groove portion formed after forming a groove portion in the first insulating film. A step (b) of forming a first wiring by embedding a conductive material in the step, and a step (c) of forming a second insulating film on the first insulating film after the step (b). Irradiating the second insulating film with ultraviolet rays in a heated state (d); forming a third insulating film on the second insulating film (e); and And a step (f) of forming a resist pattern thereon.

  According to the first method for manufacturing a semiconductor device, since there is a step of irradiating the second insulating film with ultraviolet rays in a heated state, reaction inhibition of the chemically amplified resist staying in the second insulating film or the like is provided. The substance can be efficiently released from the stacked insulating films. Therefore, when the resist pattern is formed on the insulating film formed on the upper side of the second insulating film, it is possible to suppress the occurrence of resist poisoning. Therefore, a semiconductor device having a highly reliable wiring structure can be obtained. It can be realized.

  The second method for manufacturing a semiconductor device according to the present invention includes a step (a) of depositing a first insulating film on a substrate, a groove portion formed in the first insulating film, and a conductive property in the formed groove portion. A step (b) of forming a first wiring by embedding a material, a step (c) of forming a second insulating film on the first insulating film after the step (b), and a second Irradiating the insulating film with an electron beam in a heated state (d), forming a third insulating film on the second insulating film (e), and on the third insulating film And a step (f) of forming a resist pattern.

  According to the second method for manufacturing a semiconductor device, since the step of irradiating the second insulating film with an electron beam in a heated state is provided, the reaction of the chemically amplified resist staying in the second insulating film or the like The inhibitory substance can be efficiently released from the laminated insulating film. Therefore, when the resist pattern is formed on the insulating film formed on the upper side of the second insulating film, it is possible to suppress the occurrence of resist poisoning. Therefore, a semiconductor device having a highly reliable wiring structure can be obtained. It can be realized.

  In the first and second semiconductor device manufacturing methods, the step (d) is preferably performed after the step (c) and before the step (e). With such a structure, the release of the inhibitor is not inhibited by the third insulating film, and the removal efficiency of the inhibitor can be improved.

  Further, the step (d) may be performed after the step (e) and before the step (f). Since ultraviolet or electron beam irradiation passes through the insulating film, even when the third insulating film is deposited on the second insulating film, the inhibitory substance can be efficiently released.

  In the first and second semiconductor device manufacturing methods, it is preferable that at least one of the first insulating film and the third insulating film has a relative dielectric constant of 3 or less.

  In the first and second semiconductor device manufacturing methods, the second insulating film is preferably a film containing nitrogen.

  According to the method for manufacturing a semiconductor device of the present invention, it is possible to realize a semiconductor device having a highly reliable wiring structure by suppressing the occurrence of resist poisoning due to a reaction inhibitor of a chemically amplified resist.

  A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a method of manufacturing a semiconductor device according to an embodiment in the order of steps. In FIG. 1, only the wiring portion is shown.

  First, as shown in FIG. 1A, after forming a first insulating film 21 made of a carbon-containing silicon oxide film (SiOC) having a relative dielectric constant of 3 or less on a substrate (not shown), A resist is applied on the insulating film 21, and a resist pattern (not shown) for wiring trenches is formed by lithography. Next, using this resist pattern as a mask, dry etching is performed to form a groove, and then the resist is removed by ashing to form a wiring groove in the first insulating film 21. Subsequently, a barrier metal 22a made of tantalum nitride (TaN) is formed in the wiring trench by sputtering, and a conductive film 22b made of Cu is embedded by electroplating. Thereafter, excess barrier metal 22a and conductive film 22b protruding from the wiring trench are removed by a chemical mechanical polishing (CMP) method to form a first metal wiring 22 composed of the barrier metal 22a and the conductive film 22b.

  Next, as shown in FIG. 1B, a second insulating film 23 made of SiCN containing carbon and nitrogen is chemically formed so as to cover the first metal wiring 22 on the first insulating film 21. It is formed using a vapor deposition (CVD) method. The second insulating film 23 functions as a metal diffusion preventing film that prevents metal diffusion from the first metal wiring 22. Further, it functions as an etching stopper film in a step of forming a via hole described later.

After forming the second insulating film 23, as shown in FIG. 1C, a UV irradiation heat treatment for irradiating ultraviolet rays (UV) in a heated state is performed. Thereby, for example, the OH ⁻ and CH ₃ formed by destroying the Si—O—CH ₃ bond and the Si—CH ₃ bond of the first insulating film 21 by the plasma when the second insulating film 23 is formed. A base such as NH ₃ ^— formed by a reaction between a base such as ⁻ and nitrogen in the second insulating film and moisture in the atmosphere is efficiently discharged from the laminated insulating film. Accordingly, it is possible to prevent the reaction-inhibiting substance of the chemically amplified resist that causes the resist poisoning from occurring in the interface between the first insulating film 21 and the second insulating film 23 and in the second insulating film 23. . UV irradiation heat treatment, while performing UV irradiation at 10mW / cm ² ~200mW / cm ² of about illuminance example a pressure in an atmosphere of 2.6 Pa (0.02 Torr) ~ normal pressure, heated to a temperature of 350 ° C. to 450 ° C. The processing to be performed may be performed.

  Next, as shown in FIG. 1D, a third insulating film 25 made of SiOC having a relative dielectric constant of 3 or less is formed on the second insulating film 23 by the CVD method. Subsequently, a fourth insulating film 26 made of a Si oxide film is formed on the third insulating film 25 by using the CVD method. Subsequently, a resist is applied to the surface of the fourth insulating film 26, and a via hole resist pattern 31 is formed by lithography.

  Next, as shown in FIG. 1E, dry etching is performed using the resist pattern 31 as a mask, and then ashing is performed. Via holes 28a penetrating the third insulating film 25 and the fourth insulating film 26 are formed. Form. The second insulating film 23 also functions as an etching stopper film when forming the via hole 28a. Further, a resist is again applied to the surface of the fourth insulating film 26, and a resist pattern 32 for wiring trenches is formed by using a lithography method. In this embodiment, since the UV irradiation heat treatment is performed, the reaction inhibitor of the chemically amplified resist hardly stays in the second insulating film. Therefore, resist poisoning does not occur when the resist pattern 31 and the resist pattern 32 are formed.

  Next, as shown in FIG. 1F, dry etching is performed using the resist pattern 32 as a mask, and then ashing is performed to form wiring grooves in the third insulating film 25 and the fourth insulating film 26, Further, the exposed portion of the second insulating film 23 from the via hole 28a is removed to expose the first metal wiring 22. Thereafter, a barrier metal 27a made of TaN is formed by sputtering in the wiring groove, and then a conductive film 27b made of Cu is formed by electroplating. Subsequently, the excess barrier metal 27a and the conductive film 27b protruding from the wiring trench are removed by CMP to form the second metal wiring 27 and the via 28 made of the barrier metal 27a and the conductive film 27b. The first metal wiring 22 and the second metal wiring 27 are electrically connected through a via 28.

  Below, the effect of the process which irradiates UV to the surface of the 2nd insulating film 23 in a heating state is demonstrated.

2 (a) and 2 (b) show the amount of the reaction inhibitor desorbed from the second insulating film 23 formed as described above, and FIG. 2 (a) shows a sample after performing the UV irradiation heat treatment. (B) shows the desorption amount of the reaction inhibitory substance from the sample before performing the UV irradiation heat treatment. In FIG. 2, after the second insulating film 23 is deposited by the method described above, the laminated structure of the formed insulating film is cut out to a predetermined size before and after UV irradiation in a heated state. Used. The amount of desorption of the reaction inhibitor was determined by measuring the amount of ammonia (NH ₃ ) desorption from the sample by the TDS (Thermal Desorption Spectroscpy) method. In FIG. 2, the vertical axis represents the signal strength of the TDS apparatus.

As shown in FIG. 2B, a large amount of NH ₃ is desorbed from the sample before the UV irradiation heat treatment. On the other hand, as shown in FIG. 2A, only a small amount of NH ₃ is desorbed from the sample after the UV irradiation heat treatment, and the sample stays in the second insulating film 23 by the UV irradiation heat treatment. It is clear that the amount of base such as NH ₃ can be greatly reduced.

This is because reaction inhibiting substances such as NH ₃ staying in the interface between the first insulating film and the second insulating film and in the second insulating film are decomposed by performing UV irradiation, and the efficiency of the insulating film is increased. It is thought that it is due to being released well. That is, the high energy of UV light has the effect of breaking the bond between the reaction inhibitor and the insulating film material or desorbing the reaction inhibitor adsorbed on the surface of the insulating film. For this reason, the reaction-inhibiting substance is easily moved in the insulating film by UV light irradiation, and can be easily discharged from the insulating film by thermal energy. Therefore, an efficient removal effect of the reaction inhibitor can be obtained.

  In this embodiment, the UV irradiation heat treatment is performed before the third insulating film 25 is formed, but may be performed after the third insulating film 25 is formed. Since the UV light is transmitted through the third insulating film 25 and acts on the second insulating film 23 under the third insulating film 25, the same effect as that obtained when the UV irradiation heat treatment is performed before the third insulating film 25 is formed. can get.

  The same effect can be obtained by irradiating EB (Electron Beam) having a similar energy band instead of UV light. When performing EB irradiation, for example, heat treatment may be performed at a temperature of 350 ° C. to 450 ° C. while performing EB irradiation with a pressure of 26000 Pa to 2.6 Pa and an acceleration voltage of 10 kV to 20 kV.

  The second insulating film may be a stacked film of two or more films in which at least one film contains nitrogen. For example, as shown in FIG. 3, a lower film 23a and an upper film 23b made of SiOCN containing carbon and nitrogen are sequentially formed as the second insulating film using a CVD method. The lower layer film 23a is a film made of SiOCN in which the atomic percentage value of oxygen atoms (O) in the film is lower than the atomic percentage value of nitrogen atoms (N), and the upper layer film 23b is formed of O in the film. A film made of SiOCN or a film made of SiN has a higher atomic percentage value than the atomic percentage value of N. With such a configuration, diffusion of metal atoms from the metal wiring 22 can be prevented, and occurrence of peeling at the interface between the first insulating film 21 and the second insulating film 23 can be suppressed.

  Further, although both the first insulating film 21 and the third insulating film 25 are low dielectric constant insulating films, the same effect can be obtained in the case of a normal insulating film such as a silicon oxide film.

  The method for manufacturing a semiconductor device according to the present invention suppresses the occurrence of resist poisoning due to a reaction inhibitor of a chemically amplified resist, and can realize a semiconductor device having a highly reliable wiring structure. A method for manufacturing a semiconductor device, particularly a damascene structure It is useful as a method for manufacturing a semiconductor device having

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention to process order. (A) and (b) show the effect of the UV irradiation heat treatment in the method for manufacturing a semiconductor device according to one embodiment of the present invention, and (a) shows the removal of the reaction inhibitor from the sample after the UV irradiation heat treatment. It is a graph which shows separation amount, (b) is a graph which shows the desorption amount of the reaction inhibitory substance from the sample before performing UV irradiation heat processing. It is sectional drawing which shows the other example of the semiconductor device which concerns on one Embodiment of this invention.

Explanation of symbols

21 1st insulating film 22 1st metal wiring 22a Barrier metal 22b Conductive film 23 2nd insulating film 25 3rd insulating film 26 4th insulating film 27 2nd metal wiring 27a Barrier metal 27b Conductive film 28 Via 28a Via hole 31 Resist pattern 32 Resist pattern

Claims (6)

Forming a first insulating film on the substrate (a);
(B) forming a wiring by embedding a conductive material in the formed groove after forming the groove in the first insulating film;
A step (c) of forming a second insulating film on the first insulating film after the step (b);
Irradiating the second insulating film with ultraviolet rays in a heated state (d);
Forming a third insulating film on the second insulating film (e);
And a step (f) of forming a resist pattern on the third insulating film. Depositing a first insulating film on the substrate (a);
(B) forming a first wiring by embedding a conductive material in the formed groove after forming a groove in the first insulating film;
A step (c) of forming a second insulating film on the first insulating film after the step (b);
Irradiating the second insulating film with an electron beam in a heated state (d);
Forming a third insulating film on the second insulating film (e);
And a step (f) of forming a resist pattern on the third insulating film.   The method of manufacturing a semiconductor device according to claim 1, wherein the step (d) is performed after the step (c) and before the step (e).   The method of manufacturing a semiconductor device according to claim 1, wherein the step (d) is performed after the step (e) and before the step (f).   5. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the first insulating film and the third insulating film has a relative dielectric constant of 3 or less. .   The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a film containing nitrogen.

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