JP2007215389A - Power semiconductor element and semiconductor circuit using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor element in which a parasitic diode is switched without being forward-biased and which performs a reflux mode operation, and to provide a small and inexpensive semiconductor circuit which is suitable for high reliable driving with a low loss. <P>SOLUTION: A threshold voltage at the time of an opposite direction operation of the power semiconductor element is lowered compared to a forward voltage of a diode between a gate and a drain. In a reflux mode when an inductive load is driven, a main component in all currents flowing to a drain terminal is set not to be a parasitic diode current but an FET current. The diode between the gate and the drain is not easily forward-biased and a Schottky diode connected between gate and drain terminals of a power FET is installed immediately below a gate pad for overvoltage protection. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wide band gap semiconductor device and a driving circuit thereof, and particularly, a small and low cost semiconductor circuit suitable for driving an inductive load such as a motor and a coil with low loss and high reliability, and the semiconductor circuit. A semiconductor device structure that is suitable to be provided is provided.

  Wide band gap semiconductor elements such as SiC (silicon carbide), GaN (gallium nitride), and diamond are characterized by being capable of high pressure, low loss, and high frequency. For this reason, a high voltage, low loss, and high frequency can be achieved by replacing the inverter circuit composed of a conventional IGBT using Si with an inverter circuit composed of SIT using SiC.

  When driving an inductive load with a bridge circuit, when the upper or lower arm power element is turned off, reverse voltage is applied to the drain and source terminals of the power element on the opposite side, and the current flows in the reflux mode. However, at this time, a method of connecting a flywheel diode in parallel with a wide band gap semiconductor such as SiC or GaN has been considered so that a current flows with low loss from the source terminal to the drain terminal.

  A method of reducing energy loss due to reverse recovery of the freewheeling diode using a SiC Schottky diode as a flywheel diode is also considered.

  Further, as a protection of the SiC power device, a method of incorporating a diode in the same chip is considered.

  Patent Document 1 discloses an inverter circuit using SiC SIT, and a reflux diode is provided in parallel with each SiC SIT. In Patent Document 2, a SiC Schottky diode is used as a flywheel diode for IGBT reflux. Patent Document 3 discloses a semiconductor device in which a protection diode is built in the same chip as the SiC power device. A polycrystalline silicon diode is formed on an insulating layer and used as an overvoltage protection diode or a temperature detection diode.

Japanese Patent Laid-Open No. 2001-196605 (Description of FIG. 9, paragraphs (0055) and (0057)) JP 2001-245475 A (Description of paragraphs (0021) to (0023) from FIG. 1) Patent Application Publication US 2003 / 0042538A1 Japanese Patent Application Laid-Open No. 2001-196605 (Description of paragraphs (0055), (0055) and (0072,0074))

  In the above prior art, the one disclosed in Patent Document 1 is provided with a free-wheeling diode in parallel with each SiC SIT. As this free-wheeling diode, there is no Schottky that does not accumulate minority carriers and can increase the voltage. A diode is suitable. However, since a high-voltage Schottky diode exceeding 300 V cannot be realized with silicon, an expensive Schottky diode using a wide band gap semiconductor such as SiC needs to be used externally as in Patent Document 2. For this reason, there is a problem that the cost of the inverter becomes high. The device described in Patent Document 3 has a problem that an effective semiconductor chip region is sacrificed because an overvoltage protection diode is arranged around the semiconductor chip. In addition, when the silicon layer is formed in the SiC process, there is a problem that the manufacturing process becomes complicated.

  An object of the present invention is to provide a driving circuit suitable for a wide bandgap semiconductor, and in particular, a power semiconductor that operates with low loss in a reflux mode without a wide bandgap semiconductor Schottky diode between the drain and source terminals. It is an object to provide a semiconductor driving circuit capable of driving an element with high reliability.

  The semiconductor circuit of the present invention is a circuit for applying a reverse voltage to the FET as described above so that the characteristics of the wide bandgap semiconductor element used in the circuit operate under special conditions, and the shot for refluxing. The semiconductor circuit does not need to use a key diode. Alternatively, the semiconductor circuit of the present invention can be realized by a small area Schottky diode that can be formed directly under the gate pad of the semiconductor chip, and used for overvoltage protection. There is.

  According to the present invention, a wide band gap semiconductor drive circuit with high reliability and low cost can be realized.

  In the semiconductor circuit of the present invention, a power FET including a drain terminal, a source terminal, a gate terminal for controlling an FET current flowing between the drain terminal and the source terminal, and a parasitic diode having the drain terminal as a cathode exists. A control circuit for controlling the gate-source voltage of the power FET, and a load including an inductive element that supplies current from the power FET, and when the power FET is in an off drive state by the control circuit, It has an operation in which a reverse voltage is applied between the drain and source of the power semiconductor FET, and at this time, the component of the FET current flowing from the source terminal to the drain terminal is larger than the current component of the parasitic diode. I did it. For this reason, a power FET was used in which the threshold voltage for reverse operation of the FET was lower than the forward voltage of the parasitic diode. Furthermore, in order to realize such a power FET, a wide band gap semiconductor such as SiC, GaN, or diamond was used.

  A power FET having a drain terminal, a source terminal, a gate terminal for controlling an FET current flowing between the drain terminal and the source terminal, and a parasitic diode having the drain terminal as a cathode; A control circuit that controls a gate-source voltage; and a load that includes an inductive element that supplies current from the power FET. The control circuit includes a high-voltage terminal that is separated from the voltage of the source terminal by a first voltage; A low voltage terminal that is separated from the voltage of the source terminal by a second voltage; an on-switching element is provided between the high voltage terminal and the gate terminal of the power FET; and the low voltage terminal and the gate terminal of the power FET An off switch element is provided between the drain terminals of the power FET when the off switch element is on. Lower than the voltage of the low voltage terminal, having an operation to flow a current to the drain terminal from the source terminal, this time, the main current flowing from the source terminal to the drain terminal is set to be FET current power FET.

  Further, the gate terminal of the power FET has a drain terminal, a source terminal, a gate terminal for controlling an FET current flowing between the drain terminal and the source terminal, and a parasitic diode having the drain terminal as a cathode. An anode terminal of one diode is connected, and a cathode terminal of the first diode is connected to the drain terminal so that a forward voltage of the parasitic diode is higher than a forward voltage of the first diode. The first diode is formed directly under the gate pad.

  Furthermore, the breakdown voltage of the first diode is set lower than the voltage obtained by subtracting the threshold voltage of the power FET from the drain-source breakdown voltage. Further, the first diode is a Schottky diode.

  Furthermore, in order to turn on the power FET, the switching element for turning on the power MOSFET is turned on by charging the gate-source voltage in the positive direction via the capacitor to turn off the power FET. In this case, by turning on a switching element for turn-off, the gate-source voltage is charged in the negative direction via the capacitor.

  Furthermore, a current path for supplying a gate current necessary for maintaining the ON state of the power FET to the power FET is provided.

  FIG. 1 is a circuit diagram of the present embodiment, FIG. 2 is a characteristic diagram of a semiconductor device for obtaining desired characteristics in the semiconductor circuit of the present embodiment, and FIG. 3 is a drive waveform of the semiconductor circuit of the present embodiment. It is. FIG. 4 is a cross-sectional view and a plan view of a semiconductor device that realizes an element circuit portion of the semiconductor circuit of this embodiment. Although a circuit using an n-channel junction FET is shown for the power semiconductor elements 101 and 102, other power FETs other than the junction FET such as SIT (electrostatic induction FET) and MESFET (metal semiconductor junction FET) The same effect can be obtained by using a power semiconductor element such as a bipolar transistor having a large current gain. In this embodiment, the power semiconductor elements 101 and 102 will be described with a circuit assuming a normally-off power semiconductor element having a threshold voltage of 2.5 V to 0 V.

  In this embodiment, the power semiconductor element 101 for the high side switch is connected between the high voltage terminal 503 and the output terminal 505, and the power for the low side switch is connected between the output terminal 505 and the reference voltage terminal 504. The semiconductor element 102 is wired, and the inductive loads 104 u, 104 v, 104 w whose power is controlled by the power semiconductor element 101 for the high side switch and the power semiconductor element 102 for the low side switch are connected to the output terminal 505. It is a bridge circuit. 104u, 104v, and 104w are inductive loads such as motors, and 505u, 505v, and 505w are U-phase, V-phase, and W-phase output terminals, respectively, but in this embodiment, only the U-phase circuit is used due to space limitations. It is shown. A control circuit 110 for the high side switch is provided to control the power semiconductor element 101 for the high side switch, and a control circuit 111 for the low side switch is provided to control the power semiconductor element 102 for the low side switch.

  In this embodiment, the high-side switch terminal 110 of the high-side switch control circuit 110 is 506, and the low-voltage side voltage terminal is the same as the source terminal of the power semiconductor element 101 and is connected to the output terminal 505. The high-side voltage terminal of the low-side switch control circuit is 507, and the low-voltage side voltage terminal is the same as the source terminal of the power semiconductor element 102 and is connected to the reference voltage terminal 504. The capacitor 114 and the diode 113 constitute a bootstrap circuit that supplies a power supply voltage to the high-side control circuit 110.

  Since the control circuit 110 for the high side switch and the control circuit 111 for the low side switch have the same circuit configuration and operate in the same manner, the following description will be mainly given of the operation of the power semiconductor element 101 and the control circuit 110 thereof.

  The first characteristic of the semiconductor circuit of this embodiment is that the characteristics of the power semiconductor element are that the threshold voltage (current flows from the source terminal to the drain terminal) in the reverse operation (the current flows from the source terminal to the drain terminal). This is a normally-off type device in which the required gate terminal voltage to the drain terminal) is lower than the forward voltage of the parasitic diode (about 2.5 V in SiC), and the characteristics of the wide band gap semiconductor device as shown in FIG. Is to have. That is, although the static characteristics in the reverse direction in FIG. 2 are used, the switching element used in this circuit is a diode between the gate terminal and the drain terminal when the voltage at the source terminal is higher than that at the drain terminal. Before the current flows, the FET current flows from the source terminal to the drain terminal even in the off drive state where the gate-source voltage is zero volts. For this reason, even when the return mode is set, the return current can flow without the parasitic diode being strongly forward biased. For this reason, even if a Schottky diode is not connected between the drain and source, it is possible to prevent delay and increase in loss due to minority carrier accumulation.

  Further, since the drain-source voltage can be lowered in the reflux mode in which current flows from the drain terminal to the source terminal, the loss is small.

  The second feature of the semiconductor circuit of this embodiment is that the power semiconductor elements 101 and 102 are turned on by charging the gate-source voltage in the positive direction via capacitors 180u and 180d in order to turn on the power semiconductor elements 101 and 102. In order to turn off the transistors 101 and 102, the gate-source voltage is charged in the negative direction via the capacitors 180u and 180d by turning on the turn-off switching element. In a normal circuit, a negative power supply is required to apply a negative gate voltage. However, only a positive power supply is required for the drive circuits 110 and 111 of this embodiment, and the drive circuit can be simplified and the cost can be reduced. A conventional bootstrap circuit can also be used.

  The reason for applying a negative gate voltage between the gate and the source is as follows. A junction FET, SIT (electrostatic induction FET), MESFET (metal semiconductor junction FET), and bipolar transistor, which are well studied as power semiconductor elements of a wide band gap semiconductor, have a threshold voltage of about 2.5 V for being turned on. The following is lower than that of silicon power MOSFETs and IGBTs. For this reason, a malfunction called self-turn-on that is turned on under the influence of the parasitic capacitance between the drain and the gate after the power semiconductor element is cut off is likely to occur. Therefore, in this embodiment, the self-turn-on is prevented by applying a negative gate voltage between the gate and the source at the time of interruption.

  Further, in this embodiment, only when the gate voltage is applied, a large current is passed through the gate through the capacitor 180u to turn on the power semiconductor element 101 at a high speed, and the gate current Igs when the on state is maintained has a high resistance 161u. It is characterized in that the gate current of the power semiconductor element 101 which is a junction FET is kept low by using it. That is, the resistor 161u functions as a current path for supplying current to the gate terminal when the power semiconductor element 101 is in the on state. Further, the gate-source voltage of the power semiconductor element 101, which is a junction FET sufficiently lowered at the time of turn-off, is driven to return the gate-source voltage to near the threshold voltage in the off state by the resistor 162u and the diode 131u. did. That is, the waveforms of the drive gate voltage Vgs, the gate-source voltage Vgs0 of the junction FET, and the gate current Igs are temporarily increased when turning on as shown in FIG. 3, and between the gate and source when turning off. Drive to temporarily lower the voltage. As a result, high-speed turn-on and turn-off due to a large gate current, high-resistance 161u keeps the on-state in a low gate current state, and the gate-source after the turn-off is greatly reduced to a negative voltage to prevent self-turn-on, and then turn off By returning the gate-source voltage to near the threshold voltage during the state, the power semiconductor element 101 is automatically turned on quickly when the mode is switched to the reflux mode, so that the loss can be reduced.

  For example, if the voltage between the terminal 506 and the high-voltage side voltage terminal 507 is 12 V, the gate current for maintaining the ON state can be suppressed to 100 μA or less by setting the resistance 401 to about 1 kΩ. Further, the capacitance values of the capacitors 180u and 180v are set to be larger than several times the input capacitance values of the power semiconductor devices 101 and 102 so that the gate-source voltage becomes negative after the power semiconductor device is cut off. The resistor 162u is set to a relatively low value of about several tens of ohms.

  Further, when a resistor (NTC thermistor) having a temperature sensor function in which the resistance value decreases as the temperature increases is used as the high resistance 401, the junction temperature of the power switching element increases and the drain current is likely to decrease. Can automatically increase the gate current (base current) to suppress the decrease in drain current.

  The third feature of the semiconductor circuit of this embodiment is that a Schottky diode 140u is provided between the drain terminal and the gate terminal, particularly when the power semiconductor element 101 is a junction FET or SIT element. When the forward voltage of the Schottky diode is lower than the forward voltage (about 2.5 V in SiC) of the parasitic diode existing between the drain terminal and the gate terminal of the power FET which is the power semiconductor element 101, It is not necessary to forward bias the parasitic diode between the gate and the drain even in the reflux mode in which the voltage at the source terminal is higher. The forward drop voltage of the diode 140u is preferably selected to be higher than the maximum gate voltage of the power semiconductor element 101. Thereby, when the power semiconductor element 101 is in the ON state, a leakage current flowing from the gate terminal to the drain terminal via the diode 140u can be suppressed. This condition is easier to satisfy when the power semiconductor element 101 is a normally-on type. Further, when the breakdown voltage of the diodes 140u and 140d is lowered by about 5V to 30V from the value obtained by subtracting the threshold voltage of the power semiconductor element 101 from the drain-source breakdown voltage of the power semiconductor element 101, the diodes 140u and 140d Can be operated as an active clamp diode that prevents the breakdown due to the overvoltage by turning on the gate before the overvoltage is applied between the drain and the source of the power semiconductor element 101, and has the effect of improving the reliability. . That is, when the power semiconductor element 101 is a normally-off semiconductor element, the breakdown voltage of the diode 140u needs to be lower than the drain-source breakdown voltage of the power semiconductor element 101, but the power semiconductor element 101 is a normally-on semiconductor element. In this case, since the threshold voltage is negative, the drain-source breakdown voltage of the power semiconductor element 101 and the breakdown voltage of the diode 140u may be the same. The diode 140u can use a region directly under the gate pad of the power semiconductor element 101.

  FIG. 4 shows a plan view and a cross-sectional view of the semiconductor device of this embodiment in which the diode 140u is formed immediately below the gate pad of the power semiconductor element 101 chip. In FIG. 4, reference numeral 1 is a back drain metal layer, 2 is a high-concentration n-type drain semiconductor region, 3 is a low-concentration n-type drain semiconductor region, 4a is a source region of the high-concentration n-type region, and 5a is in ohmic contact. The source metal layer 5d is a metal layer for Schottky junction between the gate metal layer 9b and the low concentration n-type drain semiconductor region 3, 6a is a high concentration p-type gate region, and 6b is a high concentration p-type on the anode side of the diode 140u. A semiconductor region, 6c is a floating high concentration p-type semiconductor region separated by a high concentration n-type region 4c, 7a is a low concentration p-type gate region, 7b and 7c are low concentration p-type semiconductor regions, and 8 is The insulating layer, 9a is a second source metal layer, and 9b is a second gate metal layer. As shown in FIG. 4, in the semiconductor device of this embodiment, since the Schottky diode 140u is formed immediately below the gate pad, an increase in chip area can be prevented. In this embodiment, the high-concentration p-type semiconductor region 6b is spaced apart from the drain-source withstand voltage of the power semiconductor element 101 so that the breakdown voltage of the Schottky diode 140u is about 5 to 30V. Electric field concentration is likely to occur at both ends of the high-concentration p-type semiconductor region 6b, which is wider than the gate region 6a. In the case where the power semiconductor element 101 is a normally-on type semiconductor element having a threshold voltage of about −5 V to −30 V, the diode 140 u has the same breakdown voltage between the drain and source of the power semiconductor element 101 and the withstand voltage of the diode 140 u. Can be used as an active clamping diode. In such a case, the withstand voltage of the high concentration p-type semiconductor region 6b and the withstand voltage of the high concentration p-type gate region 6a may be the same. The concentration may be the same as that of the p-type gate region 6a. However, the breakdown voltage between the high-concentration p-type gate region 6a to which the gate is connected and the high-concentration p-type semiconductor region 6b to which the source is connected is high even when the gate terminal voltage becomes the minimum voltage. It is necessary to arrange them apart so as to ensure a breakdown voltage so as not to breakdown between the type semiconductor region 6b and the high-concentration p-type gate region 6a to which the source is connected.

  FIG. 5 shows this embodiment. In this embodiment, the power semiconductor element is a power MOSFET. In FIG. 2, the parasitic diode exists between the drain terminal and the gate terminal, but in the case of the present embodiment shown in FIG. 3, the threshold voltage of the reverse operation (operation in which current flows from the source terminal to the drain terminal) is parasitic. The threshold voltage of the power MOSFET is made lower than the forward voltage of the diode (about 2.5 V for SiC), and the maximum gate-source voltage is also equal to or less than the forward voltage of the parasitic diode (for example, 2.5 V). ). Such a condition is difficult to realize when silicon is used as the power semiconductor element because the forward voltage of the parasitic diode is about 0.6 V or less, but a wide band in which the forward voltage of the parasitic diode is relatively high. In the case of gap semiconductors, this has become possible. In the case of the present embodiment, the same effect as in the first embodiment is obtained.

  FIG. 6 shows this embodiment. In this embodiment, the diode 140u is not a Schottky diode but a pn junction diode. That is, 5b is a metal layer for ohmic contact, and 6d is an anode side p-type semiconductor region. In the case of the present embodiment, it is impossible to prevent minority carriers from flowing into the drain region in the reflux mode. However, as in FIG. 3, the protection function when the drain voltage becomes an overvoltage can be realized without increasing the chip area. It has the characteristics. That is, also in this embodiment, the breakdown voltage of the pn junction diode 140u is lowered by about 5V to 30V from the value obtained by subtracting the threshold voltage from the drain-source breakdown voltage of the power semiconductor element 101 as in the case of the first embodiment. Therefore, the diode 140u can be operated as an active clamp diode that prevents the breakdown due to the overvoltage by turning on the gate before the overvoltage is applied between the drain and the source of the power semiconductor element 101, thereby improving the reliability. There is an effect of doing. Further, since the diode 140u can use a region immediately under the gate pad of the power semiconductor element 101, the above-described effect can be obtained without increasing the chip area of the power semiconductor element 101.

  Even in this embodiment, the threshold voltage of the power semiconductor element needs to be lower than the forward drop voltage of the diode 140u, and the maximum value of the gate voltage that can be applied between the gate and source of the power semiconductor element 101 is It is below the forward drop voltage of the diode 140u. Therefore, also in this embodiment, the structure is suitable when the power semiconductor element 101 is a normally-on semiconductor element. When the power semiconductor element 101 is a normally-on semiconductor element having a threshold voltage of about −5V to −30V, the diode 140u is activated even if the drain-source breakdown voltage of the power semiconductor element 101 and the breakdown voltage of the diode 140u are the same. It can be used as a clamping diode. In such a case, the breakdown voltage of the high-concentration p-type semiconductor region 6b and the breakdown voltage of the high-concentration p-type gate region 6a may be the same as in the first embodiment. The interval 6b may be the same as that of the high-concentration p-type gate region 6a in the gate portion. The breakdown voltage between the high-concentration p-type semiconductor region 6b to which the gate is connected and the high-concentration p-type gate region 6a to which the source is connected is high even when the gate terminal voltage becomes the lowest voltage. It is necessary to arrange them apart so as to ensure a breakdown voltage so as not to breakdown between the type semiconductor region 6b and the high-concentration p-type gate region 6a to which the source is connected.

  Although not shown in the drawing, the circuit of FIG. 1 can be further reduced in size by forming a capacitor 180u by laminating a dielectric material and an electrode layer on the gate pad region.

  FIG. 7 shows this embodiment. In this embodiment, the embodiment is simplified as compared with FIG. In this embodiment, the constant voltage circuit using the Zener diode 141u is not used, and the gate-source diode of the power semiconductor element 101 is used instead of the Zener diode 141. This embodiment is possible because there is a diode in which the current increases exponentially with the voltage applied between the gate and the source like the junction FET of the power semiconductor element 101. By optimizing the value of the capacitor 180u, the gate voltage of the power semiconductor element 101, which is a junction FET, can be prevented from becoming excessive. The resistor 163u is a high resistance of about 100 kΩ provided to maintain an off state when no voltage is applied to the gate of the power semiconductor element 101 that is a junction FET, but may not be required. In the present embodiment, a power semiconductor element which is a junction FET by supplying a leakage current flowing through a parallel circuit composed of a gate-source diode of the power semiconductor element 101 which is a junction FET and a resistor 163u in the ON state via the resistor 161u. 101 is kept on.

  In this embodiment, there is no current path composed of the resistor 162u and the diode 131u that rapidly returns the gate-source voltage to zero in the off state as shown in FIG. In addition, a diode 149u is provided so that the electric charge stored in the capacitor 180u is difficult to be discharged through the resistor 161u. Therefore, the gate drive waveform is as shown in FIG. As can be seen from the comparison of the waveforms in FIG. 4 and FIG. 8, in the circuit of FIG. 1, it is necessary to charge the capacitor 180 u each time the power semiconductor element 101, which is a junction FET, is turned on. The charged voltage is difficult to be discharged in the off state. For this reason, the charge / discharge power of the gate can be reduced.

  However, in the case of the present embodiment, since the mode is the reflux mode, the voltage between the gate and the source when the current starts to flow automatically from the source to the drain of the power semiconductor element 101 which is a junction FET remains lower. There is a possibility that the drain-source voltage at which the power semiconductor element 101 that is a junction FET starts to turn on in the reverse direction becomes higher than in the case of the first embodiment and the loss increases. For this reason, it is desirable that the power semiconductor element 101, which is a junction FET, is quickly turned on and operated in the reverse direction when it enters the reflux mode. In the present embodiment, it is desirable to provide a flywheel diode between the drain and the source in order to easily reduce the loss in the reflux mode. Other features are the same as those of the first embodiment and have the same effects.

  FIG. 9 shows this embodiment. This embodiment is characterized in that by providing the diodes 146u and 147u, the value of the gate resistance 164u related to the turn-on speed and the value of the gate resistance 165u related to the turn-off speed are set separately. As a result, noise due to excessive high-speed switching can be reduced and optimization can be performed so as to reduce switching loss. Here, the resistor 161u provided in parallel with the capacitor 180u is a high resistance for flowing a gate current necessary for continuing to turn on the power semiconductor element 101 which is a junction FET as in FIG. Other features are the same as those of the fourth embodiment and have the same effects.

  FIG. 10 shows this embodiment. The present embodiment is characterized in that a constant voltage circuit for preventing an excessive voltage from being applied between the gate and the source 101 is realized by the diode array 146u. Compared with the Zener diode 141u of the first embodiment, the diode array 144u has an advantage that it is easy to clamp the gate voltage of the power semiconductor element 101 which is a junction FET because a large current can flow.

  In the present embodiment, since the diode array 144u is assumed to be silicon diodes having a low forward drop voltage, it is arranged in multiple stages. However, as with the power semiconductor element 101 that is a junction FET, the diode array 144u is 1 when a wide band gap semiconductor is used. It does not matter if it is individual. The diode 144u may be formed on a chip of the power semiconductor element 101 that is a junction FET. Other features are the same as those of the fourth embodiment and have the same effects.

  FIG. 11 shows this embodiment. This embodiment is characterized in that the transistor 123u is added so that the constant voltage effect is maintained even if the size of the constant voltage Zener diode 149u for clamping the gate voltage is small. In this embodiment, when the Zener diode 149u breaks down, the transistor 123u is turned on to suppress an excessive rise in the gate voltage of the power semiconductor element 101 that is a junction FET. For this reason, the gate voltage of the power semiconductor element 101 which is a junction FET is clamped to the sum of the breakdown voltage of the Zener diode 149u and the base-emitter voltage of the transistor 123u. For this reason, there is an advantage that the gate voltage can be suppressed from being excessive even when a large current flows through the gate. In this embodiment, the diode 148u is a Schottky diode that clamps between the base and the collector so that the transistor 123u is not saturated.

  Other features are the same as those of the fourth embodiment and have the same effects.

  FIG. 12 shows this embodiment. In this embodiment, a large current is applied to turn on at a high speed, the transistor 120u is turned off after the turn-on, a transistor 124u is applied to pass a minute gate current to maintain the on state, and a negative voltage is applied between the gate and the source. The transistor 121u is turned off after a negative gate voltage sufficient to prevent the self-turn-on phenomenon that the power switch element is turned on erroneously at the time of turn-off, and the gate-source voltage necessary for maintaining the off state is applied. A feature is that a transistor 125u that is turned on to continue is provided. Resistors 167u and 168u are high resistances provided to suppress a leakage current for maintaining the on or off state, and the same drive as in FIG. 3 can be obtained.

  In the present embodiment, the signal processing circuit 118u is required, but there is an advantage that the power for charging and discharging the capacitor 180u required in the first embodiment is unnecessary. Reference numerals 171u and 172u denote power sources for the driving circuit. When the power semiconductor elements 101 and 102 are normally off type, both are positive power sources. However, when the power semiconductor elements 101 and 102 are normally on type elements, The voltage of the power source 171u is zero or negative. Other features are the same as those of the first embodiment and have the same effects.

  FIG. 13 shows this embodiment. This embodiment is an embodiment in which a protection circuit when a junction FET or a bipolar transistor is used as a power switch element is incorporated. When the power semiconductor element 101 is a junction FET or a bipolar transistor, the gate current (base current) increases when the temperature rises in an overload state. Therefore, this embodiment is characterized in that the gate current of the power semiconductor element 101 is monitored, and when the temperature rises in an overload state, the power switch element is cut off or the on-resistance is increased to prevent destruction. That is, when the gate current of the power semiconductor element 101 increases, the current of the transistor 126u that monitors the gate current of the power semiconductor element 101 also increases. For this reason, the current of the transistor 127u connected in the current mirror also increases, and the voltage at the terminal X increases. Normally, the voltage at the terminal X is set to be equal to the voltage at the terminal Y. Therefore, even if a signal for turning on the power semiconductor element 101 that is a junction FET is applied to the terminal 509, the power semiconductor element 101 that is a junction FET The drain current is suppressed. Thereby, there is an effect that destruction of the power switch element can be prevented.

  115u is a separation circuit composed of a filter and a switch circuit. The terminal X and the terminal Y are connected with a low impedance only during a period in which the protection circuit is activated, and for example, a power that is a junction FET is not desired in the protection circuit. When the semiconductor element 101 is turned on, a high impedance is set between the terminal X and the terminal Y. Note that the separation circuit 115 may be provided with a latch circuit that holds the state in which the protection circuit is operated even after the chip temperature is lowered, or a hysteresis circuit that holds the protection state only in a specified high temperature state. Other features are the same as those of the fourth embodiment and have the same effects.

  FIG. 14 shows this embodiment. In this embodiment, the gate-source voltage of the power semiconductor element 101 which is a junction FET is monitored, and when the gate-source voltage of the power semiconductor element 101 which is a junction FET becomes lower than the reference voltage 117u, the junction FET is The junction FET is protected by assuming that the temperature is higher than a specified temperature. 116u is a comparator.

  Other features are the same as those of the ninth embodiment, and the same effects as those of the sixth embodiment are obtained.

  As described above, in the invention of this embodiment, the field effect type power semiconductor element is described as an n-channel type. However, in the case of a p-channel type power semiconductor element, the polarity of the circuit and the polarity of the impurity layer are reversed. Needless to say, the same configuration can be realized and the same effect can be obtained.

FIG. 3 is an explanatory diagram of a semiconductor circuit of Example 1. FIG. 3 is an explanatory diagram of characteristics of a power FET used in the first embodiment. 4 is a gate waveform of the semiconductor circuit of Example 1. FIG. 2 is a schematic cross-sectional view and a schematic plan view of the semiconductor device of Example 1. FIG. 6 is an explanatory diagram of the characteristics of a power FET used in Example 2. FIG. 7 is a schematic cross-sectional view and a schematic plan view of a semiconductor device in Example 3. FIG. 7 is an explanatory diagram of a semiconductor circuit in an implementation column 4. The gate waveform of the semiconductor circuit of Example column 4. FIG. 10 is an explanatory diagram of a semiconductor circuit in Example column 5. FIG. 11 is an explanatory diagram of a semiconductor circuit in Example 6; FIG. 10 is an explanatory diagram of a semiconductor circuit in an implementation column 7. FIG. 10 is an explanatory diagram of a semiconductor circuit in an implementation column 8. FIG. 10 is an explanatory diagram of a semiconductor circuit in an embodiment column 9; FIG. 10 is an explanatory diagram of a semiconductor circuit in an implementation column 10;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Back surface drain metal layer, 2 ... High concentration n type drain semiconductor region, 3 ... Low concentration n type drain semiconductor region, 4a, 4b, 4c, 4d, 4e ... High concentration n type region, 5a, 5b, 5c, 5d ... Metal layer, 6a ... High concentration p-type gate region, 6b, 6c, 6d ... High concentration p-type semiconductor region, 7a ... Low concentration p-type gate region, 7b, 7c ... Low concentration p-type semiconductor region, 8 ... Insulating layer , 9a ... Source metal layer, 9b ... Gate metal layer, 101, 102 ... Power semiconductor element, 104u, 104v, 104w ... Load, 110, 111 ... Control circuit, 112 ... Level shift circuit, 115u, 115d ... Isolation circuit, 116u 116d, comparator circuit, 117u, 117d, reference voltage, 120u-128u, 120d-128d, transistor 113, 140u-148u, 140d-1 8d: Diode, 160u to 166u, 160d to 166d ... Resistor, 114, 180u, 180d ... Capacitor, 503 ... High voltage terminal, 504 ... Reference voltage terminal, 505u, 505v, 505w ... Output terminal, 507 ... High voltage side voltage terminal, 508u, 508d ... input terminals.

Claims (9)

A power FET having a drain terminal, a source terminal, a gate terminal for controlling an FET current flowing between the drain terminal and the source terminal, and a parasitic diode having the drain terminal as a cathode;
A control circuit for controlling the gate-source voltage of the power FET;
A load including an inductive element that supplies current from the power FET;
When the power FET is in an off drive state by the control circuit, a reverse voltage is applied between the drain and source of the power semiconductor FET, and at this time, the current component of the parasitic diode is changed from the source terminal to the drain terminal. A semiconductor circuit characterized in that the flowing FET current component is larger. The semiconductor circuit according to claim 1,
The control circuit has a high voltage terminal separated from the voltage of the source terminal by a first voltage and a low voltage terminal separated from the voltage of the source terminal by a second voltage;
An on-switching element is provided between the high-voltage terminal and the power FET gate terminal, and an off-switching element is provided between the low-voltage terminal and the power FET gate terminal,
When the off switch element is in the on state, the voltage of the drain terminal of the power FET is lowered from the voltage of the low voltage terminal, and a current flows from the source terminal to the drain terminal. A semiconductor circuit characterized in that a main current flowing through a terminal is an FET current of a power FET. A drain terminal; a source terminal; a gate terminal that controls an FET current flowing between the drain terminal and the source terminal; and a gate terminal of a power FET including a parasitic diode having the drain terminal as a cathode. , Connect the anode terminal of the first diode,
Connecting the cathode terminal of the first diode to the drain terminal;
A semiconductor circuit, wherein a forward voltage of the parasitic diode is higher than a forward voltage of the first diode. The semiconductor circuit according to claim 3,
A semiconductor circuit characterized in that a threshold voltage during reverse operation of the power FET is made lower than a forward voltage of the parasitic diode. In the semiconductor circuit according to claim 3 or 4,
The semiconductor circuit according to claim 1, wherein a breakdown voltage of the first diode is lower than a breakdown voltage between the drain and source. The semiconductor circuit according to any one of claims 3 to 5,
A semiconductor circuit, wherein the diode is a Schottky diode. In order to turn on the power FET, the switching element for turning on the power FET is turned on, and the gate-source voltage is charged in the positive direction via the capacitor and turned on.
In order to turn off a power FET, a switching element for turning off the power FET is turned on to charge a gate-source voltage in a negative direction through the capacitor. The semiconductor circuit according to claim 7,
A semiconductor circuit comprising a current path for supplying a gate current necessary for maintaining an ON state of the power FET to the power FET. 9. The semiconductor circuit according to claim 1, wherein the power FET is an FET using a wide band gap semiconductor element.

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